X40620

X40620 XICOR | Alldatasheet

Document overview

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Technical content

Xicor, Inc. 2000 Patents Pending 9900-3003.5 4/24/00 EP Characteristics subject to change without notice. 1 of 17 64K X40620 BLOCK DIAGRAM Command Decode and Control Logic HV Generation Timing and Control X Decoder Y Decoder Data Register Write ControlWP SCL SDA VCC V2FAIL (VCC) Control Signal V2MON RESET Logic Power on and Generation V2TRIP Reset Low Voltage VTRIP Reset & Watchdog Timebase Watchdog Timer Reset EEPROM Array (64Kbits) Dual Voltage CPU Supervisor with 64K Serial EEPROM

FEATURES

• Dual Voltage Detection and Reset Assertion —Three standard reset threshold settings. (3.1V/ —Adjust low voltage reset threshold voltages using special programming sequence —RESET signal valid down to V CC =1V
• Watchdog Timer (150ms)
• Power On Reset (150ms)
• Low Power CMOS —10µA typical standby current, watchdog on —400µA typical standby current, watchdog off
• 64kbit 2-Wire Serial EEPROM —1MHz serial interface speed —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• 2.5 to 3.7V Power Supply Operation
• 8-Lead TSSOP package

DESCRIPTION

The X40620 combines several functions into one device. The first is a dual voltage monitoring, power-on reset control, watchdog timer and 64Kbit serial EEPROM memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying voltage to V CC activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the set minimum Vtrip point. RESET is active until V CC returns to proper operating level and stabilizes. A second voltage monitor circuit (V2MON) tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. When the second monitored voltage drops below a preset TRIP voltage. V2F AIL is active until V2 returns to proper operating level and above the V2 TRIP voltage. Five common low voltage combinations are available, however, Xicor’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applica- tions requiring higher precision.

Characteristics subject to change without notice. 2 of 17 PACKAGE/PINOUTS PIN NAMES PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open col- lector outputs. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin should be tied HIGH at all time. (This WP pin is reserved for internal factory testing only). Reset Output (RESET RESET is an active LOW, open drain output which goes active whenever V CC falls below the minimum Vtrip sense level. It will remain active until V CC rises above the minimum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the select- able Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes. V2 Voltage Fail Output (V2FAIL V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the mini- mum V2trip sense level. It will remain active until V2MON rises above the minimum V2MON sense level. DEVICE OPERATION Power On Reset Application of power to the X40620 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscil- lator. When V CC exceeds the device V TRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage V CC (V1) Monitoring During operation, the X40620 monitors the V CC level and asserts RESET if supply voltage falls below a pre- set minimum V TRIP . The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until V CC returns and exceeds V TRIP for 200ms. When the internal low voltage detect circuitry senses that V CC is low, the following happens: – The RESET pin goes active. – Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to complete the operation. The low V CC threshold is typically set to 3.1V for a 2.5 to 3.7V operating range. LOW VOLTAGE V2 MONITORING The X40620 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset mini- mum V2 TRIP . The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impend- ing power failure. The V2F AIL signal remains active until the V CC drops below 1V. It also remains active until V2MON returns and exceeds V2 TRIP by 0.2V V SS Ground SDA Serial Data V CC Power SCL Serial Clock WP Write Protect V2MON Voltage monitor input RESET Low Voltage Detect Output V2FAIL V2 Voltage Fail Output WP VCC V2FAIL SCL VSS V2MON SDA RESET 8L TSSOP

Characteristics subject to change without notice. returns and exceeds it’s minimum voltage. dog timer period is set at 150msec. X40620; READ and WRITE of the memory arrays. The basic sequence is illustrated in Figure 1. reset and enter into a standby mode. Figure 1. X40620 Device Operation

Characteristics subject to change without notice. 6 of 17 VTRIP/V2TRIP Programming Apply 5V to VCC or V2MON Decrement VCC RESET goes active? Measured V(2)TRIP - Desired V(2)TRIP DONE Execute Sequence Reset VTRIP/V2TRIP Set VCC = VCC Applied = Desired VTRIP OR Execute Sequence Set VTRIP , V2TRIP New VCC or V2MON Applied = Old VCC V2MON Applied + Error (<50mV Step) Execute Sequence Reset V2TRIP, VTRIP New VCC/V2MON Applied = Old VCC Applied—Error Error < 0 Error = 0 YES NO Error > 0 Set V2MON = V2MON Applied = Desired V2TRIP , VCC>=V2Trip or V2MON or V2FAIL pin Recycle VCC Power

the nonvolatile write cycle. Figure 9. Memory Array Programming

• • • Polling Write ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X40620 initiates the internal nonvolatile write cycle. In order to take advan- tage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start con- dition followed by the new command code of 8 bits (1st byte of the protocol.) If the X40620 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has com- pleted, an “ACK” will be returned and the host can then proceed with the rest of the protocol. Data ACK Polling Sequence ACK Returned? Issue New Command Code Write Sequence Completed Enter Ack Polling Issue Start NO YES Proceed

Characteristics subject to change without notice. 10 of 17 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C +70°C Extended –20°C +85°C Device Supply Voltage Limits X40620 2.5V to 3.7V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) CAPACITANCE (TA = +25°C, F = 1MHZ, VCC = 3V) Notes: (1) Must perform a stop command after a read command prior to measurement (2) V IL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Units Test ConditionsMin. Max. ICC1 VCC Supply Current (Read) 1 mA f SCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor V2MON = VCC ICC2 (3) VCC Supply Current (Write) 3 mA f SCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor RST = VSS ISB1 (1) VCC Supply Current (Standby) 50 µA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 1MHz, fSDA = 400 KHz ISB2 (1) VCC Supply Current (Standby) 1 µA V SDA = VSCL = V2MON = VCC Other = GND or VCC–0.3V ILI Input Leakage Current 10 µA V IN = VSS to VCC ILO Output Leakage Current 10 µA V OUT = VSS to VCC VIL1 (2) Input LOW Voltage –0.5 V CC x 0.3 V V CC = 3.0V VIH1 (2) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V V CC = 3.0V VIL2 (2) Input LOW Voltage –0.5 V CC x 0.1 V V CC = 3.0V VIH2 (2) Input HIGH Voltage V CC x 0.9 V CC + 0.5 V V CC = 3.0V VOL Output LOW Voltage 0.4 V I OL = 3mA Symbol Test Max. Units Conditions COUT (3) Output Capacitance (SDA) 8 pF V I/O = 0V CIN (3) Input Capacitance (WP, SCL, V2MON) 6 pF V IN = 0V

Characteristics subject to change without notice. 11 of 17 EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS 1.3KΩ Output 100pF Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 Output load 100pF AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) RESET AC SPECIFICATIONS Nonvolatile Write Cycle Timing Notes: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (1) Max. Units fSCL SCL Clock Frequency 0 1000 KHz tIN Pulse width of spikes which must be suppressed by the input filter 10 ns tAA SCL LOW to SDA Data Out Valid 0.05 0.55 µs tBUF Time the bus must be free before a new transmit can start 0.5 µs tLOW Clock LOW Time 0.6 µs tHIGH Clock HIGH Time 0.4 µs tSU:STA Start Condition Setup Time 0.25 µs tHD:STA Start Condition Hold Time 0.25 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.25 µs tDH Data Output Hold Time 0 100 ns tR SDA and SCL Rise Time (10% to 90% of VCC) 10 100 ns tF SDA and SCL Fall Time 10 100 ns Symbol Parameter Min. Typ. (1) Max. Units tWC (1) Write Cycle Time 5 10 mS

Characteristics subject to change without notice. 12 of 17 TIMING DIAGRAMS Bus Timing Write Cycle Timing GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition 5040302010 Bus capacitance in pF Pull Up Resistance in KΩ RMIN RPMAX For VIH = 0.9VCC RMIN VCCMAX 0.4– IOLMIN VIH Vcc 1 e tRMAX– RPMAX CBUS RPMAX tR tRMAX = maximum allowable SDA rise time 100ns Max Rise Time

Characteristics subject to change without notice. 13 of 17 POWER-UP AND POWER-DOWN TIMING RESET Output Timing V2FAIL Output Timing Notes: (5) This parameter is periodically sampled and not 100% tested. (6) Typical values not tested. Symbol Parameter Min. Typ. Max. Units VTRIP RESET Trip Point Voltage 2.4 – 3.5 V V2TRIP V2FAIL Trip Point Voltage 1.7 – 3.5 V VTH VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV V2TA V2TRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV tPURST Power-up Reset Timeout 75 150 225 ms tDVC (5) Detect VCC Low Voltage to Reset Output (VCC = 2.3V) 65 µs tDVB (5) Detect V2MON Low Voltage to Reset Output (VCC = 2.5-3.7V) 100 µs tFV (5) VCC Fall Time 100 µs tRV (5) VCC Rise Time 100 µs tFB (5) V2MON Fall Time 500 ns tRB (5) V2MON Rise Time 500 ns VRVALID Reset Valid VCC 1V VCC tPURST tRV tFV tDVC RESET

0 Volts

Characteristics subject to change without notice. 14 of 17 Start Bit vs. RESET Timing RESET Output Timing Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period 75 150 225 ms tWDR SDA LOW duration (Reset the Watchdog) 400 ns tRST Reset Timeout 75 150 225 ms SDA tWDR RESET tWDO tRST SCL tSU:STA tSU:STO tWDO tRST

Characteristics subject to change without notice. 15 of 17 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical

Characteristics subject to change without notice. 16 of 17

Ordering Information

Notes: Tolerance for VTRIP and V2TRIP are +/-5% VCC Range V TRIP V2TRIP Package Operating Temperature Range Part Number -20°C–85°C X40620V8E-3.1 -20°C–85°C X40620V8E- 3.1A -20°C–85°C X40620V8E-2.9

Characteristics subject to change without notice. 17 of 17 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Part Mark Convention 8-Lead TSSOP EYWW XXXX XX

4062 AR =

4062 AS =

4062 AT =

4062 AU =

4062 AV =

4062 AW =

2.6 2.6 1.7 1.7 2.3 2.3 0 to 70°C -20 to 85°C 0 to 70°C -20 to 85°C 0 to 70°C -20 to 85°C 3.1 3.1 3.1 3.1 2.9 2.9