X40430 XICOR | Alldatasheet

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REV 1.2.3 11/28/00 Characteristics subject to change without notice. 1 of 24 www.xicor.com Preliminary Information 4kbit EEPROM X40430/X40431 Triple Voltage Monitor with Integrated CPU Supervisor

FEATURES

  • Triple voltage detection and reset assertion —Three standard reset threshold settings 2.9V/1.7V/2.4V) —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to V CC = 1V —Monitor three voltages or detect power fail
  • Fault detection register
  • Selectable power on reset timeout
  • Selectable watchdog timer interval
  • Debounced manual reset input
  • Low power CMOS —30µA typical standby current, watchdog on —10µA typical standby current, watchdog off
  • 4Kbits of EEPROM —16 byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
  • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block lock protect 0, 1/4, 1/2, all of EEPROM
  • 400kHz I C interface
  • 2.4V to 5.5V power supply operation
  • Available packages —14-lead SOIC, TSSOP

DESCRIPTION

The X40430/31 combines power-on reset control, watchdog timer, supply voltage supervision, secondary and third voltage supervision, manual reset, and Block Lock protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to V CC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V TRIP1 point. RESET/ RESET is active until V CC returns to proper operating level and stabilizes. A second and third voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Xicor’s unique circuits allows the threshold for either voltage monitor to be repro- grammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM V3FAIL V2FAIL WDO MR LOWLINE RESET RESET X40430 X40431 V3 MonitorLogic V2 MonitorLogic VTRIP2 Fault Detection Register Status Register EEPROM Array Data Register Command Decode Test & Control Logic Power on, Manual Reset Low Voltage Reset GenerationVCC Monitor Logic V3MON V2MON SDA WP SCL VCC (V1MON) VTRIP3 VTRIP1 Watchdog and Reset Logic

X40430/X40431 – Preliminary Information Characteristics subject to change without notice. 2 of 24REV 1.2.3 11/28/00 www.xicor.com A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing opera- tion on an I C bus. The device utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION PIN DESCRIPTION Pin Name Function

1 V2FAIL

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V TRIP2 and goes HIGH when V2MON exceeds V TRIP2 . There is no power up reset delay circuitry on this pin.

2 V2MON

V2 Voltage Monitor Input. When the V2MON input is less than the V TRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V SS or V CC when not used.

3 LOWLINE

Detect. This CMOS output signal goes LOW when V CC < V TRIP1 and goes high when V CC > V TRIP1 4N C No connect. 5M R Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the t PURST thereafter.

6 RESET /

RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever V CC falls below V TRIP voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (t PURST ) on power up. It will also stay active until manual reset is released and for t PURST thereafter. RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever V CC falls below V TRIP voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (t PURST ) on power up. It will also stay active until manual reset is released and for t PURST thereafter. SS Ground V3MON VSS VCC SDA SCL LOWLINE NC RESET V2MON MR WP V3F AIL WDO V2FAIL V3MON VCC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL X40430 X40431 14-Pin SOIC, TSSOP 14-Pin SOIC, TSSOP

Characteristics subject to change without notice.

8 SDA

requires a pull up resistor and the input buffer is always active (not gated).

9 SCL

The Serial Clock controls the serial bus timing for data input and output. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor.

11 V3MON

12 V3FAIL

. There is no power up reset delay circuitry on this pin.

13 WDO

active. This signal provides several benefits. to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power up. Figure 1. Connecting a Manual Reset Push-Button

Characteristics subject to change without notice. Figure 2. Two Uses of Multiple Voltage Monitoring Notice: No external components required to monitor three voltages.

brought LOW to complete the operation. nal value of 1.7V or lesser. nonvolatile and do not change when power is removed. process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7. Figure 5. Sample VTRIP Reset Circuit

Figure 6. VTRIP Set/Reset Sequence (X = 1, 2, 3) tile latch that powers up in the LOW (disabled) state. zeroes to the other bits of the control register. operation immediately after the stop condition.

X40430/X40431 – Preliminary Information BP1, BP0: Block Protect Bits (Nonvolatile) The Block Protect Bits, BP1 and BP0, determine which blocks of the array are write protected. A write to a pro- tected block of memory is ignored. The block protect bits will prevent write operations to one of eight seg- ments of the array. PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power up times are shown in the following table. WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write one byte value to the Control Register that has all the control bits set to the desired state. The Con- trol register can be represented as qxys t01r in binary, where xy are the WD bits, and st are the BP bits and qr are the power up bits. This operation pro- ceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys t11r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, BP1 and BP0 bits remain unchanged. Writing a second byte to the con- trol register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Fault Detection Register (FDR) The Fault Detection Register provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR. BP1 BP0 Protected Addresses (Size) Array Lock 0 0 None None 0 1 180h – 1FFh (128 bytes) Upper 1/4 (Q4) 1 0 100h – 1FFh (256 bytes) Upper 1/2 (Q3,Q4) 1 1 000h – 1FFh (512 bytes) Full Array (All) PUP1 PUP0 Power on Reset Delay ( tPURST) 0 0 50ms 0 1 200ms 1 0 400ms 1 1 800ms WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled 7 65432 1 0 LV1F LV2F LV3F WDF MRF 0 0 0

Figure 10. Byte Write Sequence goes back to ‘0’ on the same page. data overwrites the previous data, one byte at a time. Figure 11. Page Write Operation Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

5 Bytes

7 Bytes

edge, and data transfer sequence.

tents of the array will not be effected. device initiates the internal high voltage cycle. host can then proceed with the read or write operation. dom Reads, and Sequential Reads. operation for initialization. address, acknowledge, and data transfer sequence. Figure 13. Acknowledge Polling Sequence the ninth clock cycle and then issue a stop condition. address, acknowledge, and data transfer sequence.

is undefined on a power up condition. – The device is in the low power standby state. – SDA pin is the input mode. Signal is active for tPURST. – The WEL bit must be set to allow write operations. the array and all the Register. Figure 16. Sequential Read Sequence

X40430/X40431 – Preliminary Information ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Version Supply Voltage Limits -A or -B 2.7V to 5.5V -C 2.4V to 3.6V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions ICC1 (1) Active Supply Current (VCC) Read 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz ICC2 (1) Active Supply Current (VCC) Write 3.0 mA ISB1 (1) Standby Current (VCC) AC (WDT off) 10 30 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz ISB2 (2) Standby Current (VCC) DC (WDT on) 30 50 µA V SDA = VSCL = VCC Others = GND or VCC ILI Input Leakage Current (SCL, MR, WP) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL (3) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 VCC x 0.3 V VIH (3) Input HIGH Voltage (SDA, SCL, MR, WP) VCC x 0.7 VCC + 0.5 V VHYS Schmitt Trigger Input Hysteresis

  • Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RESET/ RESET, LOWLINE, V2FAIL, V3FAIL, WDO) IOL = 1.8mA (2.4-3.6V) VOH Output (RESET, LOWLINE) HIGH Voltage VCC – 0.8 VCC – 0.4 VI OH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.4-3.6V) VCC Supply VTRIP1 VCC Trip Point Voltage 2.0 4.75 V VLVRH Low VCC RESET Hysteresis 60 mV

X40430/X40431 – Preliminary Information Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t WC after a stop that ini- tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, V CC = 3V CAPACITANCE Note: (1) This parameter is not 100% tested. Second Supply Monitor IV2 V2MON Current 15 µA VTRIP2 V2MON Trip Point Voltage 1.7 4.75 V VV2H V2MON Hysteresis 60 mV Third Supply Monitor IV3 V3MON Current 15 µA VTRIP3 V3MON Trip Point Voltage 1.7 4.75 V VV3H V3MON Hysteresis 60 mV Symbol Parameter Max. Unit Test Conditions COUT (1) Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO) 8p FV OUT = 0V CIN (1) Input Capacitance (SCL, WP, MR) 6 pF V IN = 0V D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS) SYMBOL TABLE Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON, V3MON 4.6KΩ RESET 30pF 2.06KΩ V2FAIL, VCC 4.6KΩ 30pF WDO V3FAIL Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INPUTS OUTPUTS to HIGH

X40430/X40431 – Preliminary Information A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF . TIMING DIAGRAMS Bus Timing Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA

X40430/X40431 – Preliminary Information WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Power Fail Timings Symbol Parameter Min. Typ. Max. Unit tWC (1) Write Cycle Time 5 10 ms tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition V2MON or V2FAIL or tR tF tRPDX VRVALID V3MON V3FAIL LOWLINE or VCC VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3

X40430/X40431 – Preliminary Information RESET/RESET/MR Timings LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS Symbol Parameters Min. Typ. Max. Unit tRPD1 tRPDL VTRIP1 to RESET/RESET (Power down only) VTRIP1 to LOWLINE 10 20 µs t LR LOWLINE to RESET/RESET delay (Power down only) [= tRPD1-tRPDL] 500 ns tRPDX VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL 10 20 µs tPURST Power On Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 PUP1=1, PUP0=0 PUP1=1, PUP0=1 200 400 800 ms ms ms ms t F VCC, V2MON, V3MON, Fall Time 20 mV /µs tR VCC, V2MON, V3MON, Rise Time 20 mV /µs VRVALID Reset Valid VCC 1V tMD MR to RESET/ RESET delay (activation only) 500 ns tin1 Pulse width for MR 5µ s tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 1.4 200 s ms ms t RST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID MR tMD tIN1

X40430/X40431 – Preliminary Information Watchdog Time Out For 2-Wire Interface VTRIPX Set/Reset Conditions < tWDO tRST WDO SDA Start tWDO tRST SCL Timer Start tRSP Timer Restart Timer Start Start SCL SDA VCC/V2MON/V3MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 0Dh* sets VTRIP1 sets VTRIP2 sets VTRIP3 01h* 09h* 03h* 0Bh* 0Fh* resets VTRIP3 resets VTRIP2 resets VTRIP1 Start * all others reserved 00h

X40430/X40431 – Preliminary Information VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN VTRIPX Set Voltage Range 2.0 4.75 V Vta1 Initial VTRIPX Set Voltage accuracy (VCC applied—V TRIPX) -0.1 +0.4 V Vta2 Subsequent VTRIPX Program Voltage accuracy [(VCC applied—V ta1)–VTRIPX) -25 +25 mV Vtr VTRIPX Set Voltage repeatability (Successive program operations.) -25 +25 mV Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs

X40430/X40431 – Preliminary Information PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.020 (0.51) Pin 1 Pin 1 Index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-Lead Plastic Small Outline Gullwing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"T ypical 0.050"Typical 0.030" Typical

14 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45°

X40430/X40431 – Preliminary Information PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X40430/X40431 – Preliminary Information Characteristics subject to change without notice. 24 of 24 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2000 Patents Pending REV 1.2.3 11/28/00 www.xicor.com

ORDERING INFORMATION

-40oC–85oC X40430S14I-A X40431S14I-A 14L TSSOP 0 oC–70oC X40430V14-A X40431V14-A -40oC–85oC X40430V14I-A X40431V14I-A -40oC–85oC X40430S14I-B X40431S14I-B 14L TSSOP 0 oC–70oC X40430V14-B X40431V14-B -40oC–85oC X40430V14I-B X40431V14I-B -40oC–85oC X40430S14I-C X40431S14I-C 14L TSSOP 0 oC–70oC X40430V14-C X40431V14-C -40oC–85oC X40430V14I-C X40431V14I-C 14-Lead TSSOP EYWW 40430X 14-Lead SOIC X40430SX EYWW A, B, or CA, B, or C