X40420 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Renesas
  • PDF pages: 25

Technical content

FN8117 Rev 1.00 Page 1 of 25 May 25, 2006 FN8117 Rev 1.00 May 25, 2006 X40420, X40421 4kbit EEPROM Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch DATASHEET

FEATURES

  • Dual voltage detection and reset assertion —Three standard reset threshold settings —VTRIP2 programmable down to 0.9V —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to VCC = 1V —Monitor two voltages or detect power fail
  • Battery switch backup OUT: 5mA to 50mA from VCC; or 250µA from VBATT
  • Fault detection register
  • Selectable power-on reset timeout
  • Selectable watchdog timer interval (25ms, 200ms, 1.4s, off)
  • Debounced manual reset input
  • Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off —1µA typical battery current in backup mode
  • 4Kbits of EEPROM —16 byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
  • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block lock protect 0 or 1/2, of EEPROM
  • 400kHz 2-wire interface
  • 2.7V to 5.5V power supply operation
  • Available packages —14 Ld SOIC, TSSOP
  • Pb-free plus anneal available (RoHS compliant)
  • Monitor voltages: 5V to 1.6V
  • Memory security
  • Battery switch backup OUT 5mA to 50mA

APPLICATIONS

  • Communications equipment —Routers, hubs, switches —Disk arrays
  • Industrial systems —Process control —Intelligent instrumentation
  • Computer systems —Desktop computers —Network servers X40420, X40421

DESCRIPTION

The X40420, X40421 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary supervision, manual reset, and Block Lock ™ protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to V CC activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscilla- tor to stabilize before the processor can execute code. BLOCK DIAGRAM Standard VTRIP1 Level Standard V TRIP2 Level Suffix See “Ordering Information” for more details For Custom Settings, call Intersil. V2FAIL WDO MR LOWLINE RESET RESET X40420 X40421 V2 MonitorLogic VTRIP2 Fault Detection Register Status Register EEPROM Array Data Register Command Decode Test & Control Logic Power-on, Manual Reset Low Voltage Reset GenerationVCC Monitor Logic V2MON SDA WP SCL VCC (V1MON) Watchdog and Reset Logic System Switch Battery VBATT VOUT BATT-ON VTRIP1 VOUT VOUT VOUT NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X40420, X40421 FN8117 Rev 1.00 Page 2 of 25 May 25, 2006

Ordering Information

NUMBER* WITH RESET PART MARKING PART NUMBER* WITH RESET PART MARKING MONITORED VCC SUPPLIES VTRIP1 RANGE VTRIP2 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. # X40420S14-C X40420S C X40421S14-C X40421S C 1.6 to 3.6 2.9V ±50mV 1.6 V ±50mV 0 to 70 14 Ld SOIC (150 mil) MDP0027 X40420S14I-C X40420S IC X40421S14I-C X40421S IC -40 to +85 14 Ld SOI C (150 mil) MDP0027 X40420V14-C X4042 0VC X40421V14-C X40421V C 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40420V14I-C X4042 0VIC X40421V14I-C X40421V IC -40 to +85 14 Ld TSS OP (4.4mm) M14.173 X40420S14-B X40420S B X40421S14-B X40421S B 2.6 to 5.5 4.6V ±50mV 2.6 V ±50mV 0 to 70 14 Ld SOIC (150 mil) MDP0027 X40420S14Z-B (Note) X40420S ZB X40421S14Z-B (Note) X40421S ZB 0 to 70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40420S14I-B X40420S IB X40421S14I-B X40421S IB -40 to +85 14 Ld SOI C (150 mil) MDP0027 X40420S14IZ-B (Note) X40420S ZIB X40421S14IZ-B (Note) X40421S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40420V14-B X4042 0VB X40421V14-B X40421V B 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40420V14Z-B (Note) X4042 0VZB X40421V14Z-B (Note) X40421V ZB 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40420V14I-B X4042 0VIB X40421V14I-B X40421V IB -40 to +85 14 Ld TSS OP (4.4mm) M14.173 X40420V14IZ-B (Note) X4042 0VZIB X40421V14IZ-B (Note) X40421V ZIB -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40420S14-A X40420S A X40421S14-A X40421S A 2.9 to 5.5 2.9V ±50mV 0 t o 70 14 Ld SOIC (150 mil) MDP0027 X40420S14Z-A (Note) X40420S ZA X40421S14Z-A (Note) X40421S ZA 0 to 70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40420S14I-A X40420S IA X40421S14I-A X40421S IA -40 to +85 14 Ld SOI C (150 mil) MDP0027 X40420S14IZ-A (Note) X40420S ZIA X40421S14IZ-A (Note) X40421S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40420V14Z-A (Note) X4042 0VZA X40421V14Z-A (Note) X40421V ZA 0 to 70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X40420V14-A X4042 0VA X40421V14-A X40421V A 0 to 70 14 Ld TSSOP (4.4mm) M14.173 X40420V14I-A X4042 0VIA X40421V14I-A X40421V IA -40 to +85 14 Ld TSS OP (4.4mm) M14.173 X40420V14IZ-A (Note) X4042 0VZIA X40421V14IZ-A (Note) X40421V ZIA -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X40420, X40421 FN8117 Rev 1.00 Page 3 of 25 May 25, 2006 Low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V TRIP1 point. RESET/RESET is active until V CC returns to proper operating level and stabilizes . A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil’s unique circuits a llows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applica- tions requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. A battery switch circuit compares V CC with V BATT input and connects VOUT to whichever is higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X40420, X40421 can drive 50mA from V CC to 250µA from V BATT. The device only switches to V BATT when V CC drops below the low V CC voltage threshold and VBATT. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s Block Lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing oper- ation on a two-wire bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION Example Application Unreg. Supply REG Manual Reset Enable Addr SRAM Addr NMI IRQ RESET I2C uC VCC BATT-ON VCC VBATT VOUT V2MON V2FAIL VDO RESET MR SCL SDA X40420, X40421 VBATT VSS VCC SDA SCL LOWLINE WDO RESET V2MON MR WP VOUT BATT-ON V2FAIL VBATT VCC SDA SCL WP VOUT BATT-ON VSS LOWLINE WDO RESET V2MON MR V2FAIL X40420 X40421 14-Pin SOIC, TSSOP 14-Pin SOIC, TSSOP PIN DESCRIPTION Pin Name Function 1V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 2V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. 3L O W L I N E Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1. When VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor. 4W D O WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active. 5M R Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up resistor.

X40420, X40421 FN8117 Rev 1.00 Page 4 of 25 May 25, 2006

6 RESET /

RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. 7V SS Ground 8S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor. (>10M typical) 11 V BATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not used, connect V BATT to ground. 12 V OUT Output Voltage. (V) VOUT = VCC if VCC > VTRIP1. IF VCC < VTRIP1 then VOUT = VCC if VCC > VBATT + 0.03V else VOUT = VBATT (ie if VCC < VBATT - 0.03V) Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the switchover voltage. A capacitance of 0.1µF must be connected to VOUT to ensure stability. 13 BATT-ON Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current requirements are greater than 50mA. The purpose of this output is to drive an external transistor to get higher operating currents when the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply enough voltage and current to keep SRAM devices from losing their data–there is no communication at this time. 14 V CC Supply Voltage PIN DESCRIPTION (Continued) Pin Name Function

Note: This operation does not corrupt the memory array. state and draw much less current than in their active mode. changing the Block Lock and Watchdog Timer settings. and do not change when power is removed. required to end this operation. Figure 5. Sample V tion to the device is allowed.

Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2) of the control register) or un til the part powers up again. immediately after the stop condition.

X40420, X40421 FN8117 Rev 1.00 Page 9 of 25 May 25, 2006 BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. Th e block protect bit will prevent write operations to half the array segment. PUP1, PUP0: Power-uppower-up Bits (Nonvolatile) The Power-up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power-up times are shown in the following table. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watch- dog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write a one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, and st are the BP bits and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a non- volatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write oper- ation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. To illustrate, a sequence of wr ites to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolat ile bits unchanged and the RWEL bit remains set. Note: 1. t PURST is set to 200ms as factory default. 2. Watchdog timer bits are shipped disabled. Fault Detection Register (FDR) The Fault Detection Register provides the user the sta- tus of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this fault detection register. BP Protected Addresses (Size) Memory Array Lock

0 None None

1 100h – 1FFh (256 bytes) Upper Half of Memory Array PUP1 PUP0 Power-on Reset Delay (tPURST) 0 0 50ms 0 1 200ms (default) 1 0 400ms 1 1 800ms WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory default) 7 65432 1 0 LV1F LV2F 0 WDF MRF 0 0 0

Figure 10. Byte Write Sequence Figure 11. Page Write Operation Figure 12. Writing 12 bytes to a 16-byte Page Starting at Location 10

6 Bytes

ceed with the read or write operation. See Figure 13. Reads, and Sequential Reads. acknowledge, and data transfer sequence. Figure 13. Acknowledge Polling Sequence clock cycle and then issue a stop condition. edge, and data transfer sequence.

needs to read, but is not ready for the data. acknowledge and then issuing a stop condition. edge and data transfer sequence. control register and fault detection register. Figure 14. Current Address Read Sequence

X40420, X40421 FN8117 Rev 1.00 Page 16 of 25 May 25, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this spec ification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS *See ordering Info Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Version Chip Supply Voltage Monitored Voltages* -A or -B 2.7V to 5.5V 2.6 to 5.5V -C 2.7V to 5.5V 1.6V to 3.6V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (5) Max. Unit Test Conditions ICC1(1) Active Supply Current (VCC) Read (Excludes IOUT) 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHzICC2(1) Active Supply Current (VCC) Write Non Volatile Memory (Excludes IOUT) 3.0 mA ISB1(1)(7) Standby Current (VCC) AC (WDT off) 6 10 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz ISB2(2)(7) Standby Current (VCC) DC (WDT on) 25 30 µA V SDA = VSCL = VCC Others = GND or VCC IBATT1(3)(7) VBATT Current (Excludes IOUT)0 . 4 1 µ A V OUT = VCC IBATT2(7) VBATT Current (Excludes IOUT) (Battery Backup Mode) 6µ A V BATT = 2.8V VOUT = Open VOUT1(7) Output Voltage (VCC > VBATT + 0.03V or VCC > VTRIP1) VCC-0.05V VCC-0.5V VI OUT = 5mA (4.5-5.5V) IOUT = 50mA (4.5-5.5V) VOUT2(7) Output Voltage (VCC < VBATT – 0.03V and VCC < VTRIP1) {Battery Backup} VBATT-0.2 V I OUT = 250µA VOLB Output (BATT-ON) LOW Voltage 0.4 V I OL = 3.0mA (4.5-5.5V) VOHB Output (BATT-ON) HIGH Voltage V OUT-0.8 V I OH = -0.4mA (4.5-5.5V) VBSH(7) Battery Switch Hysteresis (VCC < VTRIP1) -30 mV Power-up Power-down ILI Input Leakage Current (SCL, MR, WP) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2FAIL, WDO, RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 VCC x 0.3 V VIH(3) Input HIGH Voltage (SDA, SCL, MR, WP) VCC x 0.7 VCC + 0.5 V

X40420, X40421 FN8117 Rev 1.00 Page 17 of 25 May 25, 2006 Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, exc ept those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) Negative numbers indicate charging current, positive numbers indicate discharge current. (4) V IL Min. and VIH Max. are for reference only and are not tested. (5) At 25°C, V CC = 3V. (6) See ordering information for standard programming leve ls. For custom programming levels, contact factory. (7) Based on characterization data only. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2) VHYS(7) Schmitt Trigger Input Hysteresis

  • Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RESET/ RESET, LOWLINE, V2FAIL, WDO) IOL = 1.8mA (2.4-3.6V) VCC Supply VTRIP1(6) VCC Reset Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 A, B Version 2.85 2.9 2.95 C Version t RPDL(7) VTRIP1 to LOWLINE 5µ S Second Supply Monitor VTRIP2(6) V2MON Reset Trip Point Voltage Range 0.9 3.5 V 2.85 2.9 2.95 A Version 2.55 2.6 2.65 B Version 1.55 1.6 1.65 C Version t RPD2(7) VTRIP2 to V2FAIL 5µ S D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (5) Max. Unit Test Conditions –VREF tRPDX = 5µs worst case Output VxMON R C V = 100mV V VREF

X40420, X40421 FN8117 Rev 1.00 Page 18 of 25 May 25, 2006 CAPACITANCE Note: (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS SYMBOL TABLE Symbol Parameter Max. Unit Test Conditions COUT(1) Output Capacitance (SDA, RESET, RESET/LOWLINE, V2FAIL, WDO) 8p F V OUT = 0V CIN(1) Input Capacitance (SCL, WP) 6 pF V IN = 0V Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON 4.6k RESET 30pF 2.06k V2FAIL VOUT 4.6k 30pF WDO/LOWLINE Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INP UTS OUTPUTS

X40420, X40421 FN8117 Rev 1.00 Page 19 of 25 May 25, 2006 A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter 400kHz UnitMin. Max. fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA

X40420, X40421 FN8117 Rev 1.00 Page 20 of 25 May 25, 2006 WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Power Fail Timings Symbol Parameter Min. Typ. (1) Max. Unit tWC(1) Write Cycle Time 5 10 ms tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition V2MON V2FAIL tR tF tRPDX VRVALID LOWLINE or VCC or VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 1, 2

X40420, X40421 FN8117 Rev 1.00 Page 21 of 25 May 25, 2006 RESET/RESET/MR Timings LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Note: (1) Based on characterization data. Symbol Parameters Min. Typ. Max. Unit tRPD1(1) tRPDL VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE 5µ s tLR(1) LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL] 500 ns tRPD2(1) VTRIP2 to V2FAIL 5µ s tPURST Power-on Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory default) PUP1=1, PUP0=0 PUP1=1, PUP0=1 (1) 200 400(1) 800(1) ms ms ms ms t F VCC, V2MON Fall Time 20 mV µs tR VCC, V2MON Rise Time 20 mV µs VRVALID Reset Valid VCC 1V t MD MR to RESET/ RESET delay (activation only) 500 ns tin1 Pulse width Suppression Time for MR 50 ns tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1=1, WD0=1 (factory default) 1.4 (1) 200(1) OFF s ms ms t RST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID MR tMD

X40420, X40421 FN8117 Rev 1.00 Page 22 of 25 May 25, 2006 Watchdog Time Out For 2-Wire Interface VTRIPX Set/Reset Conditions < tWDO tRST WDO SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1) SCL SDA VCC/V2MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 sets VTRIP1 sets VTRIP2 01h* 09h* 03h* 0Bh* resets VTRIP2 resets VTRIP1 Start * all others reserved 00h

X40420, X40421 FN8117 Rev 1.00 Page 23 of 25 May 25, 2006 VTRIP1, VTRIP2 Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range 0.9 3.5 V Vtv VTRIPX Set Voltage variation after programming (0-75°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs VTRIPX programming parameters are periodically sampled and are not 100% tested.

X40420, X40421 FN8117 Rev 1.00 Page 24 of 25 May 25, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8117 Rev 1.00 Page 25 of 25 May 25, 2006 X40420, X40421 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7  0o 8o 0o 8o - Rev. 2 4/06