X40415S8-B

X40410 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Intersil Corporation
• PDF pages: 24

Technical content

FN8116 Rev 0.00 Page 1 of 24 March 28, 2005 FN8116 Rev 0.00 March 28, 2005 X40410, X40411, X40414, X40415 4kbit EEPROM Dual Voltage Monitor with Integrated CPU Supervisor DATASHEET

FEATURES

• Dual voltage detection and reset assertion —Standard reset threshold settings See Selection table on page 2. —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to VCC = 1V —Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms,1.4s, off)
• Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off
• 4Kbits of EEPROM —16 byte page write mode —5ms write cycle time (typical)
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block lock protect none or 1/2 of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages —8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Memory Security
• Independent Core Voltage Monitor

APPLICATIONS

• Communication Equipment —Routers, Hubs, Switches —Disk Arrays, Network Storage
• Industrial Systems —Process Control —Intelligent Instrumentation
• Computer Systems —Computers —Network Servers

DESCRIPTION

The X40410/11/14/15 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary voltage supervision, and Block Lock ™ pro- tect serial EEPROM in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying voltage to VCC activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscilla- tor to stabilize before the processor can execute code. BLOCK DIAGRAM V2FAIL WDO RESET RESET X40410/14 X40411/15 Fault Detection Register Status Register EEPROM Array Data Register Command Decode Test & Control Logic Power-on, Low Voltage Reset Generation V2MON SDA SCL VCC (V1MON) -User Programmable Threshold Reset Logic VTRIP1 User Programmable VTRIP2 Watchdog Timer and Reset Logic V2MON VCC or *X40410/11= V2MON* X40414/15 = VCC NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 2 of 24 March 28, 2005 Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum VTRIP1 point. RESET/RE- SET is active until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Inter- sil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to re start a timer within a selectable time out interval, the devi ce activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing opera- tion on an I 2C® bus. The device utilizes Intersil’s proprietary Direct Write ™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Triple Voltage Monitors *Voltage monitor requires VCC to operation. Others are independent of VCC. PIN CONFIGURATION Device Expected System Voltages Vtrip1(V) Vtrip2(V) POR (system) X4040/11 5V; 3V or 3.3V 5V; 3V 3V; 3.3V; 1.8V 2.0–4.75* 4.55–4.65* 4.35–4.45* 2.85–2.95* 1.70–4.75 2.85–2.95 2.55–2.65 1.65–1.75 RESET = X40410 RESET = X40411 X40414/15 3V; 3.3V; 1.5V 3V; 1.5V 3V or 3.3V; 1.1 or 1.2V 2.0–4.75* 2.85–2.95* 2.55–2.65* 2.85–2.95* 0.90–3.50* 1.25–1.35* 1.25–1.35* 0.95–1.05* RESET = X40414 RESET = X40415 SDA VCC RESET/RESET VSS V2MON SCL WDO V2FAIL RESET/RESET SCL VSS SDA V2FAIL V2MON WDO VCC X40410/14, X40411/15 X40410/14, X40411/15 8-Pin SOIC 8-Pin TSSOP PIN DESCRIPTION Pin Name FunctionSOIC TSSOP 13 V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 24 V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V SS or VCC when not used.The V2MON comparator is supplied by V2MON (X40410/11) or by VCC Input (X40414/15).

35 R E S E T /

RESET Output. (X40411/15) This is an active LOW, open drain output which goes active whenever VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter. RESET Output. (X40410/14) This is an active HIGH CMOS output which goes active whenever VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.

46 V SS Ground

57 S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transi- tion within the watchdog time out period results in WDO going active.

active. This signal provides several benefits. operate with insufficient voltage. prior to initialization of the circuit. reducing the likelihood of data corruption on power-up. Figure 1. Two Uses of Multiple Voltage Monitoring 68 S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

82 V CC Supply Voltage

Notice: No external components required to monitor two voltages.

nal value of 1.7V or lesser. Note: This operation does not corrupt the memory array. changing the Block Lock and Watchdog Timer settings. and do not change when power is removed. written after the first byte is entered. not required to end this operation. Figure 4. Sample V

Figure 5. VTRIPX Set/Reset Sequence (X = 1, 2) the control register) or until the part powers up again. immediately after the stop condition.

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 7 of 24 March 28, 2005 BP: Block Protect Bit (Nonvolatile) The Block Protect Bit, BP, determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The bl ock protect bits will prevent write operations to half or none of the array. PUP1, PUP0: Power-up Bits (Nonvolatile) The Power-up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power-up times are shown in the following table. WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watch- dog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write a one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. To illustrate, a sequence of wr ites to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolat ile bits unchanged and the RWEL bit remains set. FAULT DETECTION REGISTER The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and three Low Voltage Fail bits are volatile. The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this fault detection register. BP Protected Addresses (Size) Array Lock

0 None None

1 100h – 1FFh (256 bytes) Upper Half of Memory Array PUP1 PUP0 Power-on Reset Delay (tPURST) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 65432 1 0 LV1F LV2F 0 WDF 0 0 0 0

Figure 9. Byte Write Sequence goes back to ‘0’ on the same page. and the last 6 bytes are written to locations 0 through 5. writes the previous data, one byte at a time. Figure 10. Page Write Operation Figure 11. Writing 12 bytes to a 16-byte page starting at location 10. edge, and data transfer sequence.

5 Bytes

7 Bytes

ceed with the read or write operation. See Figure 12. Reads, and Sequential Reads. acknowledge, and data transfer sequence. Figure 12. Acknowledge Polling Sequence clock cycle and then issue a stop condition. edge, and data transfer sequence.

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 14 of 24 March 28, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this spec ification) is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS *See Ordering Info Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Version Chip Supply Voltage Monitored* Voltages X40410/11 -A or -B 2.7V to 5.5V 2.6V to 5V X40410/11- C, X40414/15 2.7V to 5.5V 1V to 3.6V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions ICC1(1) Active Supply Current (VCC) Read 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz ICC2(1) Active Supply Current (VCC) Read 3.0 mA ISB1(1)(6) Standby Current (VCC) AC (WDT off) 6 10 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz ISB2(2)(6) Standby Current (VCC) DC (WDT on) 25 30 µA V SDA = VSCL = VCC Others = GND or VCC ILI Input Leakage Current (SCL) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2- FAIL, WDO, RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage (SDA, SCL) -0.5 VCC x 0.3 V VIH(3) Input HIGH Voltage (SDA, SCL) VCC x 0.7 VCC + 0.5 V VHYS(6) Schmitt Trigger Input Hysteresis

• Fixed input level
• VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RE- SET/RESET, V2FAIL, WDO) IOL = 1.8mA (2.7-3.6V) VOH Output (RESET) HIGH Voltage VCC - 0.8 VCC - 0.4 VI OH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.7-3.6V)

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 15 of 24 March 28, 2005 Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, exc ept those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, V CC = 5V. (5) See Ordering Information for standard programming le vels. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2) CAPACITANCE Note: (1) This parameter is not 100% tested. VCC Supply VTRIP1(5) VCC Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 V X40410/11-A 4.35 4.4 4.45 V X40410/11-B 2.85 2.9 2.95 V X40410/11-C, X40414/15-A&C 2.55 2.6 2.65 V X40414/15-B tRPD2(6) VTRIP2 to V2FAIL 5µ S Second Supply Monitor IV2 V2MON Current 15 µA VTRIP2 V2MON Trip Point Voltage Range 1.7 0.9 4.75 3.5 V V X40410/11 X40414/15 2.85 2.9 2.95 V X40410/11-A 2.55 2.6 2.65 V X40410/11-B 1.65 1.7 1.75 V X40410/11-C 1.25 1.3 1.35 V X40414/15-A&B 0.95 1.0 1.05 V X40414/15-C D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions –VREF tRPDX = 5µs worst case Output Pin VxMON R C V = 100mVV Vref Symbol Parameter Max. Unit Test Conditions COUT(1) Output Capacitance (SDA, RESET, RESET, V2FAIL, WDO) 8p F V OUT = 0V CIN(1) Input Capacitance (SCL) 6 pF V IN = 0V

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 16 of 24 March 28, 2005 EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS SYMBOL TABLE Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON 4.6k RESET 30pF 2.06k V2FAIL VOUT 4.6k 30pF WDO Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INP UTS OUTPUTS

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 17 of 24 March 28, 2005 A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter 400kHz UnitMin. Max. fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 18 of 24 March 28, 2005 Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Power Fail Timings Symbol Parameter Min. Typ. (1) Max. Unit tWC(1) Write Cycle Time 5 10 ms SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition V2MON V2FAIL or tR tF tRPDX VRVALIDV3FAIL LOWLINE or VCC or VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 19 of 24 March 28, 2005 RESET/RESET Timings LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Notes: (1) V CC = 5V at 25°C. (2) Values based on characterization data only. Symbol Parameters Min. Typ. (1) Max. Unit tRPD1(2) VTRIP1 to RESET/RESET (Power-down only) 5 µs tRPDX(2) VTRIP2 to V2FAIL 5µ s tPURST Power-on Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) PUP1=1, PUP0=0 PUP1=1, PUP0=1 200 (2) 400(2) 800(2) ms ms ms ms t F VCC, V2MON, Fall Time 20 mV µs tR VCC, V2MON, Rise Time 20 mV µs VRVALID Reset Valid VCC 1V tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1=1, WD0=1 (factory setting) 1.4 (2) 200(2) OFF s ms ms t RST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 20 of 24 March 28, 2005 Watchdog Time Out For 2-Wire Interface VTRIPX Set/Reset Conditions < tWDO tRST WDO SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1) SCL SDA VCC/V2MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 sets VTRIP1 sets VTRIP2 01h* 09h* 03h* 0Bh* resets VTRIP2 resets VTRIP1 Start * all others reserved 00h

FN8116 Rev 0.00 Page 21 of 24 March 28, 2005 X40410, X40411, X40414, X40415 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. VTRIP1, VTRIP2, Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range – X40410/11 1.7 4.75 V VTRAN2A VTRIP2 Set to Voltage Range – X40414/15 0.9 3.5 V Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 22 of 24 March 28, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic, SOIC, Package Code S8 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 23 of 24 March 28, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Code V8 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical

X40410, X40411, X40414, X40415 FN8116 Rev 0.00 Page 24 of 24 March 28, 2005

ORDERING INFORMATION

Range V TRIP1 Range V TRIP2 Range Package Operating Temperature Range Part Number with RESET Part Number with RESET 2.9-5.5 4.6V±50mV 2.9V±50mV 8L SOIC 0 oC - 70oC X40410S8-A X40411S8-A -40oC - 85oC X40410S8I-A X40411S8I-A 8L TSSOP 0 oC - 70oC X40410V8-A X40411V8-A -40oC - 85oC X40410V8I-A X40411V8I-A 2.6-5.5 4.4V±50mV 2.6V±50mV 8L SOIC 0 oC - 70oC X40410S8-B X40411S8-B -40oC - 85oC X40410S8I-B X40411S8I-B 8L TSSOP 0 oC - 70oC X40410V8-B X40411V8-B -40oC - 85oC X40410V8I-B X40411V8I-B 1.7-3.6 2.9V±50mV 1.7V±50mV 8L SOIC 0 oC - 70oC X40410S8-C X40411S8-C -40oC - 85oC X40410S8I-C X40411S8I-C 8L TSSOP 0 oC - 70oC X40410V8-C X40411V8-C -40oC - 85oC X40410V8I-C X40411V8I-C 1.3-3.6 2.9V±50mV 1.3V±50mV 8L SOIC 0 oC - 70oC X40414S8-A X40415S8-A -40oC - 85oC X40414S8I-A X40415S8I-A 8L TSSOP 0 oC - 70oC X40414V8-A X40415V8-A -40oC - 85oC X40414V8I-A X40415V8I-A 1.3-3.6 2.6V±50mV 1.3V±50mV 8L SOIC 0 oC - 70oC X40414S8-B X40415S8-B -40oC - 85oC X40414S8I-B X40415S8I-B 8L TSSOP 0 oC - 70oC X40414V8-B X40415V8-B -40oC - 85oC X40414V8I-B X40415V8I-B 1.0-3.6 2.9V±50mV 1.0V±50mV 8L SOIC 0 oC - 70oC X40414S8-C X40415S8-C -40oC - 85oC X40414S8I-C X40415S8I-C 8L TSSOP 0 oC - 70oC X40414V8-C X40415V8-C -40oC - 85oC X40414V8I-C X40415V8I-C 8-Lead Package X4041XX YYWWXX I – Industrial 0/1/4/5 Package - S/V Blank – Commercial WW – Workweek YY – Year A, B, or C