X40231 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Renesas
- PDF pages: 36
Technical content
FN8115 Rev 0.00 Page 1 of 36 April 11, 2005 FN8115 Rev 0.00 April 11, 2005 X40231, X40233, X40235, X40237, X40239 Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP DATASHEET
FEATURES
- Triple Voltage Monitors —User Programmable Threshold Voltage —Power-on Reset (POR) Circuitry —Software Selectable Reset timeout —Manual Reset Input
- 2-Wire industry standard Serial Interface
- 2 kbit EEPROM with Write Protect & Block Lock TM
- Digitally Controlled Potentiometers (DCP) —Total Resistance
256 Tap = 100k100 Tap or 64 Tap = 10k
—Nonvolatile wiper position —Write Protect Function
- Single Supply Operation —2.7V to 5.5V
- 16 Pin SOIC (300) package —SOIC
DESCRIPTION
The X4023x family of Integrated System Manage- ment ICs combine CPU Supervisor functions (V CC Power-onpower-on Reset (POR) circuitry, two addi- tional programmable voltage monitor inputs with soft- ware and hardware indicators), integrated EEPROM with Block Lock TM protection and one or two Intersil Digitally Controlled Potentiometers (XDCP). All func- tions of the X4023x are accessed by an industry standard 2-Wire serial interface.
APPLICATIONS
The DCP of the X4023x may be utilized to software control analog voltages for: – LCD contrast, LCD purity, or Backlight control. – Power Supply settings such as PWM frequency, Voltage Trimming or Margining (temperature offset control). – Reference voltage setting (e.g. DDR-SDRAM SSTL-2) The 2 kbit integrated EEPROM may be used to store ID, manufacturer data, maintenance data and module definition data. The programmable POR circuit insures V CC is stable before RESET is removed and protects against brown-outs and power failures. The programmable voltage monitors have on-chip independent reference alarm levels. With separate outputs, the voltage moni- tors can be used for power-on sequencing. BLOCK DIAGRAM X4023X Family Selector Guide X= 256 tap 100 tap 64 Tap 71 1 91 1 DATA REGISTER COMMAND DECODE & CONTROL LOGIC SDA SCL POWER-ON / LOW VOLTAGE CR REGISTER PROTECT LOGIC EEPROM THRESHOLD RESET LOGIC GENERATION RESET V2MON VCC VTRIP1 V3MON 2 kbit RESET Manual Reset (MR) RH RW V2FAIL WP V3FAIL ARRAY ©2000 Intersil Inc., Patents Pending (VTRIP1,2,3 are user programmable) WIPER REGISTER RH RWCOUNTER 8 - BIT NONVOLATILE MEMORY
256 Tap DCP
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 2 of 36 April 11, 2005 PIN CONFIGURATION V2MON V3MON NC VCC SDA RH0 RW0 VSS V3FAIL NC 1 WP 6 NC 2 MR 5 SCL RESET V2FAIL
16 Pin SOIC
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 3 of 36 April 11, 2005 X40231 PIN ASSIGNMENT SOIC Name Function 1N C No Connect 2N C No Connect 3V 3 M O N V3MON Voltage Monitor Input. V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V 3 F A I L V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground.
10 NC No Connect
H0 Connection to end of resistor array for (the 64 Tap) DCP . 12 RW0 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
13 V2MON
V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used.
14 V2FAIL
V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor.
15 RESET
VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 V CC Supply Voltage.
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 4 of 36 April 11, 2005 X40233 PIN ASSIGNMENT SOIC Name Function 1N C No Connect 2N C No Connect 3V 3 M O N V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V 3 F A I L V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground. 10 RW1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP . 11 RH1 Connection to end of resistor array for (the 100 Tap) DCP.
12 NC No Connect
V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor. VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 VCC Supply Voltage.
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 5 of 36 April 11, 2005 X40235 PIN ASSIGNMENT SOIC Name Function 1 RH2 Connection to end of resistor array for (the 256 Tap) DCP. 2 RW2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP . 3V 3 M O N V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V 3 F A I L V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground.
11 NC No Connect
V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-uppower-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor. VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 VCC Supply Voltage.
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 6 of 36 April 11, 2005 X40237 PIN ASSIGNMENT SOIC Name Function 1 RH2 Connection to end of resistor array for (the 256 Tap) DCP2. 2 RW2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2. 3V 3 M O N V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V 3 F A I L V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground. 11 RH0 Connection to end of resistor array for (the 64 Tap) DCP0. 12 RW0 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP0. V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-uppower-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor. VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 VCC Supply Voltage.
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 7 of 36 April 11, 2005 X40239 PIN ASSIGNMENT SOIC Name Function 1 RH2 Connection to end of resistor array for (the 256 Tap) DCP2. 2 RW2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2. 3V 3 M O N V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V 3 F A I L V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground. 10 R W1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP1. 11 RH1 Connection to end of resistor array for (the 100 Tap) DCP1. V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor. VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 VCC Supply Voltage.
ability, and reduces board space requirements. allows the user to externally activate the RESET output. advanced recovery algorithms to be implemented. eters, either at the time of manufacture, or in the field. cycles and a minimum data retention of 100 years. The device features a 2-Wire interface. X4023x, the SDA pin is in the input mode. Figure 1. Valid Data Changes on the SDA Bus
significant four bits of the Slave Address (SA7 - SA4). write cycle has been completed.
000 EEPROM Array
010 CR Register
111 DCP
1 READ
Figure 4. Slave Address Format
ered down and then powered back up. nonvolatile write operation. powered down then powered back up. If WT is “0” then a DCP Volatile Write is performed. Figure 7. DCP Power-up
0 Select a Volatile Write operation to be performed
1 Select a Nonvolatile Write operation to be per-
†This bit has no effect when a Read operation is being performed. Figure 8. Instruction Byte Format
three byte command sequence shown in Figure 9. been issued on SDA (See Figure 34). over to the lowest tap position. data for DCP1 (100 Tap), is shown in “APPENDIX 1” . Data Byte (binary) for DCP1, is given in “APPENDIX 2” . Figure 9. DCP Write Command Sequence
11 R e s e r v e d
ACKNOWLEDGE bit after the Address Byte. back to ‘0’ on the same page. the previous data, one byte at a time (See Figure 13). ACKNOWLEDGE, and data transfer sequence. and receiving the subsequent ACKNOWLEDGE signal. Figure 12. EEPROM Pag e Write Operation
various parameters of the X4023x (See Figure 17). tive of their value at power-down). powers down, and then up again. that powers up in the disabled, LOW (“0”) state. register has been completed (See Figure 18). —When the X4023x is powered down. Lock protection bits - (Nonvolatile)", below). aborted without changing any data in the array. Figure 17. CR Register Format NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
01 C0h - FFh (64 bytes) Upper 1/4
“wiper position” of the DCPs cannot be changed - i.e. period of time, tPURST (See Figure 30). atile, and therefore power-up to the last written state. The default for these bits are PUP1 = 0, PUP0 = 1. —The corresponding VxFAIL output becomes LOW. after the first byte is entered (Refer to Figure 18).
01 N O
10 N O
11 N O
Figure 18. CR Register Write Command Sequence
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 20 of 36 April 11, 2005 Prior to writing to the CR register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps —Write a 02H to the CR Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP). —Write a 06H to the CR Register to set the Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP). —Write a one byte value to the CR Register that has all the bits set to the desired state. The CR register can be rep- resented as qxyst01r in binary, where xy are the Voltage Monitor Output Status (V2FS and V3FS) bits, st are the Block Lock Protection (BL1 and BL0) bits, and qr are the Power-on Reset delay time (t PURST) control bits (PUP1 - PUP0). This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys t11r) then the RWEL bit is set, but the V2FS, V3FS, PUP1, PUP0, BL1 and BL0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and the X4023x does not return an ACKNOWLEDGE. For example, a sequence of writes to the device CR reg- ister consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the CR Register to “0”. It should be noted that a write to any nonvolatile bit of CR register will be ignored if the Write Protect pin of the X4023x is active (HIGH) (See "WP: Write Protection Pin"). CR (Control) Register Read Operation The contents of the CR Register can be read at any time by performing a random read (See Figure 18). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each register read operation. The X4023x resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol. After setting the WEL and / or the RWEL bit(s) to a “1”, a CR register read operation may o CCur, without interrupt- ing a proceeding CR register write operation. DATA PROTECTION There are a number of levels of data protection features designed into the X4023x. Any write to the device first requires setting of the WEL bit in the CR register. A write to the CR register itself, further requires the setting of the RWEL bit. Block Lock protection of the device enables the user to inhibit writes to certain regions of the EEPROM memory, as well as to all the DCPs. One fur- ther level of data protection in the X4023x, is incorpo- rated in the form of the Write Protection pin. WP: Write Protection Pin When the Write Protection (WP) pin is active (HIGH), it disables nonvolatile write operations to the X4023x. The table below (X4023x Write Permission Status) sum- marizes the effect of the WP pin (and Block Lock), on the write permission status of the device. Additional Data Protection Features In addition to the preceding features, the X4023x also incorporates the following data protection functionality: —The proper clock count and data bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle. VOLTAGE MONITORING FUNCTIONS VCC Monitoring The X4023x monitors the supply voltage and drives the RESET output HIGH (using an external “pull up” resistor) if VCC is lower than VTRIP1 threshold. The RESET output will remain HIGH until VCC exceeds VTRIP1 for a minimum time of tPURST. After this time, the RESET pin is driven to a LOW state. See Figure 30. For the Power-on / Low Voltage Reset function of the X4023x, the RESET output may be driven HIGH down to a VCC of 1V (VRVALID). See Figure 30. Another feature of the X4023x, is that the value of t PURST may be selected in software via the CR register (See “PUP1, PUP0: Power-on Reset bits – (Nonvolatile)” on page 19.). It is recommended to stop communication to the device while RESET is HIGH. Also , setting the Manual Reset (MR) pin HIGH overrides the Power-on / Low Voltage circuitry and forces the RESET output pin HIGH (See "MR: Manual Reset").
0 Volts
Figure 19. Manual Reset Response Figure 20. CR R egister Read Command Sequence
after system initialization). after system initialization). TRIPx voltage before setting the new value. Figure 21. Voltage Monitor Response Figure 22. Setting V TRIPx to a higher level (x = 1,2,3).
increase the accuracy of the threshold voltage. value of the calculated error. TRIPx Voltage (x = 1,2,3)"). Figure 24. V TRIPx Setting / Reset Sequence (x = 1,2,3)
Figure 30. Power-Up and Power-Down Timing Figure 31. Manual Reset Timing Diagram Figure 32. V2MON, V3MON Timing Diagram
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 29 of 36 April 11, 2005 D.C. OPERATING CHARACTERISTICS Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Sel ect Bits in the Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation. Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte. Notes: 3. Current through external pull up resistor not included. Notes: 4. V IN = Voltage applied to input pin. Notes: 5. V OUT = Voltage applied to output pin. Notes: 6. See “ORDERING INFORMATION” on page 36. Notes: 7. V IL Min. and VIH Max. are for reference only and are not tested Notes: 8. Equivalent input circuit for V XMON Symbol Parameter Min Typ Max Unit Test Conditions / Notes VCC 2.7 5.5 V Requires VCC > VTRIP1 or chip will not operate. ICC1(1) Current into VCC Pin (X4023x: Active) Read memory array (3) Write nonvolatile memory VCC = 3.5V 0.4 1.5 mA fSCL = 400KHz ICC2(2) Current into VCC Pin (X4023x:Standby) With 2-Wire bus activity (3) No 2-Wire bus activity V CC = 3.5V 50.0 50.0 VSDA = VCC MR = VSS WP = VSS or Open/Floating VSCL= VCC (when no bus activity else fSCL = 400kHz) ILI Input Leakage Current (SCL, SDA, MR) 0.1 10 AV IN(4) = GND to VCC. Input Leakage Current (WP) 10 A ILO Output Leakage Current (SDA, RESET, V2FAIL, V3FAIL) 0.1 10 A VOUT(5) = GND to VCC. X4023x is in Standby(2) VTRIP1PR VTRIP1 Programming Range 2.75 4.70 V VTRIPxPR VTRIPx Programming Range (x = 2,3) 1.75 3.50 V VTRIP1(6) Pre - programmed VTRIP1 threshold 2.8 4.3 2.95 4.45 3.00
4.50 V Factory shipped default option A
Factory shipped default option B VTRIP2(6) Pre - programmed VTRIP2 threshold 2.05 2.8 2.20 2.95 2.25
3.00 V Factory shipped default option A
Factory shipped default option B VTRIP3(6) Pre - programmed VTRIP3 threshold 1.60 1.60 1.75 1.75 1.80
1.80 V Factory shipped default option A
Factory shipped default option B tRPDx VCC, V2MON, V3MON to RESET, V2FAIL, V3FAIL propagation delay (respectively) 20 s See (8) IVx V2MON Input leakage current V3MON Input leakage current 1 A VSDA = VSCL = VCC Others = GND or VCC VIL(7) Input LOW Voltage (SCL, SDA, WP, MR) -0.5 0.8 V VIH(7) Input HIGH Voltage (SCL,SDA, WP, MR) 2.0 VCC +0.5 V VOLx RESET, V2FAIL, V3FAIL, SDA Output Low Voltage 0.4 V I SINK = 2.0mA VXMON VREF
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 30 of 36 April 11, 2005 A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29) A.C. TEST CONDITIONS NONVOLATILE WRITE CYCLE TIMING CAPACITANCE (TA = 25°C, F = 1.0 MHZ, VCC = 5V) Notes: 1. Typical values are for T A = 25°C and VCC = 5.0V Notes: 2. Cb = total capacitance of one bus line in pF. Notes: 3. Over recommended operating conditions, unless otherwise specified Notes: 4. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Notes: 5. This parameter is not 100% tested. Symbol Parameter 400kHz Min Max Units fSCL SCL Clock Frequency 0 400 kHz tIN(5) Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 s tBUF Time the bus free before start of new transmission 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR(5) SDA and SCL Rise Time 20 +.1Cb(2) 300 ns tF(5) SDA and SCL Fall Time 20 +.1Cb(2) 300 ns tSU:WP WP Setup Time 0.6 s tHD:WP WP Hold Time 0 s Cb Capacitive load for each bus line 400 pF Input Pulse Levels 0.1V CC to 0.9VCC Input Rise and Fall Times 10ns Input and Output Timing Levels 0.5V CC Output Load See Figure 25 Symbol Parameter Min. Typ. (1) Max. Units tWC(4) Nonvolatile Write Cycle Time 5 10 ms Symbol Parameter Max Units Test Conditions COUT(5) Output Capacitance (SDA, RESET, V2FAIL, V3FAIL)8 p F VOUT = 0V CIN(5) Input Capacitance (SCL, WP, MR) 6 pF VIN = 0V
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 31 of 36 April 11, 2005 POTENTIOMETER CHARACTERISTICS Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX VSS - for ANY tap position n, (x = 0,1,2). Notes: 2. Absolute Linearity is ut ilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = ±1 Ml Maximum (x = 0,1,2). Notes: 3. Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = ±0.2 Ml (x = 0,1,2) Notes: 4. 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1). Notes: 5. Typical values are for T A = 25°C and nominal supply voltage. Notes: 6. This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Test Conditions/NotesMin. Typ. Max. Units RTOL End to End Resistance Tolerance -20 +20 % In a ratiometric circuit, RTOTAL divides out of the equation and accuracy is determined by XDCP resolution. V RHx RH Terminal Voltage (x = 0,1,2) VSS VCC V VRLx RL Terminal Voltage (x = 0,1,2) VSS VSS V R L Terminal internally tied to gnd. PR Power Rating(1) 10 mW R TOTAL = 10kDCP0, DCP1) 5m W R TOTAL = 100kDCP2) RW DCP Wiper Resistance 200 400 VCC = 5 V, VRHx = VCC, VRLx = VSS (x = 0,1,2), IW = 50 uA /500 uA (100/10k. 400 1200 VCC = 2.7 V, VRHx = VCC, VRLx = VSS (x = 0,1,2), IW = 27 uA /270 uA (100/10 k. IW Wiper Current 4.4 mA Noise mV (Hz) RTOTAL = 10kDCP0, DCP1) mV (Hz) RTOTAL = 100kDCP2) Absolute Linearity(2) -1 +1 MI(4) Rw(n)(actual) - Rw(n)(expected) Relative Linearity(3) -1 +1 MI(4) Rw(n+1) - [Rw(n) + MI] RTOTAL Temperature Coefficient ±300 ppm/°C R TOTAL = 10kDCP0, DCP1) ±300 ppm/°C R TOTAL = 100kDCP2) Ratiometric Temperature Coefficient ±30 ppm/°C (Voltage divider configuration) CH/CL/ CW Potentiometer Capacitances 10/10/25 pF See Figure 26. twr Wiper Response time 200 s See Figure 34.
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 32 of 36 April 11, 2005 VTRIPX (X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 33) Notes: 100% tested. RESET, V2FAIL, V3FAIL OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32) Notes: 1. See Figure 31 for timing diagram. Notes: 2. See Figure 25 for equivalent load. Notes: 3. This parameter describes the lowest possible V CC level for which the outputs RESET, V2FAIL, and V3FAIL will be correct with respect to their inputs (VCC, V2MON, V3MON). Notes: 4. From MR rising edge crossing VIH, to RESET rising edge crossing VOH. Notes: 5. Equivalent input circuit for V XMON Parameter Description Min Typ Max Units tVPS VTRIPx Program Enable Voltage Setup time 10 s tVPH VTRIPx Program Enable Voltage Hold time 10 s tTSU VTRIPx Setup time 10 s tTHD VTRIPx Hold (stable) time 10 s tVPO VTRIPx Program Enable Voltage Off time (Between successive adjustments) 1m s tWC VTRIPx Write Cycle time 5 10 ms VP Programming Voltage 10 15 V Vta VTRIPx Program Voltage accuracy Programmed at 25°C.) -100 +100 mV Vtv VTRIP Program variation after programming (-40 - 85°C). (Programmed at 25°C.) -25 +10 +25 mV Symbol Description Condition Min. Typ. Max. Units tPURST Power-on Reset delay time PUP1 = 0, PUP0 = 0 25 50 75 ms PUP1 = 0, PUP0 = 1 50 100 150 ms PUP1 = 1, PUP0 = 0 100 200 300 ms PUP1 = 1, PUP0 = 1 150 300 450 ms t MRD(31)(2) MR to RESET propagation delay See (1)(2)(4) 5 s tMRDPW MR pulse width 500 ns tRPDx VCC, V2MON, V3MON to RESET, V2FAIL, V3FAIL propagation delay (respectively) See (5) 20 s tFx VCC, V2MON, V3MON Fall Time 20 mV/ s tRx VCC, V2MON, V3MON Rise Time 20 mV/ s VRVALID VCC for RESET, V2FAIL, V3FAIL Valid(3). 1V tRPDX = 20µs worst case VXMON VREF OUTPUT
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 33 of 36 April 11, 2005 APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Tap Position Data Byte Decimal Binary 0 0 0000 0000 1 1 0000 0001 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 98 97 0110 0001 99 96 0110 0000
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 34 of 36 April 11, 2005 APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. unsigned DCP1_TAP_Position(int tap_pos) int block; int i; int offset; int wcr_val; offset = 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned) wcr_val); case (2): wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned) wcr_val); case (3): wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned) wcr_val); return((unsigned)01100000);
X40231, X40233, X40235, X40237, X40239 FN8115 Rev 0.00 Page 35 of 36 April 11, 2005 16-Lead Plastic, SOIC (300-mil body), Package Code S16 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.403 (10.2 ) 0.413 ( 10.5) (4X) 7° 0.420" 0.050" Typical 0.030" Typical
16 PlacesFOOTPRINT
0.010 (0.25) 0.020 (0.50) 0.0075 (0.19) 0.010 (0.25) 0 - 8 X 45 0.050" Typical 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) 0.015 (0.40) 0.050 (1.27)
FN8115 Rev 0.00 Page 36 of 36 April 11, 2005 X40231, X40233, X40235, X40237, X40239 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Device Preset (Factory Shipped) VTRIPx Threshold Levels (x = 1,2,3) A = Optimized for 3.3 V system monitoring B = Optimized for 5 V system monitoring † Temperature Range I = Industrial -40C to +85C Package S16 = 16-Lead Widebody SOIC (300 mil) X4023x PT - y † For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"