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Technical content

Features

  • Selectable watchdog timer - Select 200ms, 600ms, 1.4s, off
  • L o w VCC detection and reset assertion - Five standard reset threshold voltages nominal 4.62V, -A d j u s t l o w VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V
  • Low power CMOS - 12µA typical standby current, watchdog on - 800nA typical standby current watchdog off - 3mA active current
  • 400kHz I 2C interface
  • 1.8V to 5.5V power supply operation
  • Available packages - 8 Ld SOIC - 8 Ld MSOP
  • Pb-free available (RoHS compliant) Pinout X4003, X4005 (8 LD SOIC, MSOP) TOP VIEW Block Diagram NC VSS VCC SDA SCL3 8NC WP RESET/RESET* *RESET APPLIES TO X4003 RESET APPLIES TO X4005 DATA REGISTER COMMAND DECODE AND CONTROL LOGIC SDA SCL VCC RESET AND WATCHDOG TIMEBASE POWER-ON AND GENERATION RESET (X4003) RESET LOW VOLTAGE CONTROL REGISTER WATCHDOG TRANSITION DETECTOR WP VCC THRESHOLD RESET LOGIC RESET (X4005) VTRIP WATCHDOG TIMER RESET NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X4003, X4005 FN8113 Rev 2.00 Page 2 of 16 June 30, 2008

Ordering Information

(ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP. RANGE (°C) PACKAGE PKG. DWG. # (3.0mm) M8.118 X4003M8Z-4.5A (Note) DAH X4005M8Z-4.5A (Note) DAP 0 to +70 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8-4.5A X4003 AL X4005S8-4.5A X4005 AL 0 to +70 8 Ld SOIC (150 mil) MDP0027 X4003S8Z-4.5A (Note) X4003 ZAL X4005S8Z-4.5A (Note) X4005 ZAL 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8I-4.5A ACI X4005M8I-4.5A ACR -40 to +85 8 Ld MSOP (3.0mm) M8.118 X4003M8IZ-4.5A (Note) DAD X4005M8IZ-4.5A (Note) DAM -40 to +85 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8I-4.5A X4003 AM X4005S8I-4.5A X4005 AM -40 to +85 8 Ld SOIC (150 mil) MDP0027 X4003S8IZ-4.5A (Note) X4003 ZAM X4005S8IZ-4.5A (Note) X4005 ZAM -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8 ACJ X4005M8 ACS 4.25 to 4.5 0 to +70 8 Ld MSOP (3.0mm) M8.118 X4003M8Z (Note) DAE X4005M8Z (Note) DER 0 to +70 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8 X4003 X4005S8 X4005 0 to +70 8 Ld SOIC (150 mil) MDP0027 X4003S8Z (Note) X4003 Z X4005S8Z (Note) X4005 Z 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8I ACK X4005M8I ACT -40 to +85 8 Ld MSOP (3.0mm) M8.118 X4003M8IZ (Note) DAA X4005M8IZ (Note) DAJ -40 to +85 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8I X4003 I X4005S8I X4005 I -40 to +85 8 Ld SOIC (150 mil) MDP0027 X4003S8IZ (Note) X4003 ZI X4005S8IZ (Note) X4005 ZI -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 (3.0mm) M8.118 X4003M8Z-2.7A (Note) DAG X4005M8Z-2.7A (Note) DAO 0 to +70 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8-2.7A X4003 AN X4005S8-2.7A X4005 AN 0 to +70 8 Ld SOIC (150 mil) MDP0027 X4003S8Z-2.7A (Note) X4003 ZAN X4005S8Z-2.7A (Note) X4005 ZAN 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8-2.7 ACN X4005M8-2.7 ACW 2.55 to 2.7 0 to +70 8 Ld MSOP (3.0mm) M8.118 X4003M8Z-2.7 (Note) DAF X4005M8Z-2.7 (Note) DAN 0 to +70 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8-2.7 X4003 F X4005S8-2.7 X4005 F 0 to +70 8 Ld SOIC (150 mil) MDP0027 X4003S8Z-2.7 (Note) X4003 ZF X4005S8Z-2.7 (Note) X4005 ZF 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027

X4003, X4005 FN8113 Rev 2.00 Page 3 of 16 June 30, 2008 (150 mil) MDP0027 X4003S8IZ-2.7A (Note) X4003 ZAP X4005S8IZ-2.7A (Note) X4005 ZAP -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8I-2.7A ACM X4005M8I-2.7A ACV -40 to +85 8 Ld MSOP (3.0mm) M8.118 X4003M8IZ-2.7A (Note) DAC X4005M8IZ-2.7A (Note) DAL -40 to +85 8 Ld MSOP (3.0mm) (Pb-free) M8.118 X4003S8I-2.7 X4003 G X4005S8I-2.7 X4005 G 2.55 to 2.7 -40 to +85 8 Ld SOIC (150 mil) MDP0027 X4003S8IZ-2.7 (Note) X4003 ZG X4005S8IZ-2.7 (Note) X4005 ZG -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X4003M8I-2.7 ACO X4005M8I-2.7 ACX -40 to +85 8 Ld MSOP (3.0mm) M8.118 X4003M8IZ-2.7 (Note) DAB X4005M8IZ-2.7 (Note) DAK -40 to +85 8 Ld MSOP (3.0mm) (Pb-free) M8.118 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP. RANGE (°C) PACKAGE PKG. DWG. # Pin Descriptions PIN NUMBER (MSOP) NAME FUNCTION

1 NC No internal connections

2 NC No internal connections

3 RESET /RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a stop condition resets the watchdog timer. RESET/RESET goes active on power-up and remains active for 250ms after the power supply stabilizes. 4V SS Ground 5S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop condition resets the watchdog timer. The absence of this procedure within the watchdog time-out period results in RESET /RESET going active. 6S C L Serial Clock. The serial clock controls the serial bus timing for data input and output. 7W P Write Protect. WP HIGH prevents changes to the watchdog timer setting. 8V CC Supply voltage

are nonvolatile and do not chan ge when power is removed. steps. See "Writing to the Control Register" on page 7. written after the first byte is entered. not required to end this operation. FIGURE 5. VTRIP PROGRAMMING SEQUENCE

WEL bit and zeroes to the other bits of the control register.

  • Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop.)
  • Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop.)
  • Write a value to the control register that has all the control bits set to the desired state. This can be represented as 0xy0 0010 in binary, where xy are the WD bits. (Operation preceeded by a start and ended with a stop.) Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then the RWEL bit is set, but the WD1 and WD0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.
  • A read operation occurring between any of the previous operations will not interrupt the register write operation.
  • The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Serial Interface Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6. WD1 WD0 WATCHDOG TIME-OUT PERIOD 0 0 1.4s 0 1 600ms 1 0 200ms 1 1 Disabled (factory setting) SCL DATA STABLE DATA CHANGE DATA STABLE SDA

FIGURE 6. VALID DATA CHANGES ON THE SDA BUS

  • After loading the entire slave address byte from the SDA bus, the device compares the input slave byte data to the proper slave byte. Upon a correct compare, the device outputs an acknowledge on the SDA line. Write Control Register To write to the control register, the device requires the slave address byte and a byte address. This gives the master access to register. After receipt of the address byte, the device responds with an acknowledge, and awaits the data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. If WP is HIGH, the control register cannot be changed. A write to the control register will suppress the acknowledge bit and no data in the control register will change. With WP low, a second byte written to the control register terminates the operation and no write occurs. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. Serial Read Operations The read operation allows the master to access the control register. To conform to the I2C standard, prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the byte address. After acknowledging receipt of the byte address, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit control register. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 10 for the address, acknowledge, and data transfer sequences. Operational Notes The device powers-up in the following state:
  • The device is in the low power standby state.
  • The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
  • SDA pin is the input mode. RESET /RESET signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes:
  • The WEL bit must be set to allow a write operation.
  • The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle.
  • A three step sequence is required before writing into the control register to change watchdog timer or block lock settings.
  • The WP pin, when held HIGH, prevents all writes to the control register.
  • Communication to the device is inhibited below the VTRIP voltage.
  • Command to change the control register are terminated if in- progress when RESET/RESET go active. Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance SLAVE ADDRESS BYTE ADDRESS A C K A C K S T A R T S T O P SLAVE ADDRESS DATA A C K S T A R T SDA BUS SIGNALS FROM THE SLAVE SIGNALS FROM THE MASTER 010011011 11111111 1001101

FIGURE 10. CONTROL REGISTER READ SEQUENCE

X4003, X4005 FN8113 Rev 2.00 Page 10 of 16 June 30, 2008 Absolute Maximum Ratings Thermal Information Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp DC Operating Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS VCC = 1.8 TO 3.6V V CC = 2.7 TO 5.5V UNITMIN MAX MIN MAX ICC (Note 1) Active Supply Current Read Control Register fSCL = 400kHz nonvolatile, SDA = Open 0.5 1.0 mA ICC2 (Note 1) Active Supply Current Write Control Register fSCL = 400kHz nonvolatile, SDA = Open 1.5 3.0 mA ICC3 (Note 2) Operating Current AC (WDT Off) f SCL = 400kHz nonvolatile, SDA = Open 11 µ A ICC4 (Note 2) Operating Current DC (WDT Off) V SDA = VSCL = VCC Others = GND or VSB 11 µ A ICC5 (Note 2) Operating Current DC (WDT On) V SDA = VSCL = VCC Others = GND or VSB 10 20 µA ILI Input Leakage Current V IN = GND to VCC 10 10 µA ILO Output Leakage Current V SDA = GND to VCC Device is in Standby (Note 2) 10 10 µA VIL (Note 3) Input LOW Voltage -0.5 V CC x 0.3 -0.5 V CC x 0.3 V VIH (Note 3) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V CC x 0.7 V CC + 0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed Input Level 0.2 0.2 V VCC Related Level 0.05 x V CC 0.05 x VCC V VOL Output LOW Voltage I OL = 3.0mA (2.7V to 5.5V) IOL = 1.8mA (1.8V to 3.6V) 0.4 0.4 V NOTES: 1. The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. 2. The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. 3. VIL min. and VIH max. are for reference only and are not tested. Capacitance (TA = +25°C, f = 1.0 MHz, VCC = 5V) SYMBOL PARAMETER TYP UNIT TEST CONDITIONS COUT Output Capacitance (SDA, RESET/RESET) 8 pF V OUT = 0V CIN Input Capacitance (SCL, WP) 6 pF V IN = 0V

X4003, X4005 FN8113 Rev 2.00 Page 11 of 16 June 30, 2008 Equivalent AC Load Circuit AC Test Conditions 4.6k RESET 100pF SDA 1533 100pF For VOL = 0.4V and IOL = 3mA RESET Input pulse levels 0.1V CC to 0.9VCC Input rise and fall times 10ns Input and output timing levels 0.5V CC Output load Standard output load SYMBOL PARAMETER 100kHz 400kHz UNITMIN MAX MIN MAX fSCL SCL Clock Frequency 0 100 0 400 kHz tIN Pulse Width Suppression Time at Inputs n/a n/a 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 0.1 0.9 µs tBUF Time the Bus Free Before Start of New Transmission 4.7 1.3 µs tLOW Clock LOW Time 4.7 1.3 µs tHIGH Clock HIGH Time 4.0 0.6 µs tSU:STA Start Condition Set-up Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:DAT Data in Setup Time 250 100 ns tHD:DAT Data in Hold Time 5.0 0 µs tSU:STO Stop Condition Set-up Time 0.6 0.6 µs tDH Data Output Hold Time 50 50 ns tR SDA and SCL Rise Time 1000 20 + 0.1Cb (Note 5) 300 ns tF SDA and SCL Fall Time 300 20 + 0.1Cb (Note 5) 300 ns tSU:WP WP Set-up Time 0.4 0.6 µs tHD:WP WP Hold Time 0 0 µs Cb Capacitive Load for Each Bus Line 400 400 pF NOTES: 4. Typical values are for TA = +25°C and VCC = 5.0V 5. Cb = total capacitance of one bus line in pF

X4003, X4005 FN8113 Rev 2.00 Page 12 of 16 June 30, 2008 Timing Diagrams Bus Timing WP Pin Timing Write Cycle Timing tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtA tR tHD:WP SCL SDA IN WP tSU:WP CLK 1 CLK 9 SLAVE ADDRESS BYTE START SCL SDA tWC 8TH BIT OF LAST BYTE ACK STOP CONDITION START CONDITION Nonvolatile Write Cycle Timing SYMBOL PARAMETER MIN TYP (Note 1) MAX UNIT tWC (Note 6) Write Cycle Time 5 10 ms NOTE: 6. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

X4003, X4005 FN8113 Rev 2.00 Page 13 of 16 June 30, 2008 Power-Up and Power-Down Timing SDA vs RESET/RESET Timing VCC tPURST tPURST tR tF tRPD RESET VTRIP VRVALID VRVALIDRESET RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT Reset Trip Point Voltage, X4003, X4005 4.25 4.38 4.5 V t PURST Power-up Reset Time-out 100 200 400 ms tRPD VCC Detect to Reset Output 500 ns tF VCC Fall Time 10 ms tR VCC Rise Time 0.1 ns VRVALID Reset Valid VCC 1V SDA tCST RESET tWDO tRST tWDO tRST SCL RESET RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT tWDO Watchdog Time-out Period WD1 = 1, WD0 = 1 (factory setting) OFF WD1 = 1, WD0 = 0 100 200 300 ms WD1 = 0, WD0 = 1 450 600 800 ms WD1 = 0, WD0 = 0 1 1.4 2 sec t CST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Time-out 100 200 400 ms

FN8113 Rev 2.00 Page 14 of 16 June 30, 2008 X4003, X4005 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2008. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. VTRIP Programming Timing Diagram VCC (VTRIP) WP tTSUtTHD tVPH tVPS VP VTRIP tVPO SCL SDA A0h01h OR 03h00h tRP VTRIP Programming Parameters PARAMETER DESCRIPTION MIN MAX UNIT tVPS VTRIP Program Enable Voltage Set-up Time 1 µs tVPH VTRIP Program Enable Voltage Hold Time 1 µs tTSU VTRIP Set-up Time 1µ s tTHD VTRIP Hold (Stable) Time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off Time (Between Successive Adjustments) 0 µs tRP VTRIP Program Recovery Period (Between Successive Adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage Accuracy (VCC Applied - VTRIP) (Programmed At +25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage Accuracy [(VCC Applied - Vta1) - VTRIP. programmed at +25°C.) -25 +25 mV Vtr VTRIP Program Voltage Repeatability (S uccessive Program Operations. Programmed at +25°C.) -25 +25 mV Vtv VTRIP Program Variation After Programming (0°C to +75°C). (Programmed at +25°C) -25 +25 mV

X4003, X4005 FN8113 Rev 2.00 Page 15 of 16 June 30, 2008 Mini Small Outline Plastic Packages (MSOP) NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M -1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums and to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimen- sions are for reference only. L 0.25 (0.010) R 4X  4X  GAUGE PLANE SEATING PLANE EE1 N TOP VIEW INDEX AREA -C- -B- 0.20 (0.008) A B C SEATING PLANE 0.20 (0.008) C 0.10 (0.004) C -A--H- SIDE VIEW b e D A -B- END VIEW0.20 (0.008) C D CL C a - H - -A - - B - - H - M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e 0.026 BSC 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N8 8 7 R 0.003 - 0.07 - - o 15o 5o 15o -  0o 6o 0o 6o - Rev. 2 01/03

X4003, X4005 FN8113 Rev 2.00 Page 16 of 16 June 30, 2008 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994