X40030 INTERSIL | Alldatasheet
Document overview
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Technical content
FN8114.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PRELIMINARY X40030, X40031, X40034, X40035 Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
- Triple voltage detection and reset assertion —Standard reset threshold settings See selection table on page 2. —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to V CC = 1V —Monitor three seperate voltages
- Fault detection register
- Selectable power on reset timeout
- Selectable watchdog timer interval (25ms, 200ms, 1.4s or off)
- Debounced manual reset input
- Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off
- 400kHz 2-wire interface
- 2.7V to 5.5V power supply operation
- Available packages —14-lead SOIC, TSSOP
- Monitor Voltages: 5V to 0.9V
- Independent Core Voltage Monitor
APPLICATIONS
- Communication Equipment —Routers, Hubs, Switches —Disk arrays, Network Storage
- Industrial Systems —Process Control —Intelligent Instrumentation
- Computer Systems —Computers —Network Servers
DESCRIPTION
The X40030, X40031, X40034, X40035 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, and manual reset, in one package. This combination lowers system cost, reduces boar d space requirements, and increases reliability. Applying voltage to V CC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscilla- tor to stabilize before the processor can execute code. Low V CC detection circuitry protects the user’s system from low voltage condit ions, resetting the system when V CC falls below the minimum V TRIP1 point. RESET/RESET is active until V CC returns to proper operating level and stabilizes. A second and third volt- age monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet specific system level requirements or to fine-tune the threshold for applica- BLOCK DIAGRAM V3FAIL V2FAIL WDO MR LOWLINE RESET RESET X40030/34 X40031/35 V3 MonitorLogic V2 MonitorLogic Fault Detection Register Status Register Data Register Command Decode Test & Control Logic Power on, Manual Reset Low Voltage Reset GenerationVCC Monitor Logic V3MON V2MON SDA WP SCL VCC (V1MON) Watchdog and Reset Logic VTRIP3 VTRIP2 VTRIP1 VCC or V2MON* Data Sheet April 28, 2005
2 FN8114.0 April 28, 2005 A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. *Voltage monitor requires VCC to operate. Others are independent of VCC PIN CONFIGURATION Device Expected System Voltages Vtrip1 (V) Vtrip2 (V) Vtrip3 (V) POR (system) X40030, X40031 5V; 3V or3.3V; 1.8V 5V; 3V; 1.8V 3.3V; 2.5V; 1.8V 2.0-4.75* 4.55-4.65* 4.35-4.45* 2.95-3.05* 1.70-4.75 2.85-2.95 2.55-2.65 2.15-2.25 1.70-4.75 1.65-1.75 1.65-1.75 1.65-1.75 RESET = X40030 RESET = X40031 X40034, X40035 5V; 3.3V; 1.5V 5V; 3V or 3.3V; 1.5V 5V; 3V or 3.3V; 1.2V 2.0-4.75* 4.55-4.65* 4.55-4.65* 4.55-4.65* 0.90-3.50 1.25-1.35 1.25-1.35 0.95-1.05 1.70-4.75 3.05-3.15 2.85-2.95 2.85-2.95 RESET = X40030 RESET = X40031 V3MON VSS VCC SDA SCL LOWLINE NC RESET V2MON MR WP V3FAIL WDO V2FAIL V3MON VCC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL X40030, X40034 X40031, X40035 14-Pin SOIC, TSSOP 14-Pin SOIC, TSSOP PIN DESCRIPTION Pin Name Function 1V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. 2V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input (X40034, X40035). 3L O W L I N E Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4 NC No connect. 5M R Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET /
RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. X40030, X40031, X40034, X40035
to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power up. allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button requires a pull up resistor and the input buffer is always active (not gated). 9S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers). not used. The V3MON comparator is supplied by the V3MON input. goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin.
X40035 control register (also refer to page 21). Figure 4. Watchdog Restart X40031, X40034, X40035 trip points may be adjusted. cation of a high voltage control signal. TRIPx voltage before setting the new value. sponding input pin (Vcc(V1MON), V2MON or V3MON). repeated again (see Figure 5). (actual) – VTRIPX (desired)). Note: This operation does not corrupt the memory array. brought LOW to complete the operation. nal value of 1.7V or lesser.
- Set VCC ≅ 1.5(V2MON or V3MON), when
to the Control Registers" on page 7. data bytes written after the first byte is entered. Figure 5. Sample V
Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3) tile latch that powers up in the LOW (disabled) state. zeroes to the other bits of the control register. operation immediately after the stop condition. shown in the following table.
8 FN8114.0 April 28, 2005 WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation pre- ceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write one byte value to the Control Register that has all the control bits set to the desired state. The Con- trol register can be represented as qxys 001r in binary, where xy are the WD bits, s is the BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, or power cycling the device or attempting a write to a write protected block. To illustrate, a sequ ence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Notes: 1. t PURST is set to 200ms as factory default. 2. Watch Dog Timer bits are shipped disabled. FAULT DETECTION REGISTER (FDR) The Fault Detection Register provides the user the status of what causes th e system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR. WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 65432 1 0 LV1F LV2F LV3F WDF MRF 0 0 0 X40030, X40031, X40034, X40035
– a device type identifier that is always ‘1011’. bit is set-to “0” as factory default. Figure 12. X40030, X40031, X40034, X40035 is undefined on a power up condition. – The device is in the low power standby state. – SDA pin is the input mode. Signal is active for tPURST. – The WEL bit must be set to allow write operations. the array and all the Register.
13 FN8114.0 April 28, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS *See Ordering Info Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Version Chip Supply Voltage Moitored* Voltages X40030, X40031 2.7V to 5.5V 1.7V to 5.5V X40034, X40035 2.7V to 5.5V 1.0V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions ICC1(1) Active Supply Current (VCC) Read 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHzICC2(1) Active Supply Current (VCC) Write 3.0 mA ISB1(1) Standby Current (VCC) AC (WDT off) 6 10 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz ISB2(2) Standby Current (VCC) DC (WDT on) 25 30 µA V SDA = VSCL = VCC Others = GND or VCC ILI Input Leakage Current (SCL, MR, WP) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 VCC x 0.3 V VIH(3) Input HIGH Voltage (SDA, SCL, MR, WP) VCC x 0.7 VCC + 0.5 V VHYS(6) Schmitt Trigger Input Hysteresis
- Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RESET/RE- SET, LOWLINE, V2FAIL, V3FAIL, WDO) IOL = 1.8mA (2.7-3.6V) VOH Output (RESET, LOWLINE) HIGH Volt- age VCC – 0.8 VCC – 0.4 VI OH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.7-3.6V) VCC Supply VTRIP1(5) VCC Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 V X40030, X40031-A, X40034, X40035 4.35 4.4 4.45 V X40030, X40031-B 2.85 2.9 2.95 V X40030, X40031-C Second Supply Monitor I V2 V2MON Current 15 µA X40030, X40031, X40034, X40035
14 FN8114.0 April 28, 2005 Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, V CC = 3V (5) See ordering information for standard programming leve ls. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3) CAPACITANCE Note: (1) This parameter is not 100% tested. VTRIP2(5) V2MON Trip Point Voltage Range 1.7 0.9 4.75 3.5 V V X40030, X40031 X40034, X40035 2.85 2.9 2.95 V X40030, X40031-A 2.55 2.6 2.65 V X40030, X40031-B 2.15 2.2 2.25 V X40030, X40031-C 1.25 1.3 1.35 V X40034, X40035-A&B 0.95 1.0 1.05 V X40034, X40035-C t RPD2(6) VTRIP2 to V2FAIL 5µ s Third Supply Monitor IV3 V3MON Current 15 µA VTRIP3(5) V3MON Trip Point Voltage Range 1.7 4.75 V 1.65 1.7 1.75 V X40030, X40031 3.05 3.1 3.15 V X40034, X40035-A 2.85 2.9 2.95 V X40034, X40035-B&C t RPD3(6) VTRIP3 to V3FAIL 5µ s Symbol Parameter Max. Unit Test Conditions COUT(1) Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO) 8p F V OUT = 0V CIN(1) Input Capacitance (SCL, WP, MR) 6 pF V IN = 0V D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions –VREF tRPDX = 5µs worst case Output Pin VxMON R C ∆V = 100mV∆V Vref X40030, X40031, X40034, X40035
15 FN8114.0 April 28, 2005 EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS SYMBOL TABLE A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON, V3MON 4.6kΩ RESET 30pF 2.06kΩ V2FAIL, VCC 4.6kΩ 30pF WDO V3FAIL Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INP UTS OUTPUTS to HIGH Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF X40030, X40031, X40034, X40035
16 FN8114.0 April 28, 2005 TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. Max. Unit tWC(1) Write Cycle Time 5 10 ms tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition X40030, X40031, X40034, X40035
17 FN8114.0 April 28, 2005 Power Fail Timings RESET/RESET/MR Timings V2MON or V2FAIL or tR tF tRPDX VRVALID V3MON V3FAIL LOWLINE or VCC VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3 [ [ VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID MR tMD tIN1 X40030, X40031, X40034, X40035
18 FN8114.0 April 28, 2005 LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Notes: (1) V CC = 5V at 25°C. (2) Values based on characterization data only. Watchdog Time Out For 2-Wire Interface Symbol Parameters Min. Typ. (1) Max. Unit tRPD1(2) tRPDL VTRIP1 to RESET/RESET (Power down only) VTRIP1 to LOWLINE 5µ s t LR LOWLINE to RESET/RESET delay (Power down only) [= tRPD1-tRPDL] 500 ns tRPDX(2) VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) 5µ s tPURST Power On Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) PUP1=1, PUP0=0 PUP1=1, PUP0=1 (2) 200 400(2) 800(2) ms ms ms ms t F VCC, V2MON, V3MON, Fall Time 20 mV /µs tR VCC, V2MON, V3MON, Rise Time 20 mV /µs VRVALID Reset Valid VCC 1V tMD MR to RESET/ RESET delay (activation only) 500 ns tin1 Pulse width for MR 5µ s tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1 = 1, WD0 = 1 (factory setting) 1.4 (2) 200(2) OFF s ms ms tRST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs < tWDO tRST WDO SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1) X40030, X40031, X40034, X40035
19 FN8114.0 April 28, 2005 VTRIPX Set/Reset Conditions VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range - X40030, X40031 1.7 4.75 V VTRAN2A VTRIP2 Set Voltage Range - X40034, X40035 0.9 3.5 V VTRAN3 VTRIP3 Set Voltage Range 1.7 4.75 V Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs SCL SDA VCC/V2MON/V3MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 0Dh* sets VTRIP1 sets VTRIP2 sets VTRIP3 01h* 09h* 03h* 0Bh* 0Fh* resets VTRIP3 resets VTRIP2 resets VTRIP1 Start * all others reserved 00h X40030, X40031, X40034, X40035
20 FN8114.0 April 28, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X40030, X40031, X40034, X40035
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8114.0 April 28, 2005
ORDERING INFORMATION
-40oC–85oC X40030S14I-A X40031S14I-A 14L TSSOP 0 oC–70oC X40030V14-A X40031V14-A -40oC–85oC X40030V14I-A X40031V14I-A -40oC–85oC X40030S14I-B X40031S14I-B 14L TSSOP 0 oC–70oC X40030V14-B X40031V14-B -40oC–85oC X40030V14I-B X40031V14I-B -40oC–85oC X40030S14I-C X40031S14I-C 14L TSSOP 0 oC–70oC X40030V14-C X40031V14-C -40oC–85oC X40030V14I-C X40031V14I-C -40oC–85oC X40030S14I-A X40031S14I-A 14L TSSOP 0 oC–70oC X40030V14-A X40031V14-A -40oC–85oC X40030V14I-A X40031V14I-A -40oC–85oC X40030S14I-B X40031S14I-B 14L TSSOP 0 oC–70oC X40030V14-B X40031V14-B -40oC–85oC X40030V14I-B X40031V14I-B -40oC–85oC X40030S14I-C X40031S14I-C 14L TSSOP 0 oC–70oC X40030V14-C X40031V14-C -40oC–85oC X40030V14I-C X40031V14I-C 14-Lead Package X4043XX YYWWXX I – Industrial 0/1/4/5 Package - S/V Blank – Commercial WW – Workweek YY – Year A, B, or C X40030, X40031, X40034, X40035