X40030_13 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Triple voltage detection and reset assertion - Standard reset threshold settings; see Table 1 on page 5. - Adjust low voltage reset threshold voltages using special programming sequence - Reset signal valid to V CC = 1V - Monitor three separate voltages
  • Fault detection register
  • Selectable power-on reset time-out (0.05s, 0.2s, 0.4s, 0.8s)
  • Selectable watchdog timer interval (25ms, 200ms, 1.4s or off)
  • Debounced manual reset input
  • Low power CMOS - 25µA typical standby current, watchdog on - 6µA typical standby current, watchdog off
  • 400kHz 2-wire interface
  • 2.7V to 5.5V power supply operation
  • Available in 14 Ld SOIC and 14 Ld TSSOP packages
  • Monitor voltages: 5V to 0.9V
  • Independent core voltage monitor
  • Pb-free available (RoHS compliant)

Applications

  • Communication equipment - Routers, hubs, switches - Disk arrays, network storage
  • Industrial systems - Process control - Intelligent instrumentation
  • Computer systems - Computers - Network servers Data Sheet August 25, 2008

2 FN8114.2 August 25, 2008 Block Diagram V3FAIL V2FAIL WDO MR LOWLINE RESET RESET X40030/34 X40031/35 V3 MONITOR LOGIC V2 MONITOR LOGIC FAULT DETECTION REGISTER STATUS REGISTER DATA REGISTER COMMAND DECODE TEST AND CONTROL LOGIC POWER-ON, MANUAL RESET LOW VOLTAGE RESET GENERATIONVCC MONITOR LOGIC V3MON V2MON SDA WP SCL VCC (V1MON) WATCHDOG AND RESET LOGIC - VTRIP3 - VTRIP2 VTRIP1 VCC OR V2MON* X40030, X40031, X40034, X40035

3 FN8114.2 August 25, 2008

Ordering Information

(Note 1) PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. # PART NUMBER WITH RESET X40034S14-B X40034S B 2.9V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40034S14-C X40034S C 1.0 to 3.6 1.0V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40034S14I-A X40034S IA 1.3 to 5.5 1.3V ±50mV 3.1V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40034S14I-B X40034S IB 2.9V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40034S14I-C X40034S IC 1.0 to 3.6 1.0V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40034V14-B X4003 4VB 2.9V ±50mV 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40034V14-C X4003 4VC 1.0 to 3.6 1.0V ±50mV 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40034V14I-B X4003 4VIB 2.9V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40034V14I-C X4003 4VIC 1.0 to 3.6 1.0V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40030S14I-C X40030S IC -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40030V14-C X4003 0VC 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40030V14I-C X4003 0VIC -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40030S14Z-B (Note 2) X40030S ZB 0 to +70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40030S14I-B X40030S IB -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40030S14IZ-B (Note 2) X40030S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40030V14-B X4003 0VB 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40030V14I-B X4003 0VIB -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40030S14-A X40030S A 4.6V ±50mV 2.9V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40030S14Z-A (Note 2) X40030S ZA 0 to +70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40030S14I-A X40030S IA -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40030S14IZ-A (Note 2) X40030S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40030V14-A X4003 0VA 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40030V14I-A X4003 0VIA -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 PART NUMBER WITH RESET X40035S14-B X40035S B 2.9V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40035S14-C X40035S C 1.0 to 3.6 1.0V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40035S14I-A X40035S IA 1.3 to 5.5 1.3V ±50mV 3.1V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40035S14I-B X40035S IB 2.9V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40035S14I-C X40035S IC 1.0 to 3.6 1.0V ±50mV -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40035V14-B X4003 5VB 2.9V ±50mV 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40030, X40031, X40034, X40035

4 FN8114.2 August 25, 2008 X40035V14I-B X4003 5VIB 2.9V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40035V14I-C X4003 5VIC 1.0 to 3.6 1.0V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40031S14I-C X40031S IC -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40031V14-C X4003 1VC 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40031V14I-C X4003 1VIC -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40031S14Z-B (Note 2) X40031S ZB 0 to +70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40031S14I-B X40031S IB -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40031S14IZ-B (Note 2) X40031S ZIB -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40031V14-B X4003 1VB 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40031V14I-B X4003 1VIB -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 X40031S14-A X40031S A 4.6V ±50mV 2.9V ±50mV 0 to +70 14 Ld SOIC (150 mil) MDP0027 X40031S14Z-A (Note 2) X40031S ZA 0 to +70 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40031S14I-A X40031S IA -40 to +85 14 Ld SOIC (150 mil) MDP0027 X40031S14IZ-A (Note 2) X40031S ZIA -40 to +85 14 Ld SOIC (150 mil) (Pb-free) MDP0027 X40031V14-A X4003 1VA 0 to +70 14 Ld TSSOP (4.4mm) MDP0044 X40031V14I-A X4003 1VIA -40 to +85 14 Ld TSSOP (4.4mm) MDP0044 NOTES: 1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. Ordering Information (Continued) PART NUMBER (Note 1) PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (°C) PACKAGE PKG. DWG. # X40030, X40031, X40034, X40035

minimum reset component count. does not change, even after cycling the power. TABLE 1. SELECTION TABLE

6 FN8114.2 August 25, 2008 Pinouts X40030, X40034 (14 LD SOIC, TSSOP) TOP VIEW X40031, X40035 (14 LD SOIC, TSSOP) TOP VIEW V3MON VSS VCC SDA SCL LOWLINE NC RESET V2MON MR WP V3FAIL WDO V2FAIL V3MON V CC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL Pin Descriptions PIN NAME FUNCTION 1V 2 F A I L V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 2V 2 M O N V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input (X40034, X40035). 3L O W L I N E Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4 NC No connect. 5M R Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter.

6 RESET /

RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40031, X40035) This open drain pin is an active LOW output ,which goes LOW whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. 7V SS Ground 8S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull-down resistor (>10MΩ typical). 11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. Connect V3MON to VSS or VCC when not used. The V3MON comparator is supplied by the V3MON input. 12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin. 13 WDO WDO Output. WDO is an active LOW, open drain output, which goes active whenever the watchdog timer goes active. 14 V CC Supply Voltage. X40030, X40031, X40034, X40035

be: VTRIPX (desired) – (VTRIPX (actual) – VTRIPX (desired)). Note: This operation does not corrupt the memory array. must then be brought LOW to complete the operation. Note: This operation does not corrupt the memory array. not change when power is removed. two step process, with the whole sequence requiring 3 steps. See “Writing to the Control Registers” on page 11. be consistent with the bus protocol. FIGURE 5. SAMPLE V TRIP RESET CIRCUIT

FIGURE 6. V TRIPX SET/RESET SEQUENCE (X = 1, 2, 3)

WEL bit and zeroes to the other bits of the control register. time delay. The nominal power-up times are shown in Table 2. Timer. The options are shown in Table 3.

  • Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write (operation preceded by a start and ended with a stop).
  • Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required (operation proceeded by a start and ended with a stop).
  • Write one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s is the BP bit and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.
  • A read operation occurring between any of the previous operations will not interrupt the register write operation.
  • The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, or power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Note: t PURST is set to 200ms as factory default. Watchdog Timer bits are shipped disabled. Fault Detection Register (FDR) The Fault Detection Register provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile. The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR. At power-up, the FDR is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring can take place. In the event of any one of the monitored sources fail, the corresponding bit in the register will change from a “1” to a “0” to indicate the failure. At this moment, the system should perform a read to the register and note the cause of the reset. After reading the register, the system should reset the register back to all “1” again. The state of the FDR can be read at any time by performing a random read at address 0FFh, using the special preamble. The FDR can be read by performing a random read at 0FFh address of the register at any time. Only one byte of data is read by the register read operation.

TABLE 2. NOMINAL POWER-UP TIMES TABLE 3. WATCHDOG TIMER OPTIONS

15 FN8114.2 August 25, 2008 Absolute Maximum Ratings Thermal Information Chip Supply Voltage Monitored Voltage http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. DC Operating Characteristics Over the recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP (Note 7) MAX (Note 3) UNIT ICC1 (Note 4) Active Supply Current (VCC) Read V IL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz 1.5 mA ICC2 (Note 4) Active Supply Current (VCC) Write 3.0 mA ISB1 (Note 4) Standby Current (VCC) AC (WDT off) V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz 61 0 µ A ISB2 (Note 5) Standby Current (VCC) DC (WDT on) V SDA = VSCL = VCC Others = GND or VCC 25 30 µA ILI Input Leakage Current (SCL, MR, WP) V IL = GND to VCC 10 µA ILO Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, RESET) VSDA = GND to VCC Device is in Standby (Note 5) 10 µA VIL (Note 6) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 V CC x 0.3 V VIH (Note 6) Input HIGH Voltage (SDA, SCL, MR, WP) V CC x 0.7 V CC + 0.5 V VHYS (Note 9) Schmitt Trigger Input Hysteresis Fixed Input Level 0.2 V VCC Related Level 0.05 x V CC V VOL Output LOW Voltage (SDA, RESET/RESET, LOWLINE, V2FAIL, V3FAIL, WDO) IOL = 3.0mA (2.7V to 5.5V) IOL = 1.8mA (2.7V to 3.6V) 0.4 V VOH Output (RESET, LOWLINE) HIGH Voltage I OH = -1.0mA (2.7V to 5.5V) V CC – 0.8 V IOH = -0.4mA (2.7V to 3.6V) V CC – 0.4 VCC SUPPLY VTRIP1 (Note 8) VCC Trip Point Voltage Range 2.0 4.75 V X40030, X40031-A, X40034, X40035 4.55 4.6 4.65 V X40030, X40031-B 4.35 4.4 4.45 V X40030, X40031-C 2.85 2.9 2.95 V SECOND SUPPLY MONITOR IV2 V2MON Current 15 µA X40030, X40031, X40034, X40035

16 FN8114.2 August 25, 2008 Equivalent Input Circuit for VxMON (x = 1, 2, 3) VTRIP2 (Note 8) V2MON Trip Point Voltage Range X40030, X40031 1.7 4.75 V X40034, X40035 0.9 3.5 V X40030, X40031-A 2.85 2.9 2.95 V X40030, X40031-B 2.55 2.6 2.65 V X40030, X40031-C 2.15 2.2 2.25 V X40034, X40035-A and B 1.25 1.3 1.35 V X40034, X40035-C 0.95 1.0 1.05 V t RPD2 (Note 9) VTRIP2 to V2FAIL 5µ s THIRD SUPPLY MONITOR IV3 V3MON Current 15 µA VTRIP3 (Note 8) V3MON Trip Point Voltage Range 1.7 4.75 V X40030, X40031 1.65 1.7 1.75 V X40034, X40035-A 3.05 3.1 3.15 V X40034, X40035-B and C 2.85 2.9 2.95 V t RPD3 (Note 9) VTRIP3 to V3FAIL 5µ s NOTES: 4. The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. 5. The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. 6. V IL Min. and VIH Max. are for reference only and are not tested. 7. At +25°C, V CC = 3V 8. See ordering information for standard programming levels. For custom programmed levels, contact factory. 9. Based on characterization data. DC Operating Characteristics Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP (Note 7) MAX (Note 3) UNIT –VREF tRPDX = 5µs WORST CASE OUTPUT PIN VxMON R C ΔV = 100mVΔV Vref Capacitance SYMBOL PARAMETER TEST CONDITIONS MAX (Note 3) UNIT COUT Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO)V OUT = 0V 8 pF CIN Input Capacitance (SCL, WP , MR) V IN = 0V 6 pF X40030, X40031, X40034, X40035

17 FN8114.2 August 25, 2008 Equivalent AC Output Load Circuit For Vcc = 5V Symbol Table AC Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load SDA 30pF V2MON, V3MON 4.6kΩ RESET 30pF 2.06kΩ V2FAIL, VCC 4.6kΩ 30pF WDO V3FAIL Must be steady Will be steady Ma y change from LO W Will change from LO W to HIGH Ma y change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INPUTS OUTPUTS to HIGH AC Characteristics SYMBOL PARAMETER MIN (Note 3) MAX (Note 3) UNIT fSCL SCL Clock Frequency 400 kHz tIN Pulse Width Suppression Time at Inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the Bus Free Before Start of New Transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0µ s tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 + 0.1Cb (Note 10) 300 ns tF SDA and SCL Fall Time 20 + 0.1Cb (Note 10) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0µ s Cb Capacitive Load for Each Bus Line 400 pF NOTE: 10. Cb = total capacitance of one bus line in pF X40030, X40031, X40034, X40035

18 FN8114.2 August 25, 2008 Timing Diagrams Bus Timing WP Pin Timing Write Cycle Timing tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA tHD:WP SCL SDA IN WP tSU:WP CLK 1 CLK 9 SLAVE ADDRESS BYTE START SCL SDA tWC 8TH BIT OF LAST BYTE ACK STOP CONDITION START CONDITION Nonvolatile Write Cycle Timing SYMBOL PARAMETER MIN (Note 3) TYP MAX (Note 3) UNIT tWC (Note 11) Write Cycle Time 5 10 ms NOTE: 11. t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. X40030, X40031, X40034, X40035

19 FN8114.2 August 25, 2008 Power Fail Timings RESET/RESET/MR Timings V2MON OR V2FAIL OR tR tF tRPDX VRVALID V3MON V3FAIL LOWLINE OR VCC VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3 [ [ VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID MR tMD tIN1 Low Voltage and Watchdog Timings Parameters (@ +25°C, VCC = 5V) SYMBOL PARAMETERS MIN (Note 3) TYP (Note 12) MAX (Note 3) UNIT tRPD1, tRPDL (Note 13) VTRIP1 to RESET/RESET (Power-down only), VTRIP1 to LOWLINE 5µ s t LR LOWLINE to RESET/RESET Delay (Power-down Only) [= tRPD1 - tRPDL] 500 ns tRPDX (Note 13) VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) 5 µs tPURST Power-on Reset Delay PUP1 = 0, PUP0 = 0 50 (Note 13) ms PUP1 = 0, PUP0 = 1 (Factory Setting) 200 ms PUP1 = 1, PUP0 = 0 400 (Note 13) ms PUP1 = 1, PUP0 = 1 800 (Note 13) ms X40030, X40031, X40034, X40035

20 FN8114.2 August 25, 2008 Watchdog Time Out for 2-Wire Interface tF VCC,V2MON, V3MON, Fall Time 20 mV /µs tR VCC, V2MON, V3MON, Rise Time 20 mV /µs VRVALID Reset Valid VCC 1V tMD MR to RESET/RESET Delay (activation only) 500 ns tin1 Pulse Width for MR 5µ s tWDO Watchdog Timer Period WD1 = 0, WD0 = 0 1.4 s WD1 = 0, WD0 = 1 200 ms WD1 = 1, WD0 = 0 25 ms WD1 = 1, WD0 = 1 (Factory Setting) OFF tRST1 Watchdog Reset Time Out Delay 100 200 300 ms WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 tRST2 Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0 12.5 25 37.5 ms tRSP Watchdog Timer Restart Pulse Width 1 µs NOTES: 12. V CC = 5V at +25°C. 13. Values based on characterization data only. Low Voltage and Watchdog Timings Parameters (@ +25°C, VCC = 5V) (Continued) SYMBOL PARAMETERS MIN (Note 3) TYP (Note 12) MAX (Note 3) UNIT < tWDO tRST WDO SDA START tWDO tRST SCL START tRSP WDT RESTART START SDA SCL MINIMUM SEQUENCE TO RESET WDT CLOCKIN (0 OR 1) X40030, X40031, X40034, X40035

21 FN8114.2 August 25, 2008 VTRIPX Set/Reset Conditions SCL SDA VCC/V2MON/V3MON(VTRIPX) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 0DH* SETS VTRIP1 SETS VTRIP2 SETS VTRIP3 01H* 09H* 03H* 0BH* 0FH* RESETS VTRIP3 RESETS VTRIP2 RESETS VTRIP1 START * ALL OTHERS RESERVED 00h VTRIP1, VTRIP2, VTRIP3 Programming Specifications VCC = 2.0V to 5.5V; Temperature = +25°C PARAMETER DESCRIPTION MIN (Note 3) MAX (Note 3) UNIT tVPS WDO Program Voltage Setup Time 10 µs tVPH WDO Program Voltage Hold Time 10 µs tTSU VTRIPx Level Setup Time 10 µs tTHD VTRIPx Level Hold (stable) Time 10 µs tWC VTRIPx Program Cycle 10 ms tVPO Program Voltage Off Time Before Next Cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range - X40030, X40031 1.7 4.75 V VTRAN2A VTRIP2 Set Voltage Range - X40034, X40035 0.9 3.5 V VTRAN3 VTRIP3 Set Voltage Range 1.7 4.75 V Vtv VTRIPx Set Voltage Variation After Programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup Time 10 µs X40030, X40031, X40034, X40035

22 FN8114.2 August 25, 2008 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994 X40030, X40031, X40034, X40035

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8114.2 August 25, 2008 X40030, X40031, X40034, X40035 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.