X40010S8-A

X40010 XICOR | Alldatasheet

Document overview

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Technical content

REV 1.3.4 7/12/02 Characteristics subject to change without notice. 1 of 25 www.xicor.com X40010/X40011/X40014/X40015 Dual Voltage Monitor with Integrated CPU Supervisor

FEATURES

• Dual voltage detection and reset assertion —Standard reset threshold settings See Selection table on page 2. —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to V CC = 1V —Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms, 1.4s, off)
• Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages —8-lead SOIC, TSSOP

APPLICATIONS

• Communication Equipment —Routers, Hubs, Switches —Disk Arrays, Network Storage
• Industrial Systems —Process Control —Intelligent Instrumentation
• Computer Systems —Computers —Network Servers

DESCRIPTION

The X40010/11/14/15 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary voltage supervision, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to V CC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V TRIP1 point. RESET/ RESET is active until V CC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are avail- able, however, Xicor’s unique circuits allows the BLOCK DIAGRAM V2FAIL WDO RESET RESET X40010/14 X40011/15 Fault Detection Register Status Register Data Register Command Decode Test & Control Logic Power on, Low Voltage Reset Generation V2MON SDA SCL VCC (V1MON) -User Programmable Threshold Reset Logic VTRIP1 User Programmable VTRIP2 Watchdog Timer and Reset Logic V2MON VCC *X40010/11 = V2MON* X40014/15 = VCC

• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor New Features Preliminary Datasheet

X40010/X40011/X40014/X40015 – Preliminary Characteristics subject to change without notice. 2 of 25REV 1.3.4 7/12/02 www.xicor.com threshold for either voltage monitor to be repro- grammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device features a 2-wire interface and software protocol allowing operation on an I C bus. Dual Voltage Monitors *Voltage monitor requires V CC to operation. Others are independent of V CC PIN CONFIGURATION Device Expected System Voltages Vtrip1(V) Vtrip2(V) POR (system) X40010/11 5V; 3V or 3.3V 5V; 3V 3V; 3.3V; 1.8V 2.0–4.75* 4.55–4.65* 4.35–4.45* 2.85–2.95* 1.70–4.75 2.85–2.95 2.55–2.65 1.65–1.75 RESET = X40010 RESET = X40011 X40014/15 3V; 3.3V; 1.5V 3V; 1.5V 3V or 3.3V; 1.1 or 1.2V 2.0–4.75* 2.85–2.95* 2.55–2.65* 2.85–2.95* 0.90–3.50* 1.25–1.35* 1.25–1.35* 0.95–1.05* RESET = X40014 RESET = X40015 PIN DESCRIPTION Pin Name FunctionSOIC TSSOP 1 3 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V TRIP2 and goes HIGH when V2MON exceeds V TRIP2 . There is no power up reset delay circuitry on this pin. 2 4 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the V TRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V SS or V CC when not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V CC Input (X40014/15). 3 5 RESET / RESET RESET Output. (X40011/15) This is an active LOW, open drain output which goes active when- ever V CC falls below V TRIP1 . It will remain active until V CC rises above V TRIP1 and for the t PURST thereafter. RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever V CC falls below V TRIP1 . It will remain active until V CC rises above V TRIP1 and for the t PURST there- after. 46 V SS Ground SDA VCC RESET /RESET VSS V2MON SCL WDO V2FAIL RESET/RESET SCL VSS SDA V2FAIL V2MON WDO VCC X40010/14, X40011/15 X40010/14, X40011/15 8-Pin SOIC 8-Pin TSSOP

Characteristics subject to change without notice. pins active. This signal provides several benefits. operate with insufficient voltage. prior to initialization of the circuit. reducing the likelihood of data corruption on power up. monitors the power supply connected to the V2MON pin. = 0, V2MON can still be monitored. Figure 1. Two Uses of Multiple Voltage Monitoring Notice: No external components required to monitor two voltages. requires a pull up resistor and the input buffer is always active (not gated). The Serial Clock controls the serial bus timing for data input and output.

nal value of 1.7V or lesser. nonvolatile and do not change when power is removed. process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7. after the first byte is entered. col, but a stop is not required to end this operation. Figure 4. Sample VTRIP Reset Circuit

Figure 5. VTRIPX Set/Reset Sequence (X = 1, 2) tile latch that powers up in the LOW (disabled) state. to the other bits of the control register. operation immediately after the stop condition.

X40010/X40011/X40014/X40015 – Preliminary PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power up times are shown in the following table. WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write a one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvola- tile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. FAULT DETECTION REGISTER The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and three Low Voltage Fail bits are volatile. The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this fault detection register. PUP1 PUP0 Power on Reset Delay ( tPURST ) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 65432 1 0 LV1F LV2F 0 WDF 0 0 0 0

Figure 9. Read Sequence dom Reads, and Sequential Reads. operation for initialization. address, acknowledge, and data transfer sequence.

Figure 10. Acknowledge Polling Sequence the ninth clock cycle and then issue a stop condition. address, acknowledge, and data transfer sequence. needs to read, but is not ready for the data. acknowledge and then issuing a stop condition. for the acknowledge and data transfer sequence.

is undefined on a power up condition. – The device is in the low power standby state. – SDA pin is the input mode. Signal is active for tPURST . – The WEL bit must be set to allow write operations. Figure 14. Sequential Read Sequence

X40010/X40011/X40014/X40015 – Preliminary ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS *See Ordering Info Temperature Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Version Chip Supply Voltage Monitored* Voltages X40010/11 -A or -B 2.7V to 5.5V 2.6V to 5V X40010/11- C, X40014/15 2.7V to 5.5V 1V to 3.6V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions ICC1 (1) Active Supply Current (VCC ) Read 1.5 mA V IL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz ICC2 (1) Active Supply Current (VCC ) Read 3.0 mA ISB1 (1)(6) Standby Current (VCC ) AC (WDT off) 6 10 µA V IL = VCC x 0.1 VIH = VCC x 0.9 fSCL , fSDA = 400kHz ISB2 (2)(6) Standby Current (VCC ) DC (WDT on) 25 30 µA V SDA = VSCL = VCC Others = GND or VCC ILI Input Leakage Current (SCL) 10 µA V IL = GND to VCC ILO Output Leakage Current (SDA, V2FAIL, WDO , RESET) 10 µA V SDA = GND to VCC Device is in Standby(2) VIL (3) Input LOW Voltage (SDA, SCL) -0.5 VCC x 0.3 V VIH (3) Input HIGH Voltage (SDA, SCL) VCC x 0.7 VCC + 0.5 V VHYS (6) Schmitt Trigger Input Hysteresis

• Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage (SDA, RESET/ RESET , V2FAIL, WDO ) IOL = 1.8mA (2.7–3.6V) VOH Output (RESET) HIGH Voltage VCC – 0.8 VCC – 0.4 VI OH = -1.0mA (2.7–5.5V) IOH = -0.4mA (2.7–3.6V)

X40010/X40011/X40014/X40015 – Preliminary Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that ini- tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) VIL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, VCC = 5V. (5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2) CAPACITANCE Note: (1) This parameter is not 100% tested. VCC Supply VTRIP1 (5) VCC Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 V X40010/11-A 4.35 4.4 4.45 V X40010/11-B 2.85 2.9 2.95 V X40010/11-C, X40014/15-A&C 2.55 2.6 2.65 V X40014/15-B t RPD2 (6) VTRIP2 to V2FAIL 5µ S Second Supply Monitor IV2 V2MON Current 15 µA VTRIP2 (5) V2MON Trip Point Voltage Range 1.7 0.9 4.75 3.5 V V X40010/11 X40014/15 2.85 2.9 2.95 V X40010/11-A 2.55 2.6 2.65 V X40010/11-B 1.65 1.7 1.75 V X40010/11-C 1.25 1.3 1.35 V X40014/15-A&B 0.95 1.0 1.05 V X40014/15-C Symbol Parameter Max. Unit Test Conditions C OUT (1) Output Capacitance (SDA, RESET, RESET, V2FAIL, WDO ) 8p FV OUT = 0V C IN (1) Input Capacitance (SCL) 6 pF V IN = 0V D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ. (4) Max. Unit Test Conditions –VREF tRPDX = 5µs worst case Output Pin VxMON R C ∆V = 100mV∆V Vref

X40010/X40011/X40014/X40015 – Preliminary EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V A.C. TEST CONDITIONS SYMBOL TABLE Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load SDA 30pF V2MON 4.6KΩ RESET 30pF 2.06KΩ V2FAIL VOUT 4.6KΩ 30pF WDO Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INPUTS OUTPUTS

X40010/X40011/X40014/X40015 – Preliminary A.C. CHARACTERISTICS Note: (1) Cb = total capacitance of one bus line in pF . TIMING DIAGRAMS Bus Timing Symbol Parameter 400kHz UnitMin. Max. fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUF tR tDHtAA

X40010/X40011/X40014/X40015 – Preliminary Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Power Fail Timings Symbol Parameter Min. Typ. (1) Max. Unit tWC (1) Write Cycle Time 5 10 ms SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition V2MON V2FAIL or tR tF tRPDX VRVALIDV3FAIL LO WLINE or VCC or VTRIPX tRPDXtRPDX tRPDL tRPDL tRPDL X = 2, 3

X40010/X40011/X40014/X40015 – Preliminary RESET/RESET Timings LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Notes: (1) VCC = 5V at 25°C. (2) Values based on characterization data only. Symbol Parameters Min. Typ. (1) Max. Unit tRPD1 (2) VTRIP1 to RESET/RESET (Power down only) 5 µs tRPDX (2) VTRIP2 to V2FAIL 5µ s tPURST Power On Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) PUP1=1, PUP0=0 PUP1=1, PUP0=1 200 (2) 400(2) 800(2) ms ms ms ms t F VCC, V2MON , Fall Time 20 mV /µs tR VCC, V2MON , Rise Time 20 mV /µs VRVALID Reset Valid VCC 1V tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1=1, WD0=1 (factory setting) 1.4 (2) 200(2) OFF s ms ms t RST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms t RST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 µs VCC VTRIP1 RESET RESET tPURST tPURST tR tF tRPD1 VRVALID

X40010/X40011/X40014/X40015 – Preliminary Watchdog Time Out For 2-Wire Interface VTRIPX Set/Reset Conditions < tWDO tRST WDO SDA Start tWDO tRST SCL Start tRSP WDT Restart Start SDA SCL Minimum Sequence to Reset WDT Clockin (0 or 1) SCL SDA VCC /V2MON(VTRIPX ) WDO tTSU tTHD tVPH tVPS VP tWC tVPO A0h 07 70 7 sets VTRIP1 sets VTRIP2 01h* 09h* 03h* 0Bh* resets VTRIP2 resets VTRIP1 Start * all others reserved 00h

X40010/X40011/X40014/X40015 – Preliminary VTRIP1, VTRIP2, Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range – X40010/11 1.7 4.75 V VTRAN2A VTRIP2 Set to Voltage Range – X40014/15 0.9 3.5 V Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 µs

X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic, SOIC, Package Code S8 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Code V8 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16)(7.72) (1.78) (0.42) (0.65) All Measurements Are Typical

X40010/X40011/X40014/X40015 – Preliminary

ORDERING INFORMATION

Range V TRIP2 Range Package Operating Temperature Range Part Number with RESET Part Number with RESET 2.9-5.5 4.6V±50mV 2.9V±50mV 8L SOIC 0 oC - 70oC X40010S8-A X40011S8-A -40oC - 85oC X40010S8I-A X40011S8I-A 8L TSSOP 0 oC - 70oC X40010V8-A X40011V8-A -40oC - 85oC X40010V8I-A X40011V8I-A 2.6-5.5 4.4V±50mV 2.6V±50mV 8L SOIC 0 oC - 70oC X40010S8-B X40011S8-B -40oC - 85oC X40010S8I-B X40011S8I-B 8L TSSOP 0 oC - 70oC X40010V8-B X40011V8-B -40oC - 85oC X40010V8I-B X40011V8I-B 1.7-3.6 2.9V±50mV 1.7V±50mV 8L SOIC 0 oC - 70oC X40010S8-C X40011S8-C -40oC - 85oC X40010S8I-C X40011S8I-C 8L TSSOP 0 oC - 70oC X40010V8-C X40011V8-C -40oC - 85oC X40010V8I-C X40011V8I-C 1.3-3.6 2.9V±50mV 1.3V±50mV 8L SOIC 0 oC - 70oC X40014S8-A X40015S8-A -40oC - 85oC X40014S8I-A X40015S8I-A 8L TSSOP 0 oC - 70oC X40014V8-A X40015V8-A -40oC - 85oC X40014V8I-A X40015V8I-A 1.3-3.6 2.6V±50mV 1.3V±50mV 8L SOIC 0 oC - 70oC X40014S8-B X40015S8-B -40oC - 85oC X40014S8I-B X40015S8I-B 8L TSSOP 0 oC - 70oC X40014V8-B X40015V8-B -40oC - 85oC X40014V8I-B X40015V8I-B 1.0-3.6 2.9V±50mV 1.0V±50mV 8L SOIC 0 oC - 70oC X40014S8-C X40015S8-C -40oC - 85oC X40014S8I-C X40015S8I-C 8L TSSOP 0 oC - 70oC X40014V8-C X40015V8-C -40oC - 85oC X40014V8I-C X40015V8I-C 8-Lead Package X4001XX YYWWXX I – Industrial 0/1/4/5 Package - S/V Blank – Commercial WW – Workweek YY – Year A, B, or C

X40010/X40011/X40014/X40015 – Preliminary ©Xicor, Inc. 2001 Patents PendingLIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.