X28C010 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Renesas
  • PDF pages: 20

Technical content

Features

  • Access time: 120ns
  • Simple byte and page write - Single 5V supply - No external high voltages or VPP control circuits - Self-timed
  • No erase before write
  • No complex programming algorithms
  • No overerase problem
  • Low power CMOS - Active: 50mA - Standby: 500µA
  • Software data protection - Protects data against system level inadvertent writes
  • High speed page write capability
  • Highly reliable Direct Write ™ cell - Endurance: 100,000 write cycles - Data retention: 100 years
  • Early end of write detection -D A T A polling - Toggle bit polling
  • X28HT010 is fuly functional @ +175°C Pinouts NC A16 A15 A12 I/O0 I/O1 I/O2 VSS VCC WE NC A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 X28C010 CERDIP Flat Pack SOIC (R) PGA X28C010 (Bottom View) I/O1 VSS I/O0 I/O2 I/O3 A15 NC VCC I/O4 I/O5 NC I/O7 A10 A11 I/O6 NC CE OE A 9 A 13 A16 3 NC NC WE NC A 14 A12 X28C010 (Top View) I/O0 A13 A11 A10 I/O7 A14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A 12 A 15 A 16 NC V CC WE NC OE CE EXTENDED LCC 23 243 3 1 15 1716 18 192014 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

X28C010, X28HT010 FN8105 Rev 1.00 Page 2 of 20 February 12, 2007

Ordering Information

(°C) PACKAGE PKG. DWG # X28C010D-12 X28C010D-12 120ns 0 to +70 32-Ld Cerdip F32.6 X28C010D-15 X28C010D-15 150ns 0 to +70 32-Ld Cerdip F32.6 X28C010DI X28C010DI - -40 to +85 32-Ld Cerdip F32.6 X28C010DI-12 X28C010DI-12 120ns -40 to +85 32-Ld Cerdip F32.6 X28C010DI-15 X28C010DI-15 150ns -40 to +85 32-Ld Cerdip F32.6 X28C010DM X28C010DM - -55 to +125 32-Ld Cerdip F32.6 X28C010DM-12 X28C010DM-12 120ns -55 to +125 32-Ld Cerdip F32.6 X28C010DM-15 X28C010DM-15 150ns -55 to +125 32-Ld Cerdip F32.6 X28C010DMB-12 C X28C010DMB-12 120ns MIL-STD-883 32-Ld Cerdip F32.6 X28C010DMB-15 C X28C010DMB-15 150ns MIL-STD-883 32-Ld Cerdip F32.6 X28C010DMB-20 C X28C010DMB-20 200ns MIL-STD-883 32-Ld Cerdip X28C010FI-12 X28C010FI-12 120ns -40 to +85 32-Ld Flat Pack X28C010FI-15 X28C010FI-15 150ns -40 to +85 32-Ld Flat Pack X28C010FI-20 X28C010FI-20 200ns -40 to +85 32-Ld Flat Pack X28C010FM X28C010FM - -55 to +125 32-Ld Flat Pack X28C010FM-12 X28C010FM-12 120ns -55 to +125 32-Ld Flat Pack X28C010FMB-12 C X28C010FMB-12 120ns MIL-STD-883 32-Ld Flat Pack X28C010FMB-15 C X28C010FMB-15 150ns MIL-STD-883 32-Ld Flat Pack X28C010K-25 X28C010K-25 250ns 0 to +70 36-Ld Pin Grid Array G36.760x 760A X28C010KM-12 X28C010KM-12 120ns -55 to +125 36-Ld Pin Grid Array G36 .760x760A X28C010KM-25 X28C010KM-25 250ns -55 to +125 36-Ld Pin Grid Array G36 .760x760A X28C010KMB-12 C X28C010KMB-12 120ns MIL-STD-883 36-Ld Pin Grid Arra y G36.760x760A X28C010KMB-15 C X28C010KMB-15 150ns MIL-STD-883 36-Ld Pin Grid Arra y G36.760x760A X28C010NM-12 X28C010NM-12 120ns -55 to +125 32-Ld Extended LCC X28C010NM-15 X28C010NM-15 150ns -55 to +125 32-Ld Extended LCC X28C010NMB-12 C X28C010NMB-12 120ns MIL-STD-883 32-Ld Extended LCC X28C010NMB-15 C X28C010NMB-15 150ns MIL-STD-883 32-Ld Extended LCC X28C010RI-12 X28C010RI-12 120ns -40 to +85 32-Ld Ceramic SOIC (Gull Wing) X28C010RI-20 X28C010RI-20 200ns -40 to +85 32-Ld Ceramic SOIC (Gull Wing) X28C010RI-20T1 X28C010RI-20 200ns -40 to +85 32-Ld Ceramic SOIC (Gu ll Wing) X28C010RM-15 X28C010RM-15 150ns -55 to +125 32-Ld Ceramic SOIC (Gul l Wing) X28C010RMB-25 C X28C010RMB-25 250ns MIL-STD-883 32-Ld Ceramic SOIC (Gull Wing) X28HT010W 200ns -40 to +175 Wafer

X28C010, X28HT010 FN8105 Rev 1.00 Page 3 of 20 February 12, 2007 Block Diagram Pin Descriptions Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C010/X28HT010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C010/X28HT010. Back Bias Voltage (VBB) (X28HT010 only) It is required to provide -3V on pin 1. This negative voltage improves higher temperature functionality. Device Operation Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C010/X28HT010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. X Buffers Latches and Decoder I/O Buffers and Latches Y Buffers Decoder Control Logic and Timing 1Mbit EEPROM Array I/O0-I/O7 Data Inputs/Outputs CE OE VCC VSS WE A0-A7 Latches and A8-A16 Pin Names SYMBOL DESCRIPTION A0-A16 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect VBB*- 3 V *VBB applies to X28HT010 only.

X28C010, X28HT010 FN8105 Rev 1.00 Page 9 of 20 February 12, 2007 Active Supply Current vs. Ambient Temperature Standby Supply Current vs. Ambient Temperature ICC (RD) by Temperature Over Frequency -55 -10 +125 Ambient Temperature (°C) ICC WR (mA) +35 +80 VCC = 5V -55 -10 +125 0.15 0.2 0.25 0.3 Ambient Temperature (°C) ISB (mA) 0.05 +35 +80 VCC = 5V 0.1 03 1 5 5.0 V CC Frequency (MHz) ICC RD (mA) -55°C +25°C +125°C

X28C010, X28HT010 FN8105 Rev 1.00 Page 10 of 20 February 12, 2007 Absolute Maximum Ratings Reco mmended Operating Conditions Temperature under bias Lead temperature the device at these or any other conditions (above those indicate d in the operational sections of this specification) is not im plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ICC VCC Current (Active) (TTL Inputs) CE = OE = VIL, WE = VIH, All I/O’s = Open, Address Inputs = 0.4V/2.4V Levels @ f = 5MHz 50 mA ISB1 VCC Current (Standby) (TTL Inputs) CE = VIH, OE = VIL, All I/O’s = Open, Other Inputs = VIH 3m A ISB2 VCC Current (Standby) (CMOS Inputs) CE = VCC - 0.3V, OE = VIL, All I/O’s = Open, Other Inputs = VCC 500 µA ILI Input Leakage Current V IN = VSS to VCC 10 µA VIN = VSS to VCC (Note 2) 20 µA ILO Output Leakage Current V OUT = VSS to VCC, CE = VIH 10 µA VOUT = VSS to VCC, CE = VIH (Note 2) 20 µA VlL (Note 1) Input LOW Voltage -1 0.8 V (Note 2) -1 0.6 V VIH (Note 1) Input HIGH Voltage 2V CC + 1 V (Note 2) 2.2 V CC + 1 V VOL Output LOW Voltage I OL = 2.1mA 0.4 V IOL = 1mA (Note 2) 0.5 V VOH Output HIGH Voltage I OH = -400µA 2.4 V IOH = -400µA 2.6 V IBB Back Bias Current V BB = -3V ±10% (Note 2) 200 µA NOTE: 1. VIL min. and VIH max. are for reference only and are not tested. 2. X28HT010W Power-Up Timing SYMBOL PARAMETER MAX UNIT tPUR (Note 3) Power-up to Read operation 100 µs tPUW (Note 3) Power-up to Write operation 5 ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL PARAMETER TEST CONDITIONS MAX UNIT CI/O (Note 3) Input/Output capacitance V I/O = 0V 10 pF CIN (Note 3) Input capacitance V IN = 0V 10 pF NOTE: 3. This parameter is periodically sampled and not 100% tested.

X28C010, X28HT010 FN8105 Rev 1.00 Page 11 of 20 February 12, 2007 Equivalent A.C. Load Circuit Symbol Table Endurance and Data Retention PARAMETER MIN MAX UNIT Endurance 10,000 Cycles per byte Endurance 100,000 Cycles per page Data Retention 100 Years A.C. Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V Mode Selection CE OE WE MODE I/O POWER LLH R e a d D OUT Active LHL W r i t e D IN Active H X X Standby and Write Inhibit High Z Standby X L X Write Inhibit — — X X H Write Inhibit — — 1.92k 100pF Output 1.37k WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance SYMBOL PARAMETER X28C010-12 X28C010-15 X28C010-20, X28HT010W X28C010-25 UNITMIN MAX MIN MAX MIN MAX MIN MAX READ CYCLE LIMITS tRC Read cycle time 120 150 200 250 ns tCE Chip enable access time 120 150 200 250 ns tAA Address access time 120 150 200 250 ns tOE Output enable access time 50 50 50 50 ns tLZ (Note 4) CE LOW to active output 0 0 0 0 ns tOLZ (Note 4) OE LOW to active output 0 0 0 0 ns tHZ (Note 4) CE HIGH to high Z output 50 50 50 50 ns tOHZ (Note 4) OE HIGH to high Z output 50 50 50 50 ns tOH Output hold from address change 0 0 0 0 ns

X28C010, X28HT010 FN8105 Rev 1.00 Page 12 of 20 February 12, 2007 Read Cycle NOTE: when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. tCE tRC Address CE OE WE Data Valid tOE tLZ tOLZ tOH tAA tHZ tOHZ Data I/O VIH HIGH Z Data Valid Write Cycle Limits SYMBOL PARAMETER MIN MAX UNIT tWC (Note 5) Write cycle time 10 ms tAS Address setup time 0 ns tAH Address hold time 50 ns tCS Write setup time 0 ns tCH Write hold time 0 ns tCW CE pulse width 100 ns tOES OE HIGH setup time 10 ns tOEH OE HIGH hold time 10 ns tWP WE pulse width 100 ns tWPH WE HIGH recovery 100 ns tDV Data valid 1µ s tDS Data setup 50 ns tDH Data hold 0 ns tDW Delay to next write 10 µs tBLC Byte load cycle 0.2 100 µs

X28C010, X28HT010 FN8105 Rev 1.00 Page 13 of 20 February 12, 2007 WE Controlled Write Cycle NOTE: 5. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete internal write operation. CE Controlled Write Cycle Address tAS tWC tAH tOES tDV tDS tDH tOEH CE WE OE Data In Data Out HIGH Z Data Valid tCS tCH tWP tWPH Address tAS tOEH tWC tAH tOES tWPH tCS tDV tDS tDH tCH CE WE OE Data In Data Out HIGH Z Data Valid tCW

X28C010, X28HT010 FN8105 Rev 1.00 Page 14 of 20 February 12, 2007 Page Write Cycle NOTES: 6. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 7. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. DATA Polling Timing Diagram (Note 8) WE OE (Note 5) Last Byte Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2 tWP tWPH tBLC tWC CE Address* (Note 7) I/O *For each successive write within the page write operation, A8-A16 should be the same or writes to an unknown address could occur. Address An DIN = X tWC tOEH tOES An An CE WE OE I/O7 tDW DOUT = X D OUT = X

X28C010, X28HT010 FN8105 Rev 1.00 Page 15 of 20 February 12, 2007 Toggle Bit Timing Diagram NOTE: 8. Polling operations are by definition read cycles and are therefore subject to read cycle timings. CE OE WE I/O6 tOES tDW tWC tOEH HIGH Z * I/O6 beginning and ending state will vary.

FN8105 Rev 1.00 Page 16 of 20 February 12, 2007 X28C010, X28HT010 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F32.6 MIL-STD-1835 GDIP1-T32 (D-16, CONFIGURATION A)

32 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.690 - 42.95 5 E 0.500 0.610 12.70 15.49 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N3 2 3 2 8 Rev. 0 8/06

X28C010, X28HT010 FN8105 Rev 1.00 Page 17 of 20 February 12, 2007 Packaging Information 32-Lead Ceramic Flat Pack Type F NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) Max. Pin 1 Index 13 2 0.120 (3.05) 0.090 (2.29) Min. 0.026 (0.66) 0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.830 (21.08) Max. 0.050 (1.27) BSC 0.440 0.430 (10.93) 0.347 (8.82) 0.330 (8.38) 0.005 (0.13) Min. 0.030 (0.76) Min. 1.228 (31.19) 1.000 (25.40)

X28C010, X28HT010 FN8105 Rev 1.00 Page 18 of 20 February 12, 2007 Packaging Information

0.300 BSC

0.458 Max. 0.450 ± 0.008 Pin 1 0.035 x 45° Ref. 0.085 ± 0.010 Typ. (3) Plcs.0.050 BSC

0.400 BSC

0.708 Max. 0.060/0.120 Pin #1 Index Corner 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NLT±0.005 (0.127) 0.700 ± 0.010 0.005/0.015 0.025 ± 0.003 0.050 ± 0.005 0.006/0.022Detail A Detail A 32-Pad Stretched Ceramic Leadless Chip Carrier Package Type N NOTES:

X28C010, X28HT010 FN8105 Rev 1.00 Page 19 of 20 February 12, 2007 Packaging Information 32-Lead Ceramic Small Outline Gull Wing Package Type R 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 0.340 ±0.007 See Detail “A” For Lead Information 0.440 Max. 0.560 Nom. 0.019 0.015 0.050 0.750 ±0.005 0.830 Max. 0.060 Nom. 0.020 Min. 0.015 R Typ. 0.035 Min. 0.015 R Typ.0.035 Typ. Detail “A” 0.560" Typical 0.050" Typical 0.050" Typical FOOTPRINT 0.030" Typical

32 Places

0.165 Typ. NOTES:

X28C010, X28HT010 FN8105 Rev 1.00 Page 20 of 20 February 12, 2007 Packaging Information

36 Lead Ceramic Pin Grid Array Package

Typ. 0.100 (2.54) All Leads Pin 1 Index NOTE: Leads 5, 14, 23, & 32 12 1 1 25 26 6 31 Typ. 0.180 (.010) (4.57 ± .25)

4 Corners

0.770 (19.56) 0.750 (19.05) SQ A A 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Typ. 0.180 (.010) (4.57 ± .25) 0.050 (1.27) 0.008 (0.20) A A Package Code G36.760x760A