X28C010FI-15

X28C010 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Access time: 120ns
• Simple byte and page write - Single 5V supply - No external high voltages or V PP control circuits - Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS - Active: 50mA - Standby: 500µA
• Software data protection - Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write ™ cell - Endurance: 100,000 write cycles - Data retention: 100 years
• Early end of write detection -D A T A polling - Toggle bit polling Pinouts 23 243 3 1NC A16 A15 A12 I/O0 I/O1 I/O2 VSS VCC WE NC A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 X28C010 CERDIP Flat Pack SOIC (R) PGA X28C010 (Bottom View) I/O1 VSS I/O0 17 I/O2 19 I/O3 A15 NC VCC I/O4 I/O5 NC I/O7 A10 A11 I/O6 NC CE OE A 9 A 13 A16 NC NC WE NC A 14 A12 X28C010 (Top View) I/O0 A13A8 A11 A10 I/O7 A14 I/O 1 I/O 2 V SS I/O 3 I/O 4 I/O 5 I/O 6 A 12 A 15 A 16 NC V CC WE NC 6 1 13 15 1716 18 1920 OE CE 14 21 X28C010 (Top View) I/O0 A13 A11 A10 I/O7 A14 I/O I/O VSS I/O I/O I/O I/O6 A 12 A 15 A 16 NC V CC WE NC OE CE PLCC LCC EXTENDED LCC 23 243 3 1 15 1716 18 1920 X28C010 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A11 A13 A14 NC NC NC WE VCC NC NC NC A16 A15 A12 TSOP

20 A321A4

Data Sheet May 11, 2005

2 FN8105.0 May 11, 2005

Ordering Information

RANGE (°C) X28C010D - 32-Ld Cerdip 0 to 70 X28C010D-12 120ns 32-Ld Cerdip 0 to 70 X28C010D-15 150ns 32-Ld Cerdip 0 to 70 X28C010DI - 32-Ld Cerdip -40 to +85 X28C010DI-12 120ns 32-Ld Cerdip -40 to +85 X28C010DI-15 150ns 32-Ld Cerdip -40 to +85 X28C010DI- 15C7681 150ns 32-Ld Cerdip -40 to +85 X28C010DM - 32-Ld Cerdip -55 to +125 X28C010DM-12 120ns 32-Ld Cerdip -55 to +125 X28C010DMB-12 120ns 32-Ld Cerdip MIL-STD-883 X28C010DMB- 12C7309 120ns 32-Ld Cerdip MIL-STD-883 X28C010DMB- 12C7729 120ns 32-Ld Cerdip MIL-STD-883 X28C010DMB-15 150ns 32-Ld Cerdip MIL-STD-883 X28C010DMB- 15C7762 150ns 32-Ld Cerdip MIL-STD-883 X28C010DMB-20 200ns 32-Ld Cerdip MIL-STD-883 X28C010DMC7237 - 32-Ld Cerdip X28C010FI-12 120ns 32-Ld Flat Pack -40 to +85 X28C010FI-15 150ns 32-Ld Flat Pack -40 to +85 X28C010FI- 15C1009 150ns 32-Ld Flat Pack -40 to +85 X28C010FI-20 200ns 32-Ld Flat Pack -40 to +85 X28C010FI-25 250ns 32-Ld Flat Pack -40 to +85 X28C010FM - 32-Ld Flat Pack -55 to +125 X28C010FM-12 120ns 32-Ld Flat Pack -55 to +125 X28C010FMB-15 150ns 32-Ld Flat Pack MIL-STD-883 X28C010FMB- 15C7619 150ns 32-Ld Flat Pack MIL-STD-883 X28C010FMB- 15C7808 150ns 32-Ld Flat Pack MIL-STD-883 X28C010K-25 250ns 36-Ld Pin Grid Array 0 to 70 X28C010KM-12 120ns 36-Ld Pin Grid Array -55 to +125 X28C010KM-25 250ns 36-Ld Pin Grid Array -55 to +125 X28C010KM- 25C7237 250ns 36-Ld Pin Grid Array -55 to +125 X28C010KMB-15 150ns 36-Ld Pin Grid Array MIL-STD-883 X28C010NM-12 120ns 32-Ld Extended LCC -55 to +125 X28C010NM-15 150ns 32-Ld Extended LCC -55 to +125 X28C010NMB-12 120ns 32-Ld Extended LCC MIL-STD-883 X28C010NMB-15 150ns 32-Ld Extended LCC MIL-STD-883 X28C010NMB- 15C7309 150ns 32-Ld Extended LCC MIL-STD-883 X28C010RI-12 120ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RI-20 200ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RI- 20C7168 200ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RI- 20C7975 200ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RI-20T1 200ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RI- 20T1C7168 200ns 32-Ld Ceramic SOIC (Gull Wing) -40 to +85 X28C010RM-15 150ns 32-Ld Ceramic SOIC (Gull Wing) -55 to +125 X28C010RMB-25 250ns 32-Ld Ceramic SOIC (Gull Wing) MIL-STD-883 Ordering Information (Continued) PART NUMBER ACCESS TIME PACKAGE TEMP RANGE (°C) X28C010

3 FN8105.0 May 11, 2005 Block Diagram Pin Descriptions Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C010. Device Operation Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. X Buffers Latches and Decoder I/O Buffers and Latches Y Buffers Decoder Control Logic and Timing 1Mbit EEPROM Array I/O0-I/O7 Data Inputs/Outputs CE OE VCC VSS WE A0-A7 Latches and A8-A16 Pin Names SYMBOL DESCRIPTION A0-A16 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect X28C010

will be in standard operating mode. will cause transient current spikes. inductive effects of the PC board traces. FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE

9 FN8105.0 May 11, 2005 Active Supply Current vs. Ambient Temperature Standby Supply Current vs. Ambient Temperature ICC (RD) by Temperature Over Frequency -55 -10 +125 Ambient Temperature (°C) ICC WR (mA) +35 +80 VCC = 5V -55 -10 +125 0.15 0.2 0.25 0.3 Ambient Temperature (°C) ISB (mA) 0.05 +35 +80 VCC = 5V 0.1 03 1 5 5.0 V CC Frequency (MHz) ICC RD (mA) -55°C +25°C +125°C X28C010

10 FN8105.0 May 11, 2005 Absolute Maximum Ratings Recommended Operating Conditions Temperature under bias Voltage on any pin with respect to V Lead temperature the device at these or any other conditions (above those indicate d in the operational sections of this specification) is not im plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ICC VCC Current (Active) (TTL Inputs) CE = OE = VIL, WE = VIH, All I/O’s = Open, Address Inputs = 0.4V/2.4V Levels @ f = 5MHz 50 mA ISB1 VCC Current (Standby) (TTL Inputs) CE = VIH, OE = VIL, All I/O’s = Open, Other Inputs = VIH 3m A ISB2 VCC Current (Standby) (CMOS Inputs) CE = VCC - 0.3V, OE = VIL, All I/O’s = Open, Other Inputs = VCC 500 µA ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC, CE = VIH 10 µA VlL (Note 1) Input LOW Voltage -1 0.8 V VIH (Note 1) Input HIGH Voltage 2V CC + 1 V VOL Output LOW Voltage I OL = 2.1mA 0.4 V VOH Output HIGH Voltage I OH = -400µA 2.4 V NOTE: 1. V IL min. and VIH max. are for reference only and are not tested. Power-Up Timing SYMBOL PARAMETER MAX UNIT tPUR (Note 2) Power-up to Read operation 100 µs tPUW (Note 2) Power-up to Write operation 5 ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL PARAMETER TEST CONDITIONS MAX UNIT CI/O (Note 2) Input/Output capacitance V I/O = 0V 10 pF CIN (Note 2) Input capacitance V IN = 0V 10 pF NOTE: 2. This parameter is periodically sampled and not 100% tested. Endurance and Data Retention PARAMETER MIN MAX UNIT Endurance 10,000 Cycles per byte Endurance 100,000 Cycles per page Data Retention 100 Years X28C010

11 FN8105.0 May 11, 2005 Equivalent A.C. Load Circuit Symbol TableA.C. Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V Mode Selection CE OE WE MODE I/O POWER LLH R e a d D OUT Active LHL W r i t e D IN Active H X X Standby and Write Inhibit High Z Standby X L X Write Inhibit — — X X H Write Inhibit — — 1.92kΩ 100pF Output 1.37kΩ WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance SYMBOL PARAMETER X28C010-12 X28C010-15 X28C010-20 X28C010-25 UNITMIN MAX MIN MAX MIN MAX MIN MAX READ CYCLE LIMITS tRC Read cycle time 120 150 200 250 ns tCE Chip enable access time 120 150 200 250 ns tAA Address access time 120 150 200 250 ns tOE Output enable access time 50 50 50 50 ns tLZ (Note 3) CE L O W t o a c t i v e o u t p u t 0000 n s tOLZ (Note 3) OE L O W t o a c t i v e o u t p u t 0000 n s tHZ (Note 3) CE HIGH to high Z output 50 50 50 50 ns tOHZ (Note 3) OE HIGH to high Z output 50 50 50 50 ns tOH Output hold from address change 0000 n s X28C010

12 FN8105.0 May 11, 2005 Read Cycle NOTE: when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. tCE tRC Address CE OE WE Data Valid tOE tLZ tOLZ tOH tAA tHZ tOHZ Data I/O VIH HIGH Z Data Valid Write Cycle Limits SYMBOL PARAMETER MIN MAX UNIT tWC (Note 4) Write cycle time 10 ms tAS Address setup time 0 ns tAH Address hold time 50 ns tCS Write setup time 0 ns tCH Write hold time 0 ns tCW CE pulse width 100 ns tOES OE HIGH setup time 10 ns tOEH OE HIGH hold time 10 ns tWP WE pulse width 100 ns tWPH WE HIGH recovery 100 ns tDV Data valid 1µ s tDS Data setup 50 ns tDH Data hold 0 ns tDW Delay to next write 10 µs tBLC Byte load cycle 0.2 100 µs X28C010

13 FN8105.0 May 11, 2005 WE Controlled Write Cycle NOTE: 4. t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete internal write operation. CE Controlled Write Cycle Address tAS tWC tAH tOES tDV tDS tDH tOEH CE WE OE Data In Data Out HIGH Z Data Valid tCS tCH tWP tWPH Address tAS tOEH tWC tAH tOES tWPH tCS tDV tDS tDH tCH CE WE OE Data In Data Out HIGH Z Data Valid tCW X28C010

14 FN8105.0 May 11, 2005 Page Write Cycle NOTES: 5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 6. The timings shown above are unique to page write operations. Indi vidual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. DATA Polling Timing Diagram (Note 7) WE OE (Note 5) Last Byte Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2 tWP tWPH tBLC tWC CE Address* (Note 6) I/O *For each successive write within the page write operation, A8-A16 should be the same or writes to an unknown address could occur. Address An DIN = X tWC tOEH tOES An An CE WE OE I/O7 tDW DOUT = X D OUT = X X28C010

15 FN8105.0 May 11, 2005 Toggle Bit Timing Diagram NOTE: 7. Polling operations are by definit ion read cycles and are therefore subject to read cycle timings. CE OE WE I/O6 tOES tDW tWC tOEH HIGH Z * I/O6 beginning and ending state will vary. X28C010

16 FN8105.0 May 11, 2005 Packaging Information 0.620 (15.75) 0.590 (14.99) Typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) Typ. 0.100 (2.54) 1.690 (42.95) Max. 0.023 (0.58) 0.014 (0.36) Typ. 0.018 (0.46) 0.232 (5.90) Max. 0.060 (1.52) 0.015 (0.38) Pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.033 (0.84) Typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) Max. 15° 32-Lead Hermetic, CerDIP, Package Code D32 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.005 (0.13) Min. 0.150 (3.81) Min. 0.015 (0.38) 0.008 (0.20) Seating Plane X28C010

17 FN8105.0 May 11, 2005 Packaging Information 0.150 (3.81) BSC 0.458 (11.63) 0.458 (11.63) 0.442 (11.22) Pin 1 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP . (4) PLCS. Typ. (3) Plcs.0.050 (1.27) BSC 0.028 (0.71) 0.022 (0.56) (32) Plcs. 0.200 (5.08) BSC 0.558 (14.17) 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) Pin 1 Index Corner 32-Pad Ceramic Leadless Chip Carrier Package Type E NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NLT ±0.005 (0.127) 0.300 (7.62) BSC 0.015 (0.38) Min. 0.400 (10.16) BSC 0.560 (14.22) 0.540 (13.71) DIA. 0.015 (0.38) 0.003 (0.08) X28C010

18 FN8105.0 May 11, 2005 Packaging Information 32-Lead Ceramic Flat Pack Type F NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) Max. Pin 1 Index 13 2 0.120 (3.05) 0.090 (2.29) Min. 0.026 (0.66) 0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.830 (21.08) Max. 0.050 (1.27) BSC 0.440 0.430 (10.93) 0.347 (8.82) 0.330 (8.38) 0.005 (0.13) Min. 0.030 (0.76) Min. 1.228 (31.19) 1.000 (25.40) X28C010

19 FN8105.0 May 11, 2005 Packaging Information 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) Typ. 0.300 (7.62) Ref. 0.453 (11.51) 0.447 (11.35) Typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) Typ. 0.490 (12.45) Pin 1 0.400 (10.16)Ref. 0.553 (14.05) 0.547 (13.89) Typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) Typ. 0.590 (14.99) 3° Typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) Typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) Seating Plane ±0.004 Lead CO - Planarity 32-Lead Plastic Leaded Chip Carrier Package Type J NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 0.510" Typical 0.050" Typical 0.050" Typical 0.300" Ref. FOOTPRINT 0.400" 0.410" 0.030" Typical

32 Places

20 FN8105.0 May 11, 2005 Packaging Information

0.300 BSC

0.458 Max. 0.450 ± 0.008 Pin 1 0.035 x 45° Ref. 0.085 ± 0.010 Typ. (3) Plcs.0.050 BSC

0.400 BSC

0.708 Max. 0.060/0.120 Pin #1 Index Corner 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NLT±0.005 (0.127) 0.700 ± 0.010 0.005/0.015 0.025 ± 0.003 0.050 ± 0.005 0.006/0.022Detail A Detail A 32-Pad Stretched Ceramic Leadless Chip Carrier Package Type N NOTES: X28C010

21 FN8105.0 May 11, 2005 Packaging Information 32-Lead Ceramic Small Outline Gull Wing Package Type R 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 0.340 ±0.007 See Detail “A” For Lead Information 0.440 Max. 0.560 Nom. 0.019 0.015 0.050 0.750 ±0.005 0.830 Max. 0.060 Nom. 0.020 Min. 0.015 R Typ. 0.035 Min. 0.015 R Typ.0.035 Typ. Detail “A” 0.560" Typical 0.050" Typical 0.050" Typical FOOTPRINT 0.030" Typical 0.165 Typ. NOTES: X28C010

22 FN8105.0 May 11, 2005 Packaging Information 36-Lead Ceramic Pin Grid Array Package Type K 15 17 19 21 22 14 16 18 20 23 10 9 27 28 8 7 29 30 5 2 36 34 32 4 3 1 35 33 Typ. 0.100 (2.54) All Leads Pin 1 Index NOTE: Leads 5, 14, 23, & 32 12 1 1 25 26 6 31 Typ. 0.180 (.010) (4.57 ± .25)

4 Corners

0.770 (19.56) 0.750 (19.05) SQ A A 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Typ. 0.180 (.010) (4.57 ± .25) 0.050 (1.27) 0.008 (0.20) A A X28C010

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8105.0 May 11, 2005 Packaging Information NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 0.50 ± 0.04 (0.0197 ± 0.0016) 0.30 ± 0.05 (0.012 ± 0.002) 14.80 ± 0.05 (0.583 ± 0.002) 1.30 ± 0.05 (0.051 ± 0.002) 0.17 (0.007) 0.03 (0.001) Typical 40 Places 15 Eq. Spc.@ 0.50 ± 0.04 0.0197 0.016 = 9.50 ± 0.06 (0.374 ± 0.0024) Overall Tol. Non-Cumulative Solder FOOTPRINT 0.396 (10.058) 0.392 (9.957) 0.493 (12.522) 0.483 (12.268) Pin #1 Ident O 0.040 (1.016) O 0.030 (0.762) (0.038) 0.045 (1.143) 0.035 (0.889) 0.0025 (0.065) 0.557 (14.148) 0.547 (13.894) Seating Plane A 0.007 (0.178) 0.040 (1.016) 15° Typ. 0.0197 (0.500) 0.048 (1.219) 0.010 (0.254) 0.006 (0.152) 0.017 (0.432) 0.032 (0.813) Typ. 0.017 (0.432) 0.020 (0.508) Typ. 0.006 (0.152) Detail A 40-Lead Thin Small Outline Package (TSOP) Type T 0.965 X0.005 (0.127) Dp. 0.003 (0.076) Dp. Plane Seating Typ.4° Typ. Pads X28C010