X2816C XICOR | Alldatasheet
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Technical content
©Xicor, 1995 Patents Pending Characteristics subject to change without notice 3852-1.4 3/27/96 T2/C3/D5 NS
5 Volt, Byte Alterable E2PROM
FEATURES
- 90ns Access Time
- Simple Byte and Page Write —Single 5V Supply —No External High Voltages or VPP Control Circuits —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem
- High Performance Advanced NMOS Technology
- Fast Write Cycle Times —16 Byte Page Write Operation —Byte or Page Write Cycle: 5ms Typical —Complete Memory Rewrite: 640ms Typical —Effective Byte Write Cycle Time: 300 µs Typical
- DATA Polling —Allows User to Minimize Write Cycle Time
- JEDEC Approved Byte-Wide Pinout
- High Reliability —Endurance: 10,000 Cycles —Data Retention: 100 Years
DESCRIPTION
The Xicor X2816C is a 2K x 8 E 2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor Programmable nonvola- tile memories it is a 5V only device. The X2816C features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs. The X2816C supports a 16-byte page write operation, typically providing a 300µs/byte write cycle, enabling the entire memory to be written in less than 640ms. The X2816C also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. Xicor E 2PROMs are designed and tested for applica- tions requiring extended endurance. Inherent data re- tention is greater than 100 years. 16K X2816C 2048 x 8 Bit PIN CONFIGURATION 3852 FHD F02.1 I/O0 I/O1 I/O2 VSS VCC WE OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3 X2816C PLASTIC DIP SOIC
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Addresses (A0–A 10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power con- sumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. X BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHESY BUFFERS LATCHES AND DECODER CONTROL LOGIC 16,384-BIT E2PROM ARRAY I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE VCC VSS A0–A10 ADDRESS INPUTS WE
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A0–A10 Address Inputs I/O0–I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect
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byte load cycle, started by the WE HIGH to LOW transition, must begin within 20µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20µs, the internal auto- matic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20µs. DATA Polling The X2816C features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2816C, eliminating additional interrupt inputs or external hard- ware. During the internal programming cycle, any at- tempt to read the last byte written will produce the complement of that data on I/O 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O 7 will reflect true data. WRITE PROTECTION There are three features that protect the nonvolatile data from inadvertent writes.
- Noise Protection—A WE pulse which is typically less than 10ns will not initiate a write cycle.
- V CC Sense—All functions are inhibited when VCC is ≤3V, typically.
- Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH during power-up and power-down, will inhibit inadvertent writes. Write cycle timing specifi- cations must be observed concurrently. ENDURANCE Xicor E 2PROMs are designed and tested for applica- tions requiring extended endurance. DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW and WE HIGH. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system envi- ronment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2816C supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X2816C allows the entire memory to be typically written in 640ms. Page write allows two to sixteen bytes of data to be consecutively written to the X2816C prior to the commencement of the internal programming cycle. Although the host system may read data from any other device in the system to transfer to the X2816C, the destination page address of the X2816C should be the same on each subsequent strobe of the WE and CE inputs. That is, A 4 through A10 must be the same for each transfer of data to the X2816C during a page write cycle. The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive
prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high fre- quency ceramic capacitor be used between V CC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. SYSTEM CONSIDERATIONS Because the X2816C is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and elimi- nate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the X2816C has two power modes, standby and active, proper decoupling of the memory array is of
*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Temperature under Bias Voltage on any Pin with Respect to V RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C 3852 PGM T02.2 Supply Voltage Limits X2816C 5V ±10% 3852 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. (1) Max. Units Test Conditions ICC VCC Current (Active) 70 110 mA CE = OE = VIL All I/O’s = Open Other Inputs = VCC ISB1 VCC Current (Standby) 35 50 mA CE = VIH, OE = VIL All I/O’s = Open Other Inputs = VCC ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC , CE = VIH VlL(2) Input LOW Voltage –1 0.8 V VIH(2) Input HIGH Voltage 2 V CC +1 V VOL Output LOW Voltage 0.4 V I OL = 2.1mA VOH Output HIGH Voltage 2.4 V I OH = –400µA 3852 PGM T02.2 Notes: (1) Typical values are for TA = 25°C and nominal supply voltage and are not tested. (2) VIL min. and VIH max. are for reference only and are not tested.
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Test Max. Units Conditions C I/O(3) Input/Output Capacitance 10 pF V I/O = 0V C IN(3) Input Capacitance 6 pF V IN = 0V 3852 PGM T05.1 POWER-UP TIMING Symbol Parameter Typ. (1) Units tPUR (3) Power-Up to Read Operation 1 ms tPUW (3) Power-Up to Write Operation 5 ms
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H X X Standby and Write Inhibit High Z Standby X L X Write Inhibit — — X X H Write Inhibit — —
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A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V 3852 PGM T06.1 ENDURANCE AND DATA RETENTION Parameter Min. Max. Unit Minimum Endurance 10,000 Cycles/Byte Data Retention 100 Years
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Note: (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUITS 6612 FHD F22.3 1.92KΩ 100pF OUTPUT 1.37KΩ
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Read Cycle Limits X2816C-90 X2816C-12 X2816C-15 X2816C-20 tRC Read Cycle Time 90 120 150 200 ns tCE Chip Enable Access Time 90 120 150 200 ns tAA Address Access Time 90 120 150 200 ns tOE Output Enable Access Time 60 60 80 100 ns tLZ(4) CE LOW to Active Output 0 0 0 0 ns tOLZ (4) OE LOW to Active Output 0 0 0 0 ns tHZ (4) CE HIGH to High Z Output 50 60 60 60 ns tOHZ (4) OE HIGH to High Z Output 50 60 60 60 ns tOH Output Hold from 0 0 0 0 ns Address Change 3852 PGM T10.1
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Notes: (4) tLZ min., tHZ , tOLZ , and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Symbol Parameter Min. Max. Min. Max. Units tWC (5) Write Cycle Time 10 10 ms tAS Address Setup Time 5 5 ns tAH Address Hold Time 80 100 ns tCS Write Setup Time 0 0 ns tCH Write Hold Time 0 0 ns tCW CE Pulse Width 80 100 ns tOES OE HIGH Setup Time 10 10 ns tOEH OE HIGH Hold Time 5 10 ns tWP WE Pulse Width 80 100 ns tWPH WE HIGH Recovery 50 50 ns tDV Data Valid 100 100 µs tDS Data Setup 35 50 ns tDH Data Hold 5 10 ns tDW Delay to Next Write 10 10 µs tBLC Byte Load Cycle 1 100 1 100 µs 3852 PGM T09.1 WE Controlled Write Cycle
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Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. ADDRESS tAS tWC tAH tOES tDV tDS tDH tOEH CE WE OE DATA IN DATA OUT HIGH Z DATA VALID tCS tCH tWP X2816C-90 X2816C-12,-15,-20
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Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. ADDRESS tAS tOEH tWC tAH tOES tCS tDV tDS tDH tCH CE WE OE DATA IN DATA OUT HIGH Z DATA VALID tCW WE OE (6) LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 tWP tWPH tBLC tWC CE ADDR. * (7) I/O *For each successive write within the page write operation, A4–A10 should be the same or writes to an unknown address could occur.
DATA Polling Timing Diagram(10) Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings. SYMBOL TABLE
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D IN=X D OUT =X D OUT =X tWC tOEH tOES An An CE WE OE I/O7 tDW WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance
Normalized Active Supply Current vs. Ambient Temperature Normalized Standby Supply Current vs. Ambient Temperature 3852 FHD F09.1 3852 FHD F10.1 Normalized Access Time vs. Ambient Temperature 3852 FHD F11.1 –55 +25 +125 0.6 0.8 1.0 1.2 1.4 VCC = 5V AMBIENT TEMPERATURE ( °C) NORMALIZED I CC –55 +25 +125 0.6 0.8 1.0 1.2 1.4 VCC = 5V AMBIENT TEMPERATURE ( °C) NORMALIZED I SB –55 +25 +125 0.6 0.8 1.0 1.2 1.4 VCC = 5V AMBIENT TEMPERATURE ( °C) NORMALIZED T AA
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NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. P ACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) REF. PIN 1 INDEX 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.065 (1.65) 15° 24-LEAD PLASTIC DUAL IN-LINE P ACKAGE TYPE P TYP. 0.010 (0.25)
0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) TYP. 0.300 (7.62) REF. 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) PIN 1 0.400 (10.16)REF. 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 3° TYP. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) SEATING PLANE ±0.004 LEAD CO – PLANARITY
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32-LEAD PLASTIC LEADED CHIP CARRIER P ACKAGE TYPE J NOTES: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONL Y 0.510" TYPICAL 0.050" TYPICAL 0.050" TYPICAL 0.300" REF FOOTPRINT 0.400" 0.410" 0.030" TYPICAL
32 PLACES
0.150 (3.81) BSC 0.458 (11.63) 0.458 (11.63) 0.442 (11.22) PIN 1
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0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. TYP. (3) PLCS.0.050 (1.27) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.200 (5.08) BSC 0.558 (14.17) 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) PIN 1 INDEX CORNER 32-P AD CERAMIC LEADLESS CHIP CARRIER P ACKAGE TYPE E NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NL T ±0.005 (0.127) 0.300 (7.62) BSC 0.015 (0.38) MIN. 0.400 (10.16) BSC 0.560 (14.22) 0.540 (13.71) DIA. 0.015 (0.38) 0.003 (0.08)
0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° – 8° X 45°
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24-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.420" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL
24 PLACESFOOTPRINT
ORDERING INFORMATION
–90 = 90ns –12 = 120ns –15 = 150ns –20 = 200ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package P = 24-Lead Plastic DIP J = 32-Lead PLCC E = 32-Pad LCC S = 24-Lead Plastic SOIC X2816C X X -X