X2816AM

X2816AM XICOR | Alldatasheet

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16K Military X2816AM 2048 x 8 Bit ee Electrically Erasable PROM FEATURES DESCRIPTION Simple Byte Write Operation The Xicor X2816A is a 2K x 8 E2PROM, fabricated with —wNo High Voltages Necessary the same reliable N-channel floating gate MOS tech- —Single TTL Level WE Signal Modifies Data nology used in all Xicor 5V programmable nonvolatile —internally Latched Address and Data memories. The X2816A features the JEDEC approved —Self Timed Write pinout for byte-wide memories, compatible with industry —Noise Protected WE Pin standard RAMs, ROMs, and EPROMs. Reliable N-Channel Floating Gate MOS Xicor E2PROMs are designed and tested for applica- Technology tions requiring extended endurance. Refer to Device © Single 5V Supply Operation for further endurance information. Data re- © Byte Write Time: 10 ms Max. tention is specified to be greater than 100 years. © Fast Access Time: 300 ns Max. © Low Power Dissipation —Active Current: 140 mA Max. —Standby Current: 60 mA Max. JEDEC Approved Byte-Wide Pinout ir a PIN CONFIGURATIONS FUNCTIONAL DIAGRAM We nme Ee aq> 2Be ae " x ade spw 6: ae purrens qs spo aes ne ad? aba :e oe ae “pe fem oho 2q= “Be “ypanpag™ nes wn «Bw, Ter Hoy we »Be. “poss-10 - BUFFERS -_ a ten PIN NAMES Ao-Aio _ Address Inputs | | | | \\/Op-I/07 Data Input/Output « We Write Enable = Conrmot YY CE Chip Enable we W/Op-1/07 OE Output Enable DATA INPUTS/OUTPUTS Voc +5V Vee O—> Vss Ground Ves O—> NC No Connect 055-3 oe ——— —

3.27 May 1987

ABSOLUTE MAXIMUM RATINGS* *COMMENT Voltage on ory, Pin with ‘stress rating only and the functional operation of the device at Lead Temperature to absolute maximum rating conditions for extended periods (Soldering, 10 Seconds) . cessceseseseeseesss, 300°C may atfect device reliability. D.C. OPERATING CHARACTERISTICS Ta = —B5°C to + 125°C, Voc = +5V +10%, unless otherwise specified. Voc Current (Active) mA CE= OE =v All /0's = Open Other Inputs = Voc Voc Current (Standby) mA CE = Vin, OF = Vit AllI/O's = Open Other Inputs = Voc. Tal Laatge Canes | [gin = GN oc ieuttow eta | =1@ [Jv CAPACITANCE Ta = 25°C, f = 1.0 MHz, Voc = 5V [_symbot [test Max, [Units [Conditions rut Canactance a A.C. CONDITIONS OF TEST MODE SELECTION (ee| oe | We] wow [ v0 | Power] poe fw |e | wets | ow | Active | Input and Output Timing Levels 1.6¥ x x Standby and Standby TTiLGawand Write Inhibit ate an Ouputoad [c= toopr | [| x | & | x | wrtonnibt | — | — | Note: (1) This parameter is periodically sampled and not 100% tested. 3-28 Cc a a

a A.C. CHARACTERISTICS Ta = —55°C to + 125°C, Voc = +5V +10%, unless otherwise specified. Read Cycle Limits [_szsen_[ zs [ szaants | une | [srmot | pean gen | [ice | Ghiptnableaccesstime |__| soo | | a0 | | 450 | ns | Cia | Assess AccessTine || s00 | | a0 | | 50 [me | [toe | Output EnabieAccesstime |__| 120 | | 195 | | 150 | ns | [ir | crpenedietw ouputiniowe | 0 | [| |] | m | i} tai [Cup Dsediete Oupuinrign2 [10 | vee | vo | veo | wo | vo | re | [ier | OuputenabietoOuputntowz | so [| | | | | vw | [enc | Output see toOuputinvigh2 | 10 | 00 | vo | veo | vo | 150 | me | ton | Output Holatrom Address Change | 20] | 20 | | 2 | | ns | Read Cycle ADDRESS CC KD “toe: cE ee ee ee | we e—tiz- tone pataivo SE KOK DATA VALID OK KX KOK _daravatio > os Note: (2) tz and toyz are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. a 3-29

[mee [eo eee eee oe [mc | wWiwcetme wo | Pw [| | me | [tau | AddressHoldtime «| -t50 | | _tso | | t50 | | ons | tou | WriteHoidTime | co | | co | | | os | | tow | ChipEnabletoEndof Write input | 150 | | 175 | | 290 | | ons | [ces | OuputenabictoisTime | 0 [| | || | m | [we | WrtePuisewith | -t50 | | ts | | 290 | | ns | Fev | ostavaistie || + | P| a [ios | Oaaseuptine [we | pve || mo | [ms | WE Controlled Write Cycle ; ADDRESS CO KKK KKK KKK KKK ae 77 VANANAN we -—_ TSN] Se eee DATA WH KRKKK Kear KKH EKKO para our XOX wovz a i — ——

ze {SAY a <1 eter. DATAIN oa KXXXX/[XXXXK oe ws ce . 3-31

PIN DESCRIPTIONS A byte write operation, once initiated, will automatically itinue to completion, typically within 5 ms. In order Addresses (Ag-A1o) cont c The Address inputs select an 8-bit memory location _'0 take advantage of the typical write time as opposed during a read or write operation. to the maximum specified time, the user can poll the X2816A. The 1/0 pins are placed in the high imped- Chip Enable (CE) ance state during the internal programming cycle. Once The Chip Enable input must be LOW to enable all __the internal cycle is complete, the X2816A may be ac- read/write operations. When CE is HIGH, power con- _cessed without any limitations. Therefore, the host can sumption is reduced. poll an address with known data (preferably with ze- foes), as soon as a compare is true, the X2816A is Output Enable (OE) ready for another wite cycle. The Output Enable input controls the data output buff- ers and is used to initiate read operations. WRITE PROTECTION Data In/Data Out (I/O-/07) there a ee features that protect the nonvolatile Data is written to or read from the X2816A through the _-4#@ from inadvertent writes. 1/0 pins. * Noise Protection—A WE pulse of less than 20 ns will Write Enable (WE) Not initiate a write cycle. The Write Enable input controls the writing of data to Voc, Sense—Alll functions are inhibited when Vcc is the X2816A. <3V, typically. DEVICE OPERATION © Write Inhibit—Holding either OE LOW, WE HIGH or Read _ CE HIGH during power-on and power-off, will inhibit Read operations are initiated by both OE and CE LOW. inadvertent writes. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture elimi. ENDURANCE ; nates bus contention in a system environment. The Xicor E2PROMSs are designed and tested for applica- data bus will be in a high impedance state when either _tions requiring extended endurance. The process aver- GE or CE is HIGH. age for endurance of Xicor E2PROMS is approximately Ya million cycles, as documented in R504, the Xicor Write . a Reliability Report on Endurance. Included in that report Write operations are initiated when both CE and WE _is a method for determining the expected endurance of are LOW and OE is HIGH. The X2816A supports both the device based upon the specific application environ- a CE and WE controlled write cycle. That is, the ad- — ment. RR504 and additional reliability reports are avail- dress is latched by the falling edge of either CE or WE, —_able from Xicor. whichever occurs last. Similarly, the data is latched in- ternally by the rising edge of either CE or WE, whichev- er occurs first. 3-32

——_— SYSTEM CONSIDERATIONS ; of prime concern. Enabling CE will cause transient cur- Because the X2816A is frequently used in large memo- rent spikes. The magnitude of these spikes is depen- ry arrays it is provided with a two line control architec- dent on the output capacitive loading of the I/Os. ture for both read and write operations. Proper usage Therefore, the larger the array sharing a common bus, can provide the lowest possible power dissipation and the larger the transient spikes. The voltage peaks as- eliminate the possibilty of contention where multiple sociated with the current transients can be suppressed 1/O pins share the same bus. by the proper selection and placement of decoupling To gain the most benefit it is recommended that CE be capacitors. As a minimum, it is ea be decoded from the address bus and be used as the pri. O.! HF high reaver corame Gaparioy te Ca mary device selection input. Both OE and WE would tween Vo and ° at sae the eapenttor ma on e then be common among all devices in the array. For a ed oI the array, the value of the capacitor may have read operation this assures that all deselected devices "0 Pe larger. are in their standby mode and that only the selected —_{n addition, it is recommended that a 4.7 yF electrolytic device(s) is outputting data on the bus. bulk capacitor be placed between Vcc and GND for tive, proper decoupling of the array is aan and active, pr lecoupling of the memory array IS used by the inductive effects of the PC board traces. SYMBOL TABLE WAVEFORM INPUTS OUTPUTS —— _ Must be Will be —__ steady steady May change Will change DD from Low to from Low to High High May change Will change ae from High to from High to Low Low Don't Care: Changing : XXXXX Changes State Not Allowed Known Center Line Impedance a 3-33

Normalized Active Supply Current Normalized Standby Supply Current vs. Ambient Temperature vs. Amblent Temperature 14) 1 - Veo =5.0¥ Veo = 5.0¥ 8 12 3 1.2 [ _ — q | 8 3 10 . 3 10 — 2 3 = 08 NI 08 — — “55 +25 125 “55 425 +125, AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) coss-7 ooss-8 Normalized Access Time vs. Ambient Temperature 1.6 + Voc=5.0V ei 13 S10 Fy = o7 “5s 425 +125, AMBIENT TEMPERATURE (°C) cnss-0 a 3-34