X25F064 XICOR | Alldatasheet
Document overview
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Technical content
SerialFlash™ and Block Lock™ Protection are trademarks of Xicor, Inc. SerialFlash™ Memory With Block LockTM Protection
FEATURES
- 1MHz Clock Rate
- SPI Serial Interface
- 64K/32K/16K/8K Bits —32 Byte Small Sector Program Mode
- Low Power CMOS —<1 µA Standby Current —<5mA Active Current
- 1.8V – 3.6V or 5V “Univolt” Read and Program Power Supply Versions
- Block Lock Protection —Protect 1/4, 1/2, or all of E2PROM Array
- Built-in Inadvertent Program Protection —Power-Up/Power-Down protection circuitry —Program Enable Latch —Program Protect Pin
- Self-Timed Program Cycle —5ms Program Cycle Time (Typical)
- High Reliability —Endurance: 100,000 cycles per byte —Data Retention: 100 Years —ESD protection: 2000V on all pins
- 8-Lead PDlP Package
- 8-Lead 150 mil SOIC Packages
- 32K, 16K, 8K available in 14-Lead TSSOP, 64K available in 20-Lead TSSOP
DESCRIPTION
The X25F064/032/016/008 family are 8/16/32/64K-bit CMOS SerialFlash memory, internally organized X 8. They feature a “Univolt” Program and Read voltage, Serial Peripheral Interface (SPI), and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK), plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25F064/032/016/008 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25F064/032/016/008 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The PP input can be used as a hardwire input to the X25F064/032/016/008 disabling all program attempts to the status register, thus providing a mechanism for limiting end user capa- bility of altering 0, 1/4, 1/2, or all of the memory. The X25F064/032/016/008 utilizes Xicor’s proprietary flash cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM © Xicor, Inc. 1995, 1996 Patents Pending Characteristics subject to change without notice 6685-3.1 8/29/96 T3/C0/D0 SH 6685 ILL F01.4 COMMAND DECODE AND CONTROL LOGIC X DECODE LOGIC MEMORY ARRAY SI SO CS HOLD STATUS REGISTER PROGRAMMING CONTROL LOGICPP HIGH VOLTAGE CONTROL SECTOR DECODE LOGIC 32 8 DATA REGISTER SCK A PPLICATION N OTE A V A I L A B L E AN61 • AN75 • AN77 • AN79 • AN82
Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN NAMES SYMBOL DESCRIPTION CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input PP Program Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input NC No Connect 6685 PGM T01.1 PIN DESCRIPTIONS Serial Output (SO) SO is a push-pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25F064/032/016/008 is deselected and the SO output pin is at high impedance and unless an internal program operation is underway the X25F064/032/016/008 will be in the standby power mode. CS LOW enables the X25F064/032/016/008, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Program Protect (PP) When PP is LOW and the nonvolatile bit PPEN is “1”, nonvolatile programming of the X25F064/032/016/008 status register is disabled, but the part otherwise func- tions normally. When PP is held HIGH, all functions, including nonvolatile programming operate normally. PP going LOW while CS is still LOW will interrupt programming of the X25F064/032/016/008 status regis- ter. If the internal program cycle has already been initiated, PP going LOW will have no effect on program- ming. The PP pin function is blocked when the PPEN bit in the status register is “0”. This allows the user to install the X25F064/032/016/008 into a system with PP pin grounded and still be able to program the status register. The PP pin functions will be enabled when the PPEN bit is set “0”. PIN CONFIGURATION 6685 ILL F02.4 CS SO PP VSS VCC HOLD SCK SI 8-Lead DIP/SOIC 14-Lead TSSOP 20-Lead TSSOP CS SO NC NC NC PP VSS VCC HOLD NC NC NC SCK SI NC CS NC SO NC NC PP VSS NC NC NC VCC NC HOLD NC NC SCK SI NC NC X25F064/ 032/016/ 008 X25F032/ X25F064
PPEN, BL0, and BL1 are set by the PRSR instruction. latch is set; when set to a “0” the latch is reset. allow the user to select one of four levels of protection. trolled as illustrated below. program or status register write cycle. Table 1. Instruction Set *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
PPEN PP PEL Blocks Blocks Register
0 X 0 Locked Locked Locked
0 X 1 Locked Programmable Programmable
1 LOW 0 Locked Locked Locked
1 LOW 1 Locked Programmable Locked
X HIGH 0 Locked Locked Locked X HIGH 1 Locked Programmable Programmable 6685 PGM T05.2 The Program Protect (PP) pin and the nonvolatile Program Protect Enable (PPEN) bit in the Status Reg- ister control the programmable hardware write protect feature. Hardware program protection is enabled when PP pin is LOW, and the PPEN bit is “1”. Hardware program protection is disabled when either the PP pin is HIGH or the PPEN bit is “0”. When the chip is hardware program protected, nonvolatile programming of the Sta- tus Register in disabled, including the Block Lock bits and the PPEN bit itself, as well as the Block Lock sections in the memory array. Only the sections of the memory array that are not Block Locked can be pro- grammed. Note: Since the PPEN bit is program protected, it cannot be changed back to a “0”, as long as the PP pin is held LOW. Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the SerialFlash memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25F064/032/016/008 device, followed by the 16-bit address. After the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached the address counter rolls over to address $0000, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the Read SerialFlash Memory Array Operation Sequence illustrated in Figure 1. To read the status register, the CS line is first pulled LOW to select the device followed by the 8-bit instruc- tion. After the read status register opcode is sent, the contents of the status register are shifted out on the SO line. The Read Status Register Sequence is illustrated in Figure 2. Programming Sequence Prior to any attempt to program the X25F064/032/016/ 008 device, the program enable latch must first be set by issuing the PREN instruction (See Figure 3). CS is first taken LOW, then the PREN instruction is clocked into the X25F064/032/016/008 device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the programming operation without taking CS HIGH after issuing the PREN instruc- tion, the programming operation will be ignored. To program the SerialFlash memory array, the user issues the PROGRAM instruction, followed by the ad- dress of the first location in the sector and then the data to be programmed. The data is programmed in a 256- clock operation. CS must go LOW and remain LOW for the duration of the operation. The 32 bytes must reside in the same sector and cannot cross sector boundaries. If the address counter reaches the end of the sector and the clock continues, or if fewer than 32 bytes are clocked in, the contents of the sector cannot be guaranteed. For the program operation to be completed, CS can only be brought HIGH after bit 0 of data byte 32 is clocked in. If it is brought HIGH at any other time the program operation will not be completed. Refer to Figure 4 below for a detailed illustration of the programming sequence and time frames in which CS going HIGH is valid. To program the status register, the PRSR instruction is followed by the data to be programmed. Data bits 0, 1, 4, 5 and 6 must be “0”. This sequence is shown in Figure 5. While the program cycle is in progress, following a status register or memory write sequence, the status register may be read to check the PIP bit. During this time the PIP bit will be HIGH. Hold Operation The HOLD input should be HIGH (at V IH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is that the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to V CC or tied to VCC through a resistor.
Figure 1. Read SerialFlash Memory Array Operation Sequence
- The device is in the low power standby state.
- A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
- SO pin is high impedance.
- The program enable latch is reset. Data Protection The following circuitry has been included to prevent inadvertent programming:
- The program enable latch is reset upon power-up.
- A program enable instruction must be issued to set the program enable latch.
- CS must come HIGH at the proper clock count in order to start a program cycle.
Figure 2. Read Status Register Operation Sequence
6685 ILL F03
6685 ILL F04
Figure 3. Program Enable Latch Sequence
Figure 5. Program Status Register Operation Sequence Figure 4. Programming Sequence
6685 ILL F08
*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Respect to V Lead Temperature D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC VCC Supply Current (Active) 5 mA SCK = V CC x 0.1/VCC x 0.9 @ 1MHz, SO = Open, CS = VSS ISB1 (2) VCC Supply Current (Standby) 1 µA CS = VCC , VIN = VSS or VCC , VCC = 3.6V ISB2 VCC Supply Current (Standby) 10 µA CS = VCC , VIN = VSS or VCC , VCC = 5V ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current –1 10 µAV OUT = VSS to VCC VIL(1) Input LOW Voltage V CC x 0.7 VCC x 0.3 V VIH(1) Input HIGH Voltage V CC + 0.5 V VOL1 Output LOW Voltage 0.4 V I OL = 1.5mA, VCC = 2.7V VOH1 Output HIGH Voltage V CC – 0.3 V I OH = –0.4mA, VCC = 2.7V VOL2 Output LOW Voltage 0.4 V I OL = 3mA, VCC = 5V VOH2 Output HIGH Voltage V CC – 0.8 V I OH = –1.6mA, VCC = 5V 6685 PGM T08.4 RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Extended –20 °C +85 °C Industrial –40 °C +85 °C 6685 PGM T06.2 Supply Voltage Limits X25F064/032/016/008 1.8V to 3.6V X25F064/032/016/008–5 4.5V to 5.5V 6685 PGM T07.3 POWER-UP TIMING Symbol Parameter Min. Max. Units tPUR (3) Power-up to Read Operation 1 ms tPUW (3) Power-up to Write Operation 5 ms
6685 PGM T09
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. CAPACITANCE TA = 25°C, f = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO) 8 pF V OUT = 0V C IN(2) Input Capacitance (SCK, SI, CS, WP, HOLD)6 p F V IN = 0V 6685 PGM T10.1
EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5
6685 PGM T11
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 1 MHz tCYC Cycle Time 1000 ns tLEAD CS Lead Time 500 ns tLAG CS Lag Time 500 ns tWH Clock HIGH Time 400 ns tWL Clock LOW Time 400 ns tSU Data Setup Time 100 ns tH Data Hold Time 100 ns tRI(4) Data In Rise Time 2 µs tFI(4) Data In Fall Time 2 µs tHD HOLD Setup Time 200 ns tCD HOLD Hold Time 200 ns tCS CS Deselect Time 2 µs tPC (5) Program Cycle Time 10 ms 6685 PGM T12.3 Data Output Timing Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 1 MHz tDIS Output Disable Time 500 ns tV Output Valid from Clock LOW 400 ns tHO Output Hold Time 0 ns tRO (4) Output Rise Time 300 ns tFO (4) Output Fall Time 300 ns tLZ(4) HOLD HIGH to Output in Low Z 100 ns tHZ (4) HOLD LOW to Output in High Z 100 ns 6685 PGM T13.2 Notes: (4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile program cycle. 6685 ILL F09.3 OUTPUT 1.44KΩ 1.95KΩ 100pF OUTPUT 2.7V 1.64KΩ 4.63KΩ 100pF
MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS
6685 ILL F10
6685 ILL F11
6685 ILL F12
3926 FHD F01
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL
8 PLACESFOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .193 (4.9) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)
3926 FHD F32
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .252 (6.4) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)
3926 FHD F45
ORDERING INFORMATION
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and backup features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Device X25FXXX P T –X VCC Range Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C E = Extended = –20°C to +85°C I = Industrial = –40°C to +85°C Package X25F064 X25F032 P = 8-Lead Plastic DIPX25F016 S = 8-Lead SOIC X25F008 V = 20-Lead TSSOP P = 8-Lead Plastic DIP S = 8-Lead SOIC V = 14-Lead TSSOP P = 8-Lead Plastic DIP Blank = 8-Lead SOIC V = 14/20-Lead TSSOP Blank = 1.8V to 3.6V, 0°C to +70°C 5 = 4.5V to 5.5V, 0°C to +70°C I5 = 4.5V to 5.5V, –40°C to +85°C X25FXXX X Part Mark Convention X25F064 X25F032 X25F016 X25F008