X25330S8

X25330 XICOR | Alldatasheet

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Technical content

Ó Xicor, Inc. 1994 - 1997 Patents Pending 1 Characteristics subject to change without notice 7048–1.0 6/18/97 T0/C0/D0 SH X25330

FEATURES

m A Standby Current <5mA Active Current 2.5V To 5.5V Power Supply SPI Modes (0,0 & 1,1) 4K X 8 Bits

32 Byte Page Mode

Block Lock™ Protection Protect 1/4, 1/2 or all of E PROM Array Programmable Hardware Write Protection In-Circuit Programmable ROM Mode Built-in Inadvertent Write Protection Power-Up/Down protection circuitry Write Enable Latch Write Protect Pin Self-Timed Write Cycle 5ms Write Cycle Time (Typical) High Reliability Endurance: 100,000 cycles Data Retention: 100 Years ESD protection: 2000V on all pins Packages 8-Lead SOIC 14-Lead TSSOP

DESCRIPTION

The X25330 is a CMOS 32K-bit serial E PROM, inter- nally organized as 4K x 8. The X25330 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS ) input, allowing any number of devices to share the same bus. The X25330 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25330 will ignore tran- sitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25330 disabling all write attempts to the status register, thus providing a mech- anism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25330 utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. COMMAND DECODE AND CONTROL LOGIC WRITE CONTROL AND TIMING LOGIC WRITE PROTECT LOGIC X DECODE LOGIC 4K BYTE ARRAY

32 X 256

64 X 256

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Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc. FUNCTIONAL DIAGRAM

Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS ) When CS is HIGH, the X25330 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25330 will be in the standby pow er mode. CS LO W enab les the X25330, placing it in the active pow er mode. It should be noted that after pow er-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP ) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25330 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25330 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25330 in a system with WP pin grounded and still be able to write to the status register. The WP pin func- tions will be enabled when the WPEN bit is set “1”. Hold (HOLD ) HOLD is used in conjunction with the CS pin to pause the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause

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0.197" Max 0.200" Max 0.252" 0.244" * Pin 2 and Pin 3 are internally connected. Only one CS needs to be connected externally. PIN NAMES

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V SS Ground V CC Supply Voltage HOLD Hold Input NC No Connect PIN CONFIGURATION

should be held HIGH at all times. face (SPI) of many popular microcontroller families. WP inputs must be HIGH during the entire operation. point when HOLD was first asserted.

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WPEN, BL0 and BL1 are set by the WRSR instruction. in progress. During a write, all other bits are set to “1”. is set, when set to a “0”, the latch is reset. allow the user to select one of four levels of protection. partitioning is controlled as illustrated below.

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Table 1. Instruction Set

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*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

The Wr ite-Protect-Enable (WPEN) bit is available for the X25330 as a nonvolatile enable bit for the WP pin.

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Programmable Hardware Write Protection The Wr ite Protect (WP ) pin and the nonvolatile Wr ite Protect Enable (WPEN) bit in the Status Register control the Programmab le Hardware Wr ite Protect feature. Hardware Wr ite Protection is enabled when WP pin is LOW , and the WPEN bit is “1”. Hardware Wr ite Protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hard- w are write protected, nonvolatile writes are disabled to the Status Register, including the Block Lock bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memor y array that are not block-protected can be written. In Circuit Programmable ROM Mode Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held LO W . Thus an In Circuit Programmab le ROM function can be emplemented by hardwiring the WP pin to Vss, writing to and Block Locking the desired portion of the array to be ROM, and then programming the WPEN bit HIGH. The table above defines the program protect status for each combination of WPEN and WP Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E PR OM memor y array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25330, follow ed by the 16-bit address of which the last 12 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 LOW 0 Protected Protected Protected

1 LOW 1 Protected Writable Protected

X HIGH 0 Protected Protected Protected X HIGH 1 Protected Writable Writable at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($0FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is termi- nated by taking CS HIGH. Refer to the read E PR OM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LO W to select the device follow ed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Figure 2 illustrates the read status register sequence. Write Sequence Prior to any attempt to write data into the X25330, the “Write Enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LO W , then the WREN instruction is clocked into the X25330. After all eight bits of the instruction are trans- mitted, CS m ust then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E PR OM memor y array, the user issues the WRITE instruction, follow ed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LO W for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25330. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustra- tion of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is follow ed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. Figure 6 illustrates this sequence. While the write is in progress following a status register or E PR OM wr ite sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH.

m ust also be LOW when HOLD is released.

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent in- advertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write enable” latch.
• CS must come HIGH at the proper clock count in or- der to start a write cycle.

Figure 1. Read E

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Figure 2. Read Status Register Operation Sequence

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Figure 3. Write Enable Latch Sequence Figure 4. Byte Write Operation Sequence

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Figure 6. Write Status Register Operation Sequence Figure 5. Page Write Operation Sequence

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ABSOLUTE MAXIMUM RATINGS* C to +135 C C to +150 C Voltage on any Pin with Respect to V SS C D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

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T A = +25 C, f = 1MHz, V CC = 5V

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Notes: (1) V IL min. and V IH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Units Test ConditionsMin. Max. I CC V CC Supply Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 5MHz, I SB V CC Supply Current (Standby) 1 m A CS = V CC , VIN = VSS or VCC – 0.3V ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VIL (1) Input LOW Voltage –1 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7VCC + 0.5 V VOL1 Output LOW Voltage 0.4 V IOL = 3mA, VCC = 5V VOH1 Output HIGH Voltage VCC –0.8 V IOH = –1.6mA, VCC = 5V VOL2 Output LOW Voltage 0.4 V IOL = 1.5mA, VCC = 3V VOH2 Output HIGH Voltage VCC –0.3 V IOH = –0.4mA, VCC = 3V Symbol Parameter Min. Max. Units TPUR (3) Power-up to Read Operation 1 ms TPUW (3) Power-up to Write Operation 1 ms Symbol Parameter Max. Units Test Conditions C I/O (3) Output Capacitance (SO) 8 pF VI/O = 0V C IN (3) Input Capacitance (SCK, SI, CS , WP , HOLD ) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS

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Temperature Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C

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X25330 5V –10% X25330-2.5 2.5V to 5.5V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability.

A.C. OPERATING CHARACTERISTICS Data Input Timing

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Notes:(4)This parameter is periodically sampled and not 100% tested. (5)tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 5 MHz tCYC Cycle Time 200 ns tLEAD CS Lead Time 100 ns tLAG CS Lag Time 100 ns tWH Clock HIGH Time 80 ns tWL Clock LOW Time 80 ns tSU Data Setup Time 20 ns tH Data Hold Time 20 ns tRI (4) Data In Rise Time 2 ms tFI (4) Data In Fall Time 2 ms tHD HOLD Setup Time 40 ns tCD HOLD Hold Time 40 ns tCS CS Deselect Time 100 ns tWC (5) Write Cycle Time 10 ms Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 5 MHz tDIS Output Disable Time 100 ns tV Output Valid from Clock LOW 80 ns tHO Output Hold Time 0 ns tRO (4) Output Rise Time 50 ns tFO (4) Output Fall Time 50 ns tLZ (4) HOLD HIGH to Output in Low Z 50 ns tHZ (4) HOLD LOW to Output in High Z 50 ns A.C. CONDITIONS OF TEST

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Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and OutputTiming Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT OUTPUT

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1.44KW 1.95KW 100pF OUTPUT 1.64KW 4.63KW 100pF

MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS

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0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FRM F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X) PACKAGING INFORMATION

ORDERING INFORMATION

Blank = 5V –10% Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. X25330 X X Blank = 8-Lead SOIC Blank = 5V –10%, 0°C to +70°C AE = 2.5V to 5.5V, 0°C to 70°C AF = 2.5V to 5.5V, –40°C to +85°C S8 = 8-Lead SOIC T V14 = 14-Lead TSSOP V = 14-Lead TSSOP 2.5 = 2.5 to 5.5V