X25648 XICOR | Alldatasheet
Document overview
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Technical content
Ó Xicor, Inc. 1994, 1995, 1996 Patents Pending 7032 -1.1 6/17/97 T1/C0/D0 SH Characteristics subject to change without notice 64K 32K 16K X25648/49, X25328/29, X25168/69 8K x 8 Bit 4K x 8 Bit 2K x 8 Bit V CC Supervisory Circuit w/Serial E PROM
FEATURES
- Low Vcc Detection and Reset Assertion —Reset Signal Valid to Vcc=1V
- Save Critical Data With Block Lock TM Protection —Block Lock TM Protect 0, 1/4, 1/2 or all of Serial E PROM Memory Array
- In Circuit Programmable ROM Mode
- Long Battery Life With Low Power Consumption —<1 m A Max Standby Current —<5mA Max Active Current during Write —<400 m A Max Active Current during Read Supply Operation
- 2MHz Clock Rate
- Minimize Programming Time —32 Byte Page Write Mode —Self-Timed Write Cycle —5ms Write Cycle Time (Typical)
- SPI Modes (0,0 & 1,1)
- Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Write Enable Latch —Write Protect Pin
- High Reliability
- Available Packages —14-Lead SOIC (X2564X) —14-Lead TSSOP (X2532X, X2516X) —8-Lead SOIC (X2532X, X2516X)
DESCRIPTION
These devices combines two popular functions, Supply Voltage Supervision and Serial E PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The user’s system is protected from low voltage condi- tions by the devices low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET /RESET is asserted until Vcc returns to proper operating levels and stabilizes. The memory portion of the device is a CMOS Serial E PROM array with Xicor’s Block Lock TM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. BLOCK DIAGRAM DATA REGISTER COMMAND DECODE & CONTROL LOGIC RESET CONTROL LOW VOLTAGE SENSE PROGRAMMING, BLOCK LOCK & ICP ROM CONTROL X - DECODE LOGIC STATUS REGISTER PAGE DECODE LOGIC SERIAL E PROM ARRAY HIGH VOLTAGE CONTROL SI SO SCK CS RESET /RESET V CC WP
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X25648/49, X25328/29, X25168/69 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS ) When CS is HIGH, the device is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP ) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the device Status Register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes to the Status Register operate normally. If an internal Status Register Wr ite Cycle has already been initiated, WP going low while WPEN is a “1” will have no effect on this write. Subsequent write attempts to the Status Register under these conditions will be disabled. The WP pin function is blocked when the WPEN bit in the Status Register is “0”. This allows the user to install the device in a system with WP pin grounded and still be able to program the Status Register. The WP pin functions will be enabled when the WPEN bit is set to a “1”. Reset (RESET /RESET) RESET /RESET is an active LOW/HIGH, open drain out- put which goes active whenever Vcc falls below the mini- m um Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. PIN CONFIGURATION PIN NAMES
7036 FRM T01
V SS Ground V CC Supply Voltage RESET /RESET Reset Output 14-LEAD SOIC X25648/49 NC CS CS SO WP VSS RESET /RESET SCK SI NC 8NC V CC V CC NC
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lar microcontroller families. again to resume operations where left off. instruction and can be reset by the WRDS instruction. Protection of that portion of memory.
7036 FRM T03
and must be written as “1’s” on all Status Register writes.
7036 FRM T02
Table 1. Instruction Set *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7036 FRM T04
X25648/49, X25328/29, X25168/69 The read only FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon power up. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide Programmab le Hardware Wr ite Protec- tion (Table 2). When WP is LOW and the WPEN bit is pro- grammed HIGH, all Status Register Wr ite Operations are disabled. In Circuit Programmable ROM Mode This mechanism protects the Block Lock and W atchdog bits from inadvertant corruption. It may be used to per- form an In Circuit Programmab le ROM function by hard- wiring the WP pin to ground, writing and Block Locking the desired portion of the array to be ROM, and then pro- gramming the WPEN bit HIGH. Read Sequence When reading from the E PR OM memor y array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16- bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memor y at the next address can be read sequentially by continuing to provide clock pulses. The address is auto- matically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read E PR OM Array Sequence (Figure 1). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruc- tion. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW , then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS m ust then be taken HIGH. If the user continues the Wr ite Operation without taking CS HIGH after issuing the WREN instruction, the Wr ite Operation will be ignored. To write data to the E PR OM memor y array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the Page Wr ite Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be “0”. Data bits 4 and 5 must be “1”. Table 2.
7036 FRM T06
WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK WPEN, BL0, BL1 BITS
0 X X Protected Protected Protected
1 1 0 Protected Writable Protected 1 0 X Protected Writable Writable
1 X 1 Protected Writable Writable
7036 FRM 03
requires a pull up resistor.
- The device is in the low power standby state.
- A HIGH to LO W transition on CS is required to enter an active state and receive an instruction.
- SO pin is high impedance.
- The Wr ite Enable Latch is reset.
- The Flag Bit is reset.
- Reset Signal is active for t PURST Data Protection The following circuitry has been included to prevent inad- vertent writes:
- A WREN instruction must be issued to set the Wr ite Enable Latch.
- CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
Figure 1. Read E
Figure 2. Read Status Register Sequence Figure 3. Write Enable Latch Sequence
7036 FRM 04
7036 FRM 05
Figure 4. Write Sequence Figure 5. Status Register Write Sequence
7036 FRM 06
7036 FRM 07
X25648/49, X25328/29, X25168/69 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
7036 FRM T09
7036 FRM T10
A = +25 C, f = 1MHz, V CC = 5V. Notes: (1) V IL min. and V IH max. are for reference only and are not tested.
7036 FRM T11
(2) This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Units Test ConditionsMin. Typ. Max. I CC1 V CC Write Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = Open I CC2 V CC Read Current (Active) 0.4 mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = Open I SB1 V CC Standby Current WDT=OFF 1 m A CS = V CC , V IN = V SS or V CC , V CC = 5.5V ISB2 VCC Standby Current WDT=ON 50 mA CS = VCC , VIN = VSS or VCC , VCC = 5.5V ISB3 VCC Standby Current WDT=ON 20 mA CS = VCC , VIN = VSS or VCC , VCC =3.6V ILI Input Leakage Current 0.1 10 mA VIN = VSS to VCC ILO Output Leakage Current 0.1 10 mA VOUT = VSS to VCC VIL (1) Input LOW Voltage –0.5 VCC x0.3 V VIH (1) Input HIGH Voltage VCC x0.7 VCC +0.5 V VOL1 Output LOW Voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC £ 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC £ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage VCC –0.8 V VCC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage VCC –0.4 V 2V < VCC £ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage VCC –0.2 V VCC £ 2V, IOH = –0.25mA VOLRS Reset Output LOW Voltage 0.4 V IOL = 1mA Symbol Parameter Min. Max. Units tPUR (2) Power-up to Read Operation 1 ms tPUW (2) Power-up to Write Operation 5 ms Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO, RESET , RESET) 8 pF VOUT = 0V C IN (2) Input Capacitance (SCK, SI, CS , WP ) 6 pF VIN = 0V ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS
7036 FRM T07
*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7036 FRM T08
Temp Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Supply Voltage Limits X25XXX –1.8 1.8V-3.6V X25XXX –2.7 2.7V to 5.5V X25XXX 4.5V-5.5V
X25648/49, X25328/29, X25168/69 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing
7036 FRM T13
Symbol Parameter Voltage Range Min. Max. Units fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 0 2
1 MHz
tCYC Cycle Time 2.7V–5.5V 1.8V–3.6V 500 1000 ns tLEAD CS Lead Time 2.7V–5.5V 1.8V–3.6V 250 500 ns tLAG CS Lag Time 2.7V–5.5V 1.8V–3.6V 250 500 ns tWH Clock HIGH Time 2.7V–5.5V 1.8V–3.6V 200 400 ns tWL Clock LOW Time 2.7V–5.5V 1.8V–3.6V 200 400 ns tSU Data Setup Time 2.7V–5.5V 1.8V–3.6V 50 ns tH Data Hold Time 2.7V–5.5V 1.8V–3.6V 50 ns tRI (3) Input Rise Time 2.7V–5.5V 1.8V–3.6V 100 ns tFI (3) Input Fall Time 2.7V–5.5V 1.8V–3.6V 100 ns tCS CS Deselect Time 2.7V–5.5V 1.8V–3.6V 500 ns tWC (4) Write Cycle Time 2.7V–5.5V 1.8V–3.6V 10 ms EQUIVALENT A.C. LOAD CIRCUIT AT 5V V CC A.C. TEST CONDITIONS
7036 FRM T12
3.3KW RESET/RESET 30pF 1.64KW 1.64KW Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x0.5
X25648/49, X25328/29, X25168/69 Data Output Timing
7036 FRM T14
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter Part Number Min. Max. Units fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 0 2 tDIS Output Disable Time 2.7V–5.5V 1.8V–3.6V 250 ns tV Output Valid from Clock Low 2.7V–5.5V 1.8V–3.6V 200 400 ns tHO Output Hold Time 2.7V–5.5V 1.8V–3.6V 0 ns tRO (3) Output Rise Time 2.7V–5.5V 1.8V–3.6V 100 ns tFO (3) Output Fall Time 2.7V–5.5V 1.8V–3.6V 100 ns
X25648/49, X25328/29, X25168/69 Serial Output Timing Serial Input Timing SCK CS SO SI MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI HIGH IMPEDANCE
X25648/49, X25328/29, X25168/69 Power-Up and Power-Down Timing RESET Output Timing
7036 FRM T15
Notes: (5) This parameter is periodically sampled and not 100% tested. Symbol Parameter Min. Typ. Max. Units VTRIP Reset Trip Point Voltage, 5V Device Reset Trip Point Voltage, 2.7V Device Reset Trip Point Voltage, 1.8V Device 4.25 2.55 1.7 4.5 2.7 1.8 V V V tPURST Power-up Reset Timeout 100 200 280 ms tRPD (5) VCC Detect to Reset/Output 500 ns tF (5) VCC Fall Time 0.1 ns tR (5) VCC Rise Time 0.1 ns VRVALID Reset Valid VCC 1 V VCC tPURST tPURST tR tF tRPD RESET (X25643)
0 Volts
RESET (X25645)
X25648/49, X25328/29, X25168/69 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-LEAD PLASTIC SMALL OUTLINE GULL WING P A CKA GE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050"Typical 0.030"Typical
14 PlacesFOO TPRINT
0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45°
X25648/49, X25328/29, X25168/69 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL
8 PLACESFOOTPRINT
X25648/49, X25328/29, X25168/69 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)
X25648/49, X25328/29, X25168/69
ORDERING INFORMATION
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. VCC Limits Blank = 5V –10% 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S14 = 14-Lead SOIC S8 = 8-Lead SOIC V14 = 14-Lead TSSOP Blank = 14-Lead SOIC Blank = 5V –10%, 0°C to +70°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C AG = 1.8V to 3.6V, 0°C to +70°C X25648/49 P T -V X25648/49 X X X25328/29 X25168/69 Blank = 8-Lead SOIC V = 14 Lead TSSOP Blank = 5V –10%, 0°C to +70°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C AG = 1.8V to 3.6V, 0°C to +70°C X25328/29 X X X25168/69