X25644 XICOR | Alldatasheet
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Technical content
Ó Xicor, Inc. 1994, 1995, 1996 Patents Pending 7050 -1.0 6/20/97 T0/C0/D0 SH Characteristics subject to change without notice 64K 32K 16K X25644/46 X25324/26 X25164/66 8K x 8 Bit 4K x 8 Bit 2K x 8 Bit Programmable Watchdog Timer w/Serial E PROM
FEATURES
- Programmable Watchdog Timer with Reset Assertion —Reset Signal Valid to Vcc=1V —Power Up Reset Control
- Save Critical Data With Block Lock TM Protection —Block Lock TM Protect 0, 1/4, 1/2 or all of Serial E PROM Memory Array
- In Circuit Programmable ROM Mode
- Long Battery Life With Low Power Consumption —<50 m A Max Standby Current, Watchdog On —<1 m A Max Standby Current, Watchdog Off —<5mA Max Active Current during Write —<400 m A Max Active Current during Read Supply Operation
- 2MHz Clock Rate
- Minimize Programming Time —32 Byte Page Write Mode —Self-Timed Write Cycle —5ms Write Cycle Time (Typical)
- SPI Modes (0,0 & 1,1)
- Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Write Enable Latch —Write Protect Pin
- High Reliability
- Available Packages —14-Lead SOIC (X2564x) —14-Lead TSSOP (X2532x, X2516x) —8-Lead SOIC (X2532x, X2516x)
DESCRIPTION
These devices combine two popular functions, Watchdog Timer, and Serial E PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET /RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial E PROM array with Xicor’s Block Lock TM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. BLOCK DIAGRAM DATA REGISTER COMMAND DECODE & CONTROL LOGIC RESET CONTROL WRITE, BLOCK LOCK & ICP ROM CONTROL X - DECODE LOGIC STATUS REGISTER WATCHDOG PAGE DECODE LOGIC SERIAL E PROM ARRAY HIGH VOLTAGE CONTROL SI SO SCK CS RESET /RESET WP
7029 FRM 01
Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS ) When CS is HIGH, the device is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device’s, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP ) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the device’s Status Register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes to the Status Register operate normally. If an internal Status Register Wr ite Cycle has already been initiated, WP going low while WPEN is a “1” will have no effect on this write. Subsequent write attempts to the Status Register under these conditions will be disabled. The WP pin function is blocked when the WPEN bit in the Status Register is “0”. This allows the user to install the device in a system with WP pin grounded and still be able to program the Status Register. The WP pin functions will be enabled when the WPEN bit is set to a “1”. Reset (RESET /RESET) RESET /RESET is an active LOW/HIGH, open drain out- put which goes active whenever the W atchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable W atchdog time-out period. It will remain active for t RST , the Reset Timeout period. A falling edge of CS will reset the W atchdog Timer. PIN CONFIGURATION PIN NAMES
7029 FRM T01
V SS Ground V CC Supply Voltage RESET /RESET Reset Output 14-LEAD SOIC X25644/46 NC CS CS SO WP VSS RESET /RESET SCK SI NC 8NC V CC V CC NC
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0.345” 0.200” 0.197” 0.244” 0.177” 0.244” Not to Scale
lar microcontroller families. during the entire operation. again to resume operations where left off. instruction and can be reset by the WRDI instruction. Protection of that portion of memory.
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7029 FRM T02
Table 1. Instruction Set *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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programmed with the WRSR instruction.
7029 FRM T05
$0000 allowing the read cycle to be continued indefinitely. PR OM Array Sequence (Figure 1). the Read Status Register Sequence (Figure 2). then the WREN instruction is clocked into the device. WREN instruction, the Wr ite Operation will be ignored. Table 2. Block Protect Matrix
7029 FRM T06
0 X X Protected Protected Protected
1 X 1 Protected Unprotected Unprotected
7029 FRM 03
requires a pull up resistor.
- The device is in the low power standby state.
- A HIGH to LO W transition on CS is required to enter an active state and receive an instruction.
- SO pin is high impedance.
- The Wr ite Enable Latch is reset.
- The Flag Bit is reset.
- Reset Signal is active for t PURST Data Protection The following circuitry has been included to prevent inad- vertent writes:
- A WREN instruction must be issued to set the Wr ite Enable Latch.
- CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
Figure 1. Read E
Figure 2. Read Status Register Sequence Figure 3. Write Enable Latch/Flag Bit Sequence
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Figure 4. Write Sequence Figure 5. Status Register Write Sequence
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
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7029 FRM T10
Units Test ConditionsMin. Typ. Max. I CC1 V CC Write Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = Open I CC2 V CC Read Current (Active) 0.4 mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = Open I SB1 V CC Standby Current WDT=OFF 1 m A CS = V CC , V IN = V SS or V CC I SB2 V CC Standby Current WDT=ON 50 m A CS = V CC , V IN = V SS or V CC , V CC = 5.5V I SB3 V CC Standby Current WDT=ON 20 m A CS = V CC , V IN = VSS or VCC , VCC =3.6V ILI Input Leakage Current 0.1 10 mA VIN = VSS to VCC ILO Output Leakage Current 0.1 10 mA VOUT = VSS to VCC VIL (1) Input LOW Voltage –0.5 VCC x0.3 V VIH (1) Input HIGH Voltage VCC x0.7 VCC +0.5 V VOL1 Output LOW Voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC £ 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC £ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage VCC –0.8 V VCC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage VCC –0.4 V 2V < VCC £ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage VCC –0.2 V VCC £ 2V, IOH = –0.25mA VOLRS Reset Output LOW Voltage 0.4 V IOL = 1mA Symbol Parameter Min. Max. Units tPUR (2) Power-up to Read Operation 1 ms tPUW (2) Power-up to Write Operation 5 ms ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS
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*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7029 FRM T08
Temp Min. Max. Commercial 0°C 70°C Industrial –40°C +85°C Supply Voltage Limits X25xxx–1.8 1.8V-3.6V X25xxx–2.7 2.7V to 5.5V X25xxx 4.5V-5.5V
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing
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Symbol Parameter Voltage Range Min. Max. Units fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 0 2
1 MHz
tCYC Cycle Time 2.7V–5.5V 1.8V–3.6V 500 1000 ns tLEAD CS Lead Time 2.7V–5.5V 1.8V–3.6V 250 500 ns tLAG CS Lag Time 2.7V–5.5V 1.8V–3.6V 250 500 ns tWH Clock HIGH Time 2.7V–5.5V 1.8V–3.6V 200 400 ns tWL Clock LOW Time 2.7V–5.5V 1.8V–3.6V 200 400 ns tSU Data Setup Time 2.7V–5.5V 1.8V–3.6V 50 ns tH Data Hold Time 2.7V–5.5V 1.8V–3.6V 50 ns tRI (3) Input Rise Time 2.7V–5.5V 1.8V–3.6V 100 ns tFI (3) Input Fall Time 2.7V–5.5V 1.8V–3.6V 100 ns tCS CS Deselect Time 2.7V–5.5V 1.8V–3.6V 500 ns tWC (4) Write Cycle Time 2.7V–5.5V 1.8V–3.6V 10 ms EQUIVALENT A.C. LOAD CIRCUIT AT 5V V CC A.C. TEST CONDITIONS
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3.3KW RESET/RESET 30pF 1.64KW 1.64KW Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x0.5 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Notes: (1) VIL min. and VIH max. are for reference only and are not tested. 7029 FRM T11 (2) This parameter is periodically sampled and not 100% tested. Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO, RESET /RESET) 8 pF VOUT = 0V C IN (2) Input Capacitance (SCK, SI, CS , WP ) 6 pF VIN = 0V
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Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing Serial Input Timing Symbol Parameter Voltage Range Min. Max. Units fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 0 2 tDIS Output Disable Time 2.7V–5.5V 1.8V–3.6V 250 ns tV Output Valid from Clock Low 2.7V–5.5V 1.8V–3.6V 200 400 ns tHO Output Hold Time 2.7V–5.5V 1.8V–3.6V 0 ns tRO (3) Output Rise Time 2.7V–5.5V 1.8V–3.6V 100 ns tFO (3) Output Fall Time 2.7V–5.5V 1.8V–3.6V 100 ns SCK CS SO SI MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAGtLEAD tH LSB IN tCS tFI HIGH IMPEDANCE
CS vs. RESET /RESET Timing
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Power Up and Down Timing Diagram
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RESET /RESET Output Timing
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Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 200 600 1.4 300 800 ms ms sec tCST CS Pulse Width to Reset the Watchdog 400 ns tRST Reset Timeout 100 200 300 ms tPURST Power Up Reset Timeout 100 350 ms VRST Reset Valid Voltage 1.0 V CS tCST RESET tWDO tRST RESET tWDO tRST VCC RESET VRST RESET tPURST
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-LEAD PLASTIC SMALL OUTLINE GULL WING P A CKA GE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050"Typical 0.030"Typical
14 PlacesFOO TPRINT
0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45°
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL
8 PLACESFOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
ORDERING INFORMATION
Blank = 5V –10% 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S14 = 14-Lead SOIC S8 = 8-Lead SOIC V14 = 14-Lead TSSOP Blank = 14-Lead SOIC Blank = 5V –10%, 0°C to +70°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C AG = 1.8V to 3.6V, 0°C to +70°C X25644/46 P T -V X X X25324/26 X25164/66 Blank = 8-Lead SOIC V = 14 Lead TSSOP Blank = 5V –10%, 0°C to +70°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C AG = 1.8V to 3.6V, 0°C to +70°C X25324/26 X X X25164/66 X25644/46