X24F128S-5

X24F128 XICOR | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

2-Wire SerialFlash with Block Lock TM Protection 128K 16K x 8 Bit Ó Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice 7012-0.8 11/25/96 T1/C0/D0 SH X24F128 FUNCTIONAL DIAGRAM

FEATURES

Save Critical Data With Programmable Block Lock Protection —Block Lock (0, 1/4, 1/2, or all of E PROM Array) —Software Program Protection —Programmable Hardware Program Protect In Circuit Programmable ROM Mode Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Program Current Less Than 3mA —Standby Current Less Than 1 m A 1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions

32 Word Sector Program Mode

—Minimizes Total Program Time Per Word 100KHz 2-Wire Serial Interface Internally Organized 16K x 8 Bidirectional Data Transfer Protocol Self-Timed Program Cycle —Typical Program Cycle Time of 5ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8-Lead DIP 16-Lead SOIC

DESCRIPTION

The X24F128 is a CMOS SerialFlash Memory, inter- nally organized 16K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S ) allow up to eight devices to share a common two wire bus. A Program Protect Register at the address location FFFFh provides three program protection features: Software Program Protect, Block Lock Protect, and Hardware Program Protect. The Software Program Protect feature prevents any nonvolatile writes to the device until the PEL bit in the Program Protect Register is set. The Block Lock Protection feature allows the user to individually block protect four blocks of the array by programming two bits in the Program Protect Register. The Programmable Hardware Program Protect feature allows the user to install the device with PP tied to V CC , program the entire memory array in circuit, and then enable the hardware program protection by programming a PPEN bit in the Program Protect Register. After this, selected blocks of the array, including the Program Protect Register itself, are permanently protected from being erased. SCL SERIALFLASH DATA AND ADDRESS (SDA) PP PROGRAM VOLTAGE CONTROL SERIALFLASH ARRAY 16K x 8 4K x 8 4K x 8 8K x 8 COMMAND DECODE AND CONTROL LOGIC SECTOR DECODE LOGIC DEVICE SELECT LOGIC PROGRAM PROTECT REGISTER BLOCK LOCK AND PROGRAM PROTECT CONTROL LOGIC Y DECODE LOGIC DATA REGISTER 7012 ILL F01.4 A PPLICATION N OTE A V A I L A B L E AN84

Xicor SerialFlash Memories are designed and tested for applications requiring e xtended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SD A is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and ma y be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S , S , S The device select inputs (S , S , S ) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appro- priate. If actively driven, they m ust be driven with CMOS levels. Program Protect (PP) The Program Protect input controls the Hardware Program Protect feature. When held LOW , hardware program protection is disabled and the device can be programmed nor mally. When this input is held HIGH, and the PPEN bit in the Program Protect Register is set HIGH, program protection is enabled, and nonvola- tile writes are disabled to the selected blocks as well as the Program Protect Register itself. PIN NAMES

7012 FRM T01

S , S , S Device Select Inputs SDA Serial Data SCL Serial Clock PP Program Protect V SS Ground V CC Supply Voltage NC No Connect VCC PP SCL SDA VSS 8-LEAD DIP 16-LEAD SOIC NC NC NC NC VSS VCC PP NC NC NC NC SCL SDA X24F128 X24F128 7012 ILL F02.1

Figure 3. Acknowledge Response From Receiver after the transmitting device has released the bus. that it received the eight bits of data. Refer to Figure 3. after the receipt of each subsequent byte. place the device into a known state.

7012 ILL F05

Figure 4. Device Addressing

1 S1 S0 R/W

0 A10 A9 A80 A13

a program operation is selected. Refer to figure 4. clock cycle and the device returns to the standby mode. two Address Bytes as shown in figure 4.

Figure 5. Sector Program Sequence disabled until completion of the nonvolatile write cycle.

7012 ILL F09

Random Reads , and Sequential Reads. the ninth clock cycle and then issue a stop condition.

7012 ILL F10

Figure 6. Acknowledge Polling Sequence Figure 7. Current Address Read Sequence

PROGRAM PROTECT REGISTER (PPR) Register Program Operation The Program Protect Register can only be modified by programming one data byte directly to the address FFFFh as described below. The data byte must contain zeroes where indicated in the procedural descriptions below; otherwise the oper- ation will not be performed. Only one data byte is allow ed for each Register Program Oper ation. The part will not acknowledge any data bytes after the first byte is entered. The user then has to issue a stop to initiate the nonvolatile write cycle that programs BL0, BL1, and PPEN to the nonvolatile bits. A stop must also be issued after volatile register program opera- tions to put the device into Standby. The state of the Program Protect Register can be read by performing a random read at FFFFh at any time. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the protocol. After the read, the address counter contains 0000h. Program Protect Register: PPR (ADDR = FFFF h PEL: Program Enable Latch (Volatile) 0 = PEL reset, programming disabled. 1 = PEL set, programming enabled. RPEL: Register Program Enable Latch (Volatile) 0 = RPEL reset, programs to the Program Protect Register disabled. 1 = RPEL set, programs to the Program Protect Register enabled. BL0, BL1: Block Lock Protect Bits (Nonvolatile) The Block Lock Protect Bits, BL0 and BL1, determine which blocks of the array are protected. A program to a protected block of memory is ignored, but will receive an acknowledge. The master must issue a stop to put the part into standby, just as it would for a valid program; but the stop will not initiate an internal nonvolatile write cycle. See figure 10. PPEN: Program Protect Enable Bit (Nonvolatile) The Program Protect (PP ) pin and the Program Protect Enable (PPEN) bit in the Program Protect Register control the Programmab le Hardw are Program Protection feature. Hardw are Prog ram Protection is enabled when the PP pin is HIGH and the PPEN bit is HIGH, and disabled when either the PP pin is LOW or the PPEN bit is LOW . When the chip is Hardware Program Protected, nonvolatile writes are disabled to the Program Protect Register, including the Block Lock Protect bits and the PPEN bit itself, as well as to the Block Lock protected sections in the memory array. Only the sections of the memory array that are not Block Lock protected, and the volatile bits PEL and RPEL, can be programmed. In Circuit Programmable ROM Mode Note that since the PPEN bit is program protected, it cannot be changed back to a LOW state; so program protection is enabled as long as the PP pin is held HIGH. Thus an In Circuit Programmab le ROM function can be implemented by hardwiring the PP pin to Vcc, programming and Block Locking the desired portion of the array to be ROM, and then programming the PPEN bit HIGH. Figure 11 defines the program protect status for each combination of PPEN and PP. Programming the PEL and RPEL bits PEL and RPEL are volatile latches that pow er up in the LOW (disabled) state. While the PEL bit is LOW , program operations to any address other than FFFFh will be ignored (no acknowledge will be issued after the data byte). The PEL bit is set by programming 00000010 to address FFFFh. Once set, PEL remains HIGH until either it is reset to 0 (by programming 00000000 to FFFFh) or until pow er cycles. Program- ming PEL and RPEL does not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. The RPEL bit controls programming to the Block Lock Protect bits, BL0 and BL1, and the PPEN bit. If RPEL is 0 then no prog ramming oper ations can be performed on BL0, BL1, or PPEN. RPEL is reset when pow er cycles or after any nonvolatile write, including those to the Block Lock Protect bits, the PPEN bit, or any sector in the memory array. RPEL m ust be reset before PEL can be reset. RPEL and PEL cannot be reset in one program operation. RPEL can also be reset by programming u00xy010 to FFFFh ONL Y when the PPR is NOT protected. This is the same operation as in step 3 described below, and will result in programming BL0, BL1, and PPEN. 7 6 5 4 3 2 1 0 PPEN 0 0 BL1 BL0 RPEL PEL 0

and the device remains at step 2. master issues the stop condition in step 3. Figure 10. Block Lock Protect Bits and Protected Addresses

7012 FRM T02

Figure 11. PP Pin and PPEN Bit Functionality

7012 FRM T03

0 X Programmab le Protected Programmab le Programmab le

ABSOLUTE MAXIMUM RATINGS* Temperature under Bias C to +135 C C to +150 C Voltage on any Pin with Respect to V SS Lead Temperature C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS 7012 FRM T06.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

7012 FRM T07

Notes:(1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels @ 100KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3VICC2 VCC Supply Current (Program) 3 mA ISB1 (1) VCC Standby Current 10 mA SCL = SDA = VCC – 0.3V, All Other Inputs = VSS or VCC – 0.3V, VCC = 5V – 10% ISB2 (1) VCC Standby Current 1 mA SCL = SDA = VCC – 0.1V, All Other Inputs = VSS or VCC – 0.1V, VCC = 1.8V ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (2) Input LOW Voltage –0.5 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 3mA Vhys (3) Hysteresis of Schmitt Trigger Inputs VCC x 0.05 V Symbol Parameter Max. Units Test Conditions C I/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V C IN (3) Input Capacitance (S0, S1, S2, SCL, PP) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS

7012 FRM T04

Temperature Min. Max. Commercial 0°C +70°C Extended –20°C +85°C

7012 FRM T05

X24F128 1.8V to 3.6V X24F128–5 4.5V to 5.5V

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Program Cycle Limits

7012 FRM T09

POWER-UP TIMING (4)

7012 FRM T10

Notes:(4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 50 100 ns tAA SCL LOW to SDA Data Out Valid 0.3 3.5 ms tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 ms tHD:STA Start Condition Hold Time 4 ms tLOW Clock LOW Period 4.7 ms tHIGH Clock HIGH Period 4 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 ms tHD:DAT Data In Hold Time 0 ms tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 ms tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 ms tDH Data Out Hold Time 300 ns Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms A.C. CONDITIONS OF TEST

7012 FRM T08

Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT 7012 ILL F14.1 1.53KΩ 100pF OUTPUT

Don’t Care: Changes Allow ed Changing: State Not Known N/A Center Line is High Impedance The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal erase/program cycle. During the program cycle, the X24F128 bus interface circuits are disabled, SDA is allow ed to remain HIGH, and the device does not respond to its slave address. Bus Timing

7012 ILL F15

tSU:STA tHD:ST A tHD:DA T tSU:DA T tLOW tSU:ST O tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH Program Cycle Limits

7012 FRM T11

Symbol Parameter Min. Typ.(5) Max. Units TWR (6) Program Cycle Time 5 10 ms

7012 ILL F16

Guidelines for Calculating Typical Values of Bus Pull-Up Resistors

7012 ILL F17

RESIST ANCE (K Ω ) BUS CAP ACITANCE (pF) MIN. RESIST ANCE MAX. RESIST ANCE R MAX =C BUS tR R MIN = IOL MIN VCC MAX =1.8KΩ Bus Timing Notes:(5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the nonvolatile write operation.

3926 FHD F01

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.012 (0.30) 0° – 8° X 45°

3926 FHD F26

16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

16 PlacesFOOTPRINT

ORDERING INFORMATION

Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V Temperature Range Blank = 0°C to +70°C E = –20°C to +85°C Package P = 8-Lead Plastic DIP S = 16-Lead SOIC Blank = 1.8V to 3.6V, 0°C to +70°C 5 = 4.5V to 5.5V, 0°C to +70°C E5 = 4.5V to 5.5V, –20°C to +85°C X24F128 X X LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. X24F128 P = 8-Lead Plastic DIP S = 16-Lead SOIC E = 1.8V to 3.6V, –20°C to +85°C