X24F064 XICOR | Alldatasheet
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Technical content
Ó Xicor, 1995, 1996 Patents Pending 6686-3.8 8/29/96 T3/C0/D0 SH Characteristics subject to change without notice X24F064/032/016 FUNCTIONAL DIAGRAM
FEATURES
1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions Low Power CMOS —Active Read Current Less Than 1mA —Active Program Current Less Than 3mA —Standby Current Less Than 1 m A Internally Organized 8K/4K/2K x 8 New Programmable Block Lock Protection —Software Write Protection —Programmable hardware Write Protect Block Lock (0, 1/4, 1/2, or all of the Flash Memory array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Sector Programming
—Typical Programming Time of 5ms Per Sector High Reliability —Endurance: 100,000 cycles per byte —Data Retention: 100 Years Available Packages —8-Lead PDIP —8-Lead SOIC (JEDEC) —14-Lead TSSOP (X24F032/016) —20-Lead TSSOP (X24F064)
DESCRIPTION
The X24F064/032/016 is a CMOS SerialFlash Memory Family, internally organized 8K/4K/2K x 8. The family features a serial interface and software protocol allowing operation on a simple two wire bus. Device select inputs (S S S ) allow up to eight devices to share a common two wire bus. A Program Protect Register accessed at the highest address location, provides three new programming protection features: Software Programming Protection, Block Lock Protection, and Hardware Programming Protection. The Software Programming Protection feature prevents any nonvolatile writes to the device until the WEL bit in the program protect register is set. The Block Lock TM Protection feature allows the user to individually protect four blocks of the array by program- ming two bits in the programming protect register. The Programmable Hardware Program Protect feature allows the user to install each device with PP tied to V CC , program the entire memory array in place, and then enable the hardware programming protection by programming a PPEN bit in the program protect register. After this, selected blocks of the array, including the program protect register itself, are permanently protected from being programmed. 6686 ILL F01.5 COMMAND DECODE AND CONTROL LOGIC X DECODE LOGIC SECTORED MEMORY ARRAY SDA SCL S2/S2 PROGRAM PROTECT REGISTER PROGRAMMING CONTROL LOGICPP HIGH VOLTAGE CONTROL SECTOR DECODE LOGIC 32 8 DATA REGISTER S1/S1 S0/S0 SerialFlash Ô Memory and Block Lock Ô Protection are trademarks of Xicor, Inc. A PPLICATION N OTE A V A I L A B L E AN76 • AN78 • AN81 • AN87
Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SD A is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and ma y be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. Device Select (S , S , S , S , S , S The device select inputs are used to set the device select bits of the 8-bit slave address. This allows m ultiple devices to share a common bus. These inputs can be static or actively driven. If used statically they m ust be tied to V SS or V CC as appropriate. If actively driven, they must be driven with CMOS levels (driven to V CC or V SS Program Protect (PP) The program protect input controls the hardware program protect feature. When held LOW , hardware program protection is disabled and the X24F064/ 032/016 can be programmed nor mally. When this input is held HIGH, and the PPEN bit in the program protect register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as w ell as the program protect register itself. PIN NAMES 6686 FRM T01.1 Symbol Description S , S , S , S , S , S Device Select Inputs SDA Serial Data SCL Serial Clock PP Program Protect V SS Ground V CC Supply Voltage NC No Connect PIN CONFIGURATION NC NC NC S VSS 14-LEAD TSSOP VCC PP NC NC NC SCL SDA 14-LEAD TSSOP NC NC NC S VSS VCC PP NC NC NC SCL SDA 20-LEAD TSSOP NC NC NC NC NC S VSS NC NC NC VCC PP NC NC NC SCL SDA NC NC VCC PP SCL SDA VSS 8-LEAD DIP & SOIC VCC PP SCL SDA VSS 8-LEAD DIP & SOIC VCC PP SCL SDA NC S VSS 8-LEAD DIP & SOIC X24F064 X24F032 X24F016 6686 ILL F02.4
after the transmitting device has released the bus. that it received the eight bits of data. Refer to Figure 3. place the device into a known state. Figure 3. Acknowledge Response From Receiver
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the corresponding input pin. Figure 4. Slave Address
1 A9 A8 R/W
X24F064/032/016 requires a second address field. Figure 5. Sector Programming
Flow 1. ACK Polling Sequence After the receipt of each byte, the five low order ad- dress bits are internally incremented by one. The high order bits of the sector address remain constant. If the master should transmit more or less than 32 bytes prior to generating the stop condition, the contents of the sector cannot be guaranteed. All inputs are disabled until completion of the internal program cycle. Refer to Figure 5 for the address, acknowledge and data trans- fer sequence. Acknowledge Polling The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1. READ OPERATIONS Read operations are initiated in the same manner as program operations with the exception that the R/W bit of the slave address is set HIGH . There are three basic read operations: current address read, random read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read op- eration, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. 6686 ILL F09.1 PROGRAM OPERA TION COMPLETED ENTER ACK POLLING ISSUE STAR T ISSUE SLAVE ADDRESS AND R/W = 0 ACK RETURNED? NEXT OPERA TION A WRITE? ISSUE SECT OR ADDRESS PROCEED ISSUE STOP NO YES YES PROCEED ISSUE STOP NO
then issuing a stop condition. address, acknowledge and data transfer sequence. Figure 8. Sequential Read Figure 9. Typical System Configuration
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Figure 10. Program Protect Register If WEL = 0 then “no ACK” after first byte of input data. ming is not disabled by the Block Lock register).
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writing 0000001x to the highest address location.
Table 1. Block Lock Bits
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tion is disabled as long as the PP pin is held HIGH. Table 2. Program Protect Status Table
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0 X Programmable Locked Programmable Programmable
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Voltage on any Pin with *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) 6686 FRM T06.4 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 2.7V
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Notes:(1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels @ 100KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3V ICC2 VCC Supply Current (Write) 3 mA ISB1 (1) VCC Standby Current 1 mA SCL = SDA = VCC , All Other Inputs = VSS or VCC – 0.3V, VCC = 3.6V ISB2 (1) VCC Standby Current 10 mA SCL = SDA = VCC , All Other Inputs = VSS or VCC – 0.3V, VCC = 5V –10% ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (2) Input LOW Voltage –1 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 3mA Symbol Parameter Max. Units Test Conditions C I/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V C IN (3) Input Capacitance (S1, S2, SCL) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS 6686 FRM T04.2 Temperature Min. Max. Commercial 0°C +70°C Extended –20°C +85°C Industrial –40°C +85°C 6686 FRM T05.2 Supply Voltage Limits X24F064/032/016 1.8V to 3.6V X24F064/032/016–5 4.5V to 5.5V
A.C. CONDITIONS OF TEST
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Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT 6686 ILL F16.1 1533Ω 100pF OUTPUT 2.7V 1533Ω 100pF OUTPUT A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits 6686 FRM T09.1 POWER-UP TIMING (4)
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Notes:(4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL LOW to SDA Data Out Valid 0.3 3.5 ms tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 ms tHD:STA Start Condition Hold Time 4 ms tLOW Clock LOW Period 4.7 ms tHIGH Clock HIGH Period 4 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 ms tHD:DAT Data In Hold Time 0 ms tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 ms tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 ms tDH Data Out Hold Time 300 ns Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms
Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance The program cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the program cycle, the X24F064/032/016 bus interface circuits are disabled, SD A is allow ed to remain HIGH, and the device does not respond to its slave address. Bus Timing
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tSU:STA tHD:ST A tHD:DA T tSU:DA T tLOW tSU:ST O tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH Program Cycle Limits 6686 FRM T11.1 Symbol Parameter Min. Typ.(5) Max. Units tPR (6) Program Cycle Time 5 10 ms Bus Timing
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Notes:(5) Typical values are for TA = 25°C and nominal supply voltage (2.7V). (6) tWR is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal program operation. Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 6686 ILL F19.1 120 100 20 40 60 80 100 120 RESIST ANCE (K Ω ) BUS CAP ACITANCE (pF) MIN. RESIST ANCE MAX. RESIST ANCE R MAX =C BUS tR R MIN = IOL MIN VCC MAX =1.2KΩ
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NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL
8 PLACESFOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .193 (4.9) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)
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NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .252 (6.4) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)
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ORDERING INFORMATION
Blank = Commercial = 0°C to +70°C E = Extended = –20°C to +85°C Package P = 8-Lead Plastic DIP P = 8-Lead Plastic DIP Blank = 8-Lead SOIC (JEDEC) Blank = 1.8V to 3.6V, 0°C to +70°C E = 1.8V to 3.6V, –20°C to +85°C X24FXXX X X LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. S = 8-Lead SOIC (JEDEC) V = 14-Lead TSSOP X24F032 X24F016 X24F064 V = 14/20-Lead TSSOP X24F064 X24F032 X24F016 X24F064 X24F032 X24F016 V CC Range Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC) V = 20-Lead TSSOP 5 = 4.5V to 5.5V, 0°C to +70°C I5 = 4.5V to 5.5V, –40°C to +85°C I = Industrial = –40°C to +85°C