X24641 XICOR | Alldatasheet
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Technical content
400 KHz 2-Wire Serial E
Ó Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice 7026 3/27/97 T0/C0/D0 SH X24641 FUNCTIONAL DIAGRAM
FEATURES
—Active Read Current Less Than 1mA —Active Write Current Less Than 3mA —Standby Current Less Than 1 m A 400KHz Fast Mode 2-Wire Serial Interface —Down to 1.8V —Schmitt Trigger Input Noise Suppression —Output Slope Control for Ground Bounce Noise Elimination Internally Organized 8K x 8
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte Hardware Write Protect Bidirectional Data Transfer Protocol Self-Timed Write Cycle —Typical Write Cycle Time of 5ms High Reliability —Endurance: 1,000,000 Cycles —Data Retention: 100 Years 8-Lead SOIC
DESCRIPTION
The X24641 is a CMOS Serial E PROM Memory, internally organized 8K x 8. The device features a serial interface and software protocol allowing opera- tion on a simple two wire bus. The bus operates at 400KHz all the way down to 1.8V. Three device select inputs (S ) allow up to eight devices to share a common two wire bus. Hardware Write Protection is provided through a Write Protect (WP) input pin on the X24641. When the WP pin is HIGH, the upper quadrant of the Serial E PROM array is protected against any nonvolatile write attempts. Xicor Serial E PROM Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. SERIAL E2PROM DATA AND ADDRESS (SDA) SCL WP COMMAND DECODE AND CONTROL LOGIC DEVICE SELECT LOGIC WRITE PROTECT LOGIC PAGE DECODE LOGIC DATA REGISTER Y DECODE LOGIC E 2PROM WRITE VOLTAGE CONTROL
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Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SD A is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and ma y be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S , S , S The device select inputs (S , S , S ) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appro- priate. If actively driven, they m ust be driven with CMOS levels. Write Protect (WP) The Wr ite Protect input controls the Hardware Wr ite Protect feature. When held LO W , Hardware Wr ite Protection is disabled and the device can be written normally. When this input is held HIGH, Wr ite Protec- tion is enabled, and nonvolatile writes are disabled to the upper quadrant of the E PR OM array. PIN NAMES
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S , S , S Device Select Inputs SDA Serial Data SCL Serial Clock WP Write Protect V SS Ground V CC Supply Voltage VCC WP SCL SD A VSS X24641 8-LEAD SOIC
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Figure 3. Acknowledge Response From Receiver after the transmitting device has released the bus. that it received the eight bits of data. Refer to Figure 3. after the receipt of each subsequent byte. place the device into a known state.
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Figure 4. Device Addressing
1 S1 S0 R /W
0 A10 A9 A80
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then a Wr ite Operation is selected. Refer to figure 4. clock cycle and the device returns to the standby mode. two Address Bytes as shown in figure 4.
Figure 5. Page Write Sequence pin is at high impedance. See figure 4. mented by one, while page address remains constant. acknowledge, and data transfer sequence.
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Figure 4. Byte Write Sequence
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Random Reads , and Sequential Reads. over” to the first address of the same page. the ninth clock cycle and then issue a stop condition.
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Figure 6. Acknowledge Polling Sequence Figure 7. Current Address Read Sequence
master must first perform a “Dumm y” write operation. address, acknowledge, and data transfer sequence. address counter, but no data is output by the device. from the newly loaded address.
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Figure 8. Random Read Sequence Figure 9. Sequential Read Sequence
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias C to +135 C C to +150 C Voltage on any Pin with Respect to V SS Lead Temperature C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS 7026 FRM T06.1 CAPACITANCE T A = +25 C, f = 1MHz, V CC = 5V
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Notes: (1) Must perform a stop command prior to measurement. (2) V IL min. and V IH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions I CC1 V CC Supply Current (Read) 1 mA SCL = V CC X 0.1/VCC X 0.9 Levels @ 400KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3V ICC2 VCC Supply Current (Write) 3 mA ISB1 (1) VCC Standby Current 3 mA SCL = SDA = VCC – 0.3V, All Other Inputs = VSS or VCC – 0.3V, VCC = 5V – 10% ISB2 (1) VCC Standby Current 1 mA SCL = SDA = VCC – 0.1V, All Other Inputs = VSS or VCC – 0.1V, VCC = 1.8V ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (2) Input LOW Voltage –0.5 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 3mA Vhys (3) Hysteresis of Schmitt Trigger Inputs VCC x 0.05 V Symbol Parameter Max. Units Test Conditions C I/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V C IN (3) Input Capacitance (S0, S1, S2, SCL,WP) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS
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Temperature Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C
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X24641 4.5V to 5.5V X24641–2.5 2.5V to 5.5V X24641–1.8 1.8V to 3.6V
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Program Cycle Limits
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POWER-UP TIMING (4)
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Notes: (4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (5) C b = total capacitance of one bus line in pF (6) tAA = 1.1ms Max below VCC = 2.5V. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 400 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA (6) SCL LOW to SDA Data Out Valid 0.1 0.9 ms tBUF Time the Bus Must Be Free Before a New Transmission Can Start 1.2 ms tHD:STA Start Condition Hold Time 0.6 ms tLOW Clock LOW Period 1.2 ms tHIGH Clock HIGH Period 0.6 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 ms tHD:DAT Data In Hold Time 0 ms tSU:DAT Data In Setup Time 100 ns tR SDA and SCL Rise Time 20+0.1XCb (5) 300 ns tF SDA and SCL Fall Time 20+0.1XCb (5) 300 ns tSU:STO Stop Condition Setup Time 0.6 ms tDH Data Out Hold Time 50 ns tOF Output Fall Time 20 + 0.1Cb (5) 250 ns Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms A.C. CONDITIONS OF TEST
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Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT 1.53KW 100pF OUTPUT
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Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance
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The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal erase/program cycle. During the program cycle, the X24641 bus interface circuits are disabled, SDA is allow ed to remain HIGH, and the device does not respond to its slave address. Bus Timing tSU:STA tHD:STA tHD:D AT tSU:D AT tLOW tSU:STO tR tBUF SCL SDA IN SD A OUT tDHtAA tF tHIGH
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Symbol Parameter Min. Typ.(7) Max. Units TWR (8) Program Cycle Time 5 10 ms SCL SD A 8th BIT W ORD n ACK tWR ST OP CONDITION STAR T CONDITION 7026 FM 15 Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 120 100 20 40 60 80 100 120 RESISTANCE (K W ) BUS CAPACITANCE (pF) MIN. RESIST ANCE MAX. RESIST ANCE R MAX = C BUS tR R MIN = IOL MIN V CC MAX =1.8KW
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Notes:(7) Typical values are for TA = 25°C and nominal supply voltage (5V). (8) tWR is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the nonvolatile write operation.
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL
8 PLACESFOOTPRINT
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ORDERING INFORMATION
X LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. V CC Range Blank = 5V –10% 2.5 = 2.5V to 5.5V Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C Package X24641 Blank = 8-Lead SOIC Blank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C AE = 2.5V to 5.5V, 0°C to +70°C AF = 2.5V to 5.5V, –40°C to +85°C S8= 8-Lead SOIC 1.8 = 1.8V to 3.6V AG = 1.8V to 3.6V, 0°C to +70°C AH = 1.8V to 3.6V, –40°C to +85°C