X24320V14I-1.8

X24320 XICOR | Alldatasheet

Document overview

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Technical content

Ó Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice 7035-1.2 4/25/97 T0/C2/D0 SH X24320 FUNCTIONAL DIAGRAM

FEATURES

Save Critical Data with Programmable Block Lock Protection —Block Lock (0, 1/4, 1/2, or all of E PROM Array) —Software Write Protection —Programmable Hardware Write Protect In Circuit Programmable ROM Mode 400KHz 2-Wire Serial Interface —Schmitt Trigger Input Noise Suppression —Output Slope Control for Ground Bounce Noise Elimination Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Write Current Less Than 3mA —Standby Current Less Than 1 m A Power Supply Versions

32 Word Page Write Mode

—Minimizes Total Write Time Per Word Internally Organized 4K x 8 Bidirectional Data Transfer Protocol Self-Timed Write Cycle —Typical Write Cycle Time of 5ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8-Lead SOIC 14-Lead TSSOP 8-Lead PDIP

DESCRIPTION

The X24320 is a CMOS Serial E PROM, internally organized 4K x 8. The device features a serial inter- face and software protocol allowing operation on a simple two wire bus. The bus operates at 400 KHz all the way down to 1.8V. Three device select inputs (S ) allow up to eight devices to share a common two wire bus. A Write Protect Register at the highest address loca- tion, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the device until the WEL bit in the Write Protect Register is set. The Block Lock Protection feature gives the user four array block protect options, set by programming two bits in the Write Protect Register. The Programmable Hardware Write Protect feature allows the user to install the device with WP tied to V CC , write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are permanently protected from being erased. SERIAL E2PROM DATA AND ADDRESS (SDA) SCL WP COMMAND DECODE AND CONTROL LOGIC BLOCK LOCK AND WRITE PROTECT CONTROL LOGIC DEVICE SELECT LOGIC WRITE PROTECT REGISTER PAGE DECODE LOGIC DATA REGISTER Y DECODE LOGIC 1K x 8 1K x 8 2K x 8 WRITE VOLTAGE CONTROL SERIAL E 2PROM ARRAY 4K x 8

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PR OMs are designed and tested for applica- tions requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SD A is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and ma y be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S , S , S The device select inputs (S , S , S ) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appro- priate. If actively driven, they m ust be driven with CMOS levels (driven to V CC or V SS Write Protect (WP) The Wr ite Protect input controls the Hardware Wr ite Protect feature. When held LO W , Hardware Wr ite Protection is disabled. When this input is held HIGH, and the WPEN bit in the Wr ite Protect Register is set HIGH, the Wr ite Protect Register is protected, preventing changes to the Block Lock Protection and WPEN bits. PIN NAMES

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S , S , S Device Select Inputs SDA Serial Data SCL Serial Clock WP Write Protect V SS Ground V CC Supply Voltage NC No Connect VCC WP SCL SD A VSS X24320 8-Lead DIP/SOIC

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• .244” .252” * .197” .200” Not to scale X24320 * SOIC Measurement 14-Lead TSSOP

Figure 3. Acknowledge Response From Receiver after the transmitting device has released the bus. that it received the eight bits of data. Refer to Figure 3. after the receipt of each subsequent 8-bit word. place the device into a known state.

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Figure 4. Device Addressing

1 S1 S0 R /W

0 A10 A9 A80

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and the device returns to the standby mode. Address Bytes as shown in figure 4. Address Byte 0. See figure 4.

Figure 6. Page Write Sequence can write 32 words to the page beginning at any byte. by the new data, one byte at a time. address, acknowledge, and data transfer sequence.

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Figure 5. Byte Write Sequence

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with the read or write operation. Refer to figure 7 .

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Random Reads , and Sequential Reads. over” to the first address on the same page. the ninth clock cycle and then issue a stop condition.

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Figure 7. Acknowledge Polling Sequence Figure 8. Current Address Read Sequence

master must first perform a “Dumm y” write operation. an acknowledge and then issuing a stop condition. address counter, but no data is output by the device. from the newly loaded address.

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Figure 9. Random Read Sequence Figure 10. Sequential Read Sequence

WRITE PROTECT REGISTER (WPR) Writing to the Write Protect Register The Wr ite Protect Register can only be modified by performing a “Byte Wr ite” operation directly to the address FFFFh as described below. The Data Byte must contain zeroes where indicated in the procedural descriptions below; otherwise the oper- ation will not be performed. Only one Data Byte is allow ed for each register write operation. The part will not acknowledge any data bytes after the first byte is entered. The user then has to issue a stop to initiate the nonvolatile write cycle that writes BL0, BL1, and WPEN to the nonvolatile bits. A stop must also be issued after volatile register write operations to put the device into Standby. The state of the Wr ite Protect Register can be read by performing a random byte read at FFFFh at any time. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the protocol, but a stop is not required to end this operation. After the read, the address counter contains 0000h. Write Protect Register: WPR (ADDR = FFFF h WEL: Write Enable Latch (Volatile) 0 = Wr ite Enable Latch reset, writes disabled. 1 = Wr ite Enable Latch set, writes enabled. RWEL: Register Write Enable Latch (Volatile) 0 = Register Wr ite Enable Latch reset, writes to the Wr ite Protect Register disabled. 1 = Register Wr ite Enable Latch set, writes to the Wr ite Protect Register enabled. BL0, BL1: Block Lock Protect Bits (Nonvolatile) The Block Lock Protect Bits, BL0 and BL1, determine which blocks of the array are protected. A write to a protected block of memory is ignored, but will receive an acknowledge. The master must issue a stop to put the part into standby, just as it would for a valid write; but the stop will not initiate an internal nonvolatile write cycle. See figure 11. WPEN: Write Protect Enable Bit (Nonvolatile) The Wr ite Protect (WP ) pin and the Wr ite Protect Enable (WPEN) bit in the Wr ite Protect Register control the Programmab le Hardware Wr ite Protection feature. Hardware Wr ite Protection is enabled when the WP pin is HIGH and the WPEN bit is HIGH, and disabled when either the WP pin is LOW or the WPEN bit is LOW . Figure 12 defines the write protect status for each combination of WPEN and WP . When the chip is Hardware Wr ite Protected, nonvolatile writes are disabled to the Wr ite Protect Register, including the Block Lock Protect bits and the WPEN bit itself, as w ell as to the Block Lock protected sections in the memor y array. Only the sections of the memory array that are not Block Lock protected, and the volatile bits WEL and RWEL, can be written. In Circuit Programmable ROM Mode Note that when the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH. Thus an In Circuit Programmab le ROM function can be implemented by hardwiring the WP pin to V CC writing to and Block Locking the desired portion of the array to be ROM, and then programming the WPEN bit HIGH. Unused Bit Positions Bits 0, 5 & 6 are not used. All writes to the WPR m ust have zeros in these bit positions. The data byte output during a WPR read will contain zeros in these bits. Writing to the WEL and RWEL bits WEL and R WEL are volatile latches that pow er up in the LOW (disabled) state. While the WEL bit is LOW , writes to any address other than FFFFh will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing 00000010 to address FFFFh. Once set, WEL remains HIGH until either it is reset to 0 (by writing 00000000 to FFFFh) or until the part pow ers up again. Wr ites to WEL and R WEL do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. The RWEL bit controls writes to the Block Lock Protect bits, BL0 and BL1, and the WPEN bit. If RWEL is 0 then no writes can be performed on BL0, BL1, or WPEN. RWEL is reset when the device pow ers up or after any nonvolatile write, including writes to the Block Lock Protect bits, WPEN bit, or any bytes in the memor y array. When R WEL is set, WEL cannot be 7 6 5 4 3 2 1 0 WPEN 0 0 BL1 BL0 RWEL WEL 0

address FFFFh, where u=WPEN, x=BL1, and y=BL0. issues the stop condition in step 3. put the device into standby mode. Figure 11. Block Lock Protect Bits and Protected Addresses

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Figure 12. WP Pin and WPEN Bit Functionality

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0 X Wr itable Protected Unprotected Unprotected

D.C. OPERATING CHARACTERISTICS

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CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

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Notes:(1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA SCL = VCC X 0.1/VCC X 0.9 Levels @ 400KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3VICC2 VCC Supply Current (Write) 3 mA ISB1 (1) VCC Standby Current 5 mA SCL = SDA = VCC , All Other Inputs = VSS or VCC – 0.3V, VCC = 5V – 10% ISB2 (1) VCC Standby Current 1 mA SCL = SDA = VCC , All Other Inputs = VSS or VCC – 0.3V, VCC = 2.5V ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (2) Input LOW Voltage –0.5 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 3mA Vhys (3) Hysteresis of Schmitt Trigger Inputs VCC x 0.05 V Symbol Parameter Max. Units Test Conditions C I/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V C IN (3) Input Capacitance (S0, S1, S2, SCL, WP) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS

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Temperature Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C

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X24320 4.5V to 5.5V X24320–2.5 2.5V to 5.5V X24320–1.8 1.8V to 3.6V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability.

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits

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POWER-UP TIMING (4)

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Notes:(4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 400 KHz tI Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 ms tBUF Time the Bus Must Be Free Before a New Transmission Can Start 1.2 ms tHD:STA Start Condition Hold Time 0.6 ms tLOW Clock LOW Period 1.2 ms tHIGH Clock HIGH Period 0.6 ms tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 ms tHD:DAT Data In Hold Time 0 ms tSU:DAT Data In Setup Time 100 ns tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 ms tDH Data Out Hold Time 50 300 ns tOF Output Fall Time 20+0.1Cb (5) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms A.C. CONDITIONS OF TEST

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Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT 1.53KW 100pF OUTPUT

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Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

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The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24320 bus interface circuits are disabled, SDA is allow ed to remain HIGH, and the device does not respond to its slave address. Bus Timing tSU:STA tHD:STA tHD:D AT tSU:D AT tLOW tSU:STO tR tBUF SCL SD A IN SD A OUT tDHtAA tF tHIGH

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Symbol Parameter Min. Typ.(5) Max. Units tWC (6) Write Cycle Time 5 10 ms SCL SD A 8th BIT W ORD n ACK tWC ST OP CONDITION STAR T CONDITION 7035 FM 15 Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 120 100 20 40 60 80 100 120 RESISTANCE (K W ) BUS CAPACITANCE (pF) MIN. RESIST ANCE MAX. RESIST ANCE R MAX = C BUS tR R MIN = IOL MIN V CC MAX =1.8KW

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Notes:(5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

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NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)

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NO TE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEA TING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP .0.010 (0.25) 15° 8-LEAD PLASTIC DU AL IN-LINE PA CKA GE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

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ORDERING INFORMATION

Blank = 5V –10% 2.5 = 2.5V to 5.5V Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C Package X24320 Blank = 8-Lead SOIC Blank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C AE = 2.5V to 5.5V, 0°C to +70°C AF = 2.5V to 5.5V, –40°C to +85°C X24320 X X LIMITED W ARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. mak es no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. S8 = 8-Lead SOIC 1.8 = 1.8V to 3.6V AG = 1.8V to 3.6V, 0°C to +70°C AH = 1.8V to 3.6V, –40°C to +85°C V14 = 14-Lead TSSOP V = 14-Lead TSSOP P = 8-Lead PDIP P = 8-Lead PDIP