X24257

X24257 XICOR | Alldatasheet

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REV 1.1.1 10/15/00 Characteristics subject to change without notice. 1 of 19 www.xicor.com Preliminary Information 256K X24257 32K x 8 Bit 400kHz 2-Wire Serial EEPROM with Block Lock

FEATURES

• S ave critical data with programmable block lock protection — Block lock (first page, first 2 pages, first 4 pages, first 8 pages, 1/4, 1/2, or all of EEPROM array) — Software write protection —P rogrammable hardware write protect
• In circuit programmable ROM mode
• 400kHz 2-wire serial interface —S chmitt trigger input noise suppression — Output slope control for ground bounce noise elimination
• Longer battery life with lower power — Active read current less than 1µA — Active write current less than 3µA — Standby current less than 1µA
• 2.5V to 5.5V power supply
• 64-byte page write mode — Minimizes total write time per word
• Internally organized 32K x 8
• Bidirectional data transfer protocol
• Self-timed write cycle —T ypical write cycle time of 5ms
• High reliability — Endurance: 100,000 cycles — Data retention: 100 years
• 8-lead XBGA, 8-lead SOIC, 14-lead TSSOP

DESCRIPTION

The X24257 is a CMOS Serial EEPROM, internally organized 32K x 8. The device features a serial inter- face and software protocol allowing operation on a simple two wire bus. Three device select inputs (S ) allow up to four devices to share a common two wire bus. A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the device until the WEL bit in the Write Protect Register is set. The Block Lock Protection feature gives the user eight array block protect options, set by programming three bits in the Write Protect Register. The Programmable Hardware Write Protect feature allows the user to install the device with WP tied to V CC , write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are protected from being erased if WP is high. Xicor EEPROMs are designed and tested for applica- tions requiring extended endurance. Inherent data retention is greater than 100 years. BLOCK DIAGRAM Serial EEPROM Data and Address (SDA) SCL WP Command Decode and Control Logic Block Lock and Write Protect Control Logic Device Select Logic Write Protect Register Page Decode Logic Data Register Y Decode Logic Write Voltage Control Serial EEPROM Array 32K X 8

X24257 – Preliminary Information Characteristics subject to change without notice. 2 of 19REV 1.1.1 10/15/00 www.xicor.com PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open col- lector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S , S The device select inputs (S , S ) are used to set bits in the slave address. This allows up to four devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appropriate. If actively driven, they must be driven with CMOS levels (driven to V CC or V SS ) and they must be constant between each start and stop issued on the SDA bus. These pins have an active pull down internally and will be sensed as low if the pin is left unconnected. Write Protect (WP) WP must be constant between each start and stop issued on the SDA bus and is always active (not gated). The WP pin has an active pull down to disable the write protection when the input is left floating. The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock Protection and WPEN bits. PIN NAMES PIN CONFIGURATION Symbol Description S , S Device Select Inputs SDA Serial Data SCL Serial Clock WP Write Protect V SS Ground V CC Supply Voltage NC No Connect 8-Lead PDIP/SOIC VCC WP SCL X24257 SDA5 14-Lead TSSOP VCC WP SCL NC X24257 VSS SDA NC NC NC NC NC SDA S2SCL VCC VSS WP 8 8-Lead XBGA: Top View VSS

Characteristics subject to change without notice. Figure 3. Acknowledge Response From Receiver the device returns to the standby mode. first read or write operation must supply an address. Address Bytes as shown in Figure 4. Address Byte 0. See Figure 4. Figure 4. Device Addressing

1 S1 S0 R/W

Characteristics subject to change without notice. is at high impedance. See Figure 5. The device is capable of a 64 byte page write operation. mented by one. The page address remains constant. edge, and data transfer sequence. Figure 5. Byte Write Sequence Figure 6. Page Write Sequence

0 S1S0

Characteristics subject to change without notice. with the read or write operation. Refer to Figure 7. Figure 7. Acknowledge Polling Sequence

dom Reads, and Sequential Reads. over” to the first address on the same page. address, acknowledge, and data transfer sequence. the ninth clock cycle and then issue a stop condition. Figure 8. Current Address Read Sequence master must first perform a “Dummy” write operation. counter, but no data is output by the device. from the newly loaded address. acknowledge and then issuing a stop condition. acknowledge and data transfer sequence.

Figure 9. Random Read Sequence Figure 10. Sequential Read Sequence trol Register is physically part of the array. counter contents are undefined. Table 1. Control Register tile latch that powers up in the LOW (disabled) state.

Table 2. Block Protect Bits Figure 11. Block Protection Configuration

2 Pages

4 Pages

8 Pages

enabled as long as the WP pin is held HIGH. Table 3. Write Protect Enable Bit and WP Pin Function ceeded by a start and ended with a stop). WPEN, BP2, BP1 and BP0 bits remain unchanged. and the RWEL bit remains set.

X24257 – Preliminary Information ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V Lead temperature COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70°C Industrial –40 °C +85°C Supply Voltage Limits X24257–2.5 2.5V to 5.5V D.C. OPERATING CHARACTERISTICS VCC equals the range indicated for each device type, unless otherwise stated. Symbol Parameter VCC = 2.5 to 5.5V Unit Test ConditionsMin. Max. ICC1 Active Supply Current (Read) 1m A V IL = VCC X 0.1 VIH = VCC X 0.9 fSCL = 400kHz SDA = Open ICC2 Active Supply Current (Write) 3m A ISB1 (2) Standby Current AC 1 mA V IL = VCC X 0.1 VIH = VCC X 0.9 fSCL = 400kHz SDA = Open VSB Standby Voltage (Test) V CC– 0.2 V ISB2 (2) Standby Current DC 1 mA V SDA = VSCL = VSB, Others = GND or VSB ILI Input Leakage Current 10 mA V IN = GND to VCC ILO Output Leakage Current 10 mA V SDA = GND to VCC Device is in Standby(2) VlL (3) Input LOW Voltage –0.5 V CC x 0.3 V VIH (3) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed input level 0.2 V V CC related level V CC x 0.05 V VOL Output LOW Voltage 0.4 V I OL = 3mA

X24257 – Preliminary Information CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. Symbol Parameter Max. Unit Test Conditions CI/O (3) Input/Output Capacitance (SDA) 8 pF V I/O = 0V CIN (3) Input Capacitance (S0, S1, S2, SCL, WP) 6 pF V IN = 0V A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC X 0.5 Output load Standard output load 1.53KΩ 100pF Output for VOL = 0.4V IOL = 3mA A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol Parameter VCC 2.5V UnitMin. Max. fSCL SCL clock frequency 0 400 kHz tIN Pulse width suppression time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW period 1.3 µs tHIGH Clock HIGH period 0.6 µs tSU:STA Start condition setup time 0.6 µs tHD:STA Start condition hold time 0.6 µs tSU:DAT Data in setup time 100 ns tHD:DAT Data in hold time 0 µs tSU:STO Stop condition setup time 0.6 µs tDH Data output hold time 50 ns tR SDA and SCL rise time 20 + .1Cb (3) 300 ns tF SDA and SCL fall time 20 + .1Cb (3) 300 ns tSU:S0, S1, S2, WP S0, S1, S2, and WP Setup Time 0.6 ns tHD:S0, S1, S2, WP S0, S1, S2, and WP Hold Time 0 ns Cb Capacitive load for each bus line 400 pF

X24257 – Preliminary Information POWER-UP TIMING(4) Notes: (4) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (5) Typical values are for TA = 25°C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF . Bus Timing S0, S1, S2, and WP Pin Timing Write Cycle Limits Notes: (6) t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24257 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Symbol Parameter Max. Unit tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms Symbol Parameter Min. Typ. Max. Unit TWC (6) Write Cycle Time — 5 10 ms tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH tSU: S0, S1, S2, WP SCL SDA IN S0, S1, S2, and WP Slave Address Byte Clk 1 Clk 9 tHD: S0, S1, S2, WP

X24257 – Preliminary Information Write Cycle Timing SCL SDA 8th Bit Word n ACK tWC Stop Condition Start Condition Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE 120 100 20 40 60 80 100 120 Resistance (KΩ) Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX = CBUS tR RMIN = IOL Min VCC Max. WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

X24257 – Preliminary Information PACKAGING INFORMATION 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (.508) 0.012 (.305) .080 (2.03) .070 (1.78) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) .212 (5.38) .203 (5.16) .035 (.889) .020 (.508) .010 (.254) .007 (.178) 0°–8° Ref. Pin 1 ID .050 (1.27) BSC 8-Lead Plastic, EIAJ SOIC, Package Code A8 .013 (.330) .004 (.102) NOTES:

X24257 – Preliminary Information PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic, SOIC, Package Code S8 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X24257 – Preliminary Information PACKAGING INFORMATION ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch) ALL DIMENSIONS ARE TYPICAL VALUES X24257: Bottom View 8-Lead XBGA: Top View SDA NCSCL VCC VSS WP 8 .137” .079” 8-Lead XBGA Complete Part Number Top Mark X24257Z-2.5 XACG X24257ZI-2.5 XACH F D C VSS NC WP VCC SDA SCL PIN 1 8-Lead XBGA X24257B-2.5 XACG X24257BI-2.5 XACH E C e A DWG Symbol 8L XBGA A Contact Factory A1 Contact Factory C Contact Factory D Contact Factory E Contact Factory e Contact Factory F Contact Factory D

X24257 – Preliminary Information PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X24257 – Preliminary Information ©Xicor, Inc. 2001 Patents PendingLIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Ordering Information

2.5 = 2.5V to 5.5V Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C Package X24257 S8 = 8-Lead SOIC, 150 mil wide, JEDEC V14 = 14-Lead TSSOP Z = 8-Lead XBGA A8 = 8-Lead SOIC, 200 mil wide, EIAJ B = 8-Lead XBGA S8 = 8-Lead SOIC (JEDEC) J = 2.5V to 5.5V, 0°C to +70°C K = 2.5V to 5.5V, –40°C to +85°C X24257 X X V14 = 14-Lead TSSOP Complete Part Number Top Mark X24257ZI - 2.5 XACH Lead TSSOP/SOIC X24257Z - 2.5 XACG X24257BI - 2.5 XACH X24257B - 2.5 XACG A8 = 8-Lead SOIC (EIAJ)