X24042 XICOR | Alldatasheet
Document overview
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Technical content
1© Xicor, 1991 Patents Pending Characteristics subject to change without notice Serial E2PROM TYPICAL FEATURES
- 2.7V to 5.5V Power Supply
- Low Power CMOS —Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA —Standby Current Less Than 50 µA
- Internally Organized 512 x 8
- 2 Wire Serial Interface —Bidirectional Data Transfer Protocol
- Sixteen Byte Page Write Mode —Minimizes Total Write Time Per Byte
- Self Timed Write Cycle —Typical Write Cycle Time of 5 ms
- High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years
- 8 Pin Mini-DlP and 8 Pin SOIC Packages
DESCRIPTION
The X24042 is a CMOS 4,096 bit serial E2PROM, internally organized 512 x 8. The X24042 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24042 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. The X24042 utilizes Xicor’s proprietary Direct Write TM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. 4K X24042 512 x 8 Bit
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+COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC D OUT ACK E2PROM
32 X 128
(8) VCC R/W PIN (4) VSS (5) SDA (6) SCL (3) A2 (2) A1 (1) A0 D OUT LOAD INC CK 3849-1
PIN CONFIGURATIONPIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address (A A0 is unused by the X24042, however, it must be tied to VSS to insure proper device operation. Address (A1, A2) The Address inputs are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to V SS or VCC as appropriate. If driven they must be driven to VSS or to VCC . PIN NAMES Symbol Description A0–A2 Address Inputs SDA Serial Data SCL Serial Clock NC No Connect VSS Ground VCC Supply Voltage
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the clock for both transmit and receive operations. any command until this condition has been met. Figure 1. Data Validity
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Figure 2. Definition of Start and Stop
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to acknowledge that it received the eight bits of data. after the receipt of each subsequent eight bit word. place the device into a known state. Figure 3. Acknowledge Response From Receiver
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defined by the state of the A1 and A2 input. access to the whole 512 x 8 array. Figure 4. Slave Address selected, when set to zero a write operation is selected.
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Figure 5. Byte Write
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order eight bits of the word address remain constant. address, acknowledge and data transfer sequence. operation the X24042 initiates the internal write cycle. read or write operation. Refer to Flow 1.
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Figure 6. Page Write
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clock cycle and then issue a stop condition. issues an acknowledge and transmits the eight bit word. acknowledge and data transfer. with an acknowledge and by issuing a stop condition. Figure 7. Current Address Read
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Figure 8. Random Read
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with an acknowledge and by issuing a stop condition. edge and data transfer sequence. Figure 9. Sequential Read
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Figure 10. Typical System Configuration
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*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Respect to V Lead Temperature RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C7 0 °C Industrial –40 °C +85 °C Military –55 °C +125 °C
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X24042 4.5V to 5.5V X24042-3 3.0V to 5.5V X24042-2.7 2.7V to 5.5V
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D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Supply Current (Read) 1 SCL = V CC x 0.1/VCC x 0.9 Levels lCC2 VCC Supply Current (Write) 3 mA @ 100 KHz, SDA = Open, All Other Inputs = GND or VCC – 0.3V ISB1 (1) VCC Standby Current 150 µA SCL = SDA = V CC – 0.3V, All Other Inputs = GND or VCC , VCC = 5.5V ISB2 (1) VCC Standby Current 50 µA SCL = SDA = V CC – 0.3V, All Other Inputs = GND or VCC , VCC = 3V ILI Input Leakage Current 10 µAV IN = GND to VCC ILO Output Leakage Current 10 µAV OUT = GND to VCC VlL(2) Input Low Voltage –1.0 V CC x 0.3 V VIH(2) Input High Voltage V CC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V I OL = 3 mA
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CAPACITANCE TA = 25°C, F = 1.0MHZ, VCC = 5V Symbol Test Max. Units Conditions C I/O(3) Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN(3) Input Capacitance (A0, A1, A2, SCL) 6 pF V IN = 0V
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Notes: (1) Must perform a stop command prior to measurement. (2) VIL min and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested.
Note: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These param- eters are periodically sampled and not 100% tested.
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tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH Bus Timing POWER-UP TIMING Symbol Parameter Max. Units tPUR (4) Power-Up to Read Operation 1 ms tPUW (4) Power-Up to Write Operation 5 ms
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A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified). READ & WRITE CYCLE LIMITS Symbol Parameter Min. Max. Units tSCL SCL Clock Frequency 0 100 KHz tI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free Before a 4.7 µs New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH Clock High Period 4.0 µs tSU:STA Start Condition Setup Time 4.7 µs tHD:DAT Data In Hold Time 0 µs tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 µs tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns
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A.C. CONDITIONS OF TEST Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns I/O Timing Levels V CC x 0.5
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EQUIVALENT A.C. LOAD CIRCUIT 5.0V 1533Ω 100pF Output
Symbol Parameter Min. Typ. (5) Max. Units tWR (6) Write Cycle Time 5 10 ms
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The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24042 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation. Write Cycle Timing Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE
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RESISTANCE (K Ω ) BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE R MAX =C BUS tR MAX R MIN = IOL MIN VCC MAX =1.8KΩ Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance OUTPUTSINPUTSWAVEFORM
0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.140 (3.56) 0.130 (3.30) 0.020 (0.51) 0.015 (0.38) PIN 1 SEATING PLANE 0.062 (1.57) 0.058 (1.47) 0.255 (6.47) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.092 (2.34) DIA. NOM. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. PACKAGING INFORMATION
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.41) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)
ORDERING INFORMATION
Blank = 4.5V to 5.5V 3 = 3.0 to 5.5V 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC Part Mark Convention Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S = 8-Lead SOIC Blank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C D = 3.0V to 5.5V, 0°C to +70°C E = 3.0V to 5.5V, –40°C to +85°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. X24042 X X