X24001 XICOR | Alldatasheet

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Technical content

128 Bit X24001 16 x 8 Bit

Identi™ PROM © Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice 3830-1.5 6/10/96 T2/C1/D0 NS

FEATURES

  • 2.7V to 5.5V Power Supply
  • 128 Bit Serial E2PROM
  • Low Power CMOS —Active Current Less Than 1mA —Standby Current Less Than 50 µA
  • Internally Organized 16 x 8
  • 2 Wire Serial Interface
  • High Voltage Programmable Only PGM , 12V to 15V
  • Push/Pull Output
  • High Reliability —Data Retention: 100 Years
  • Available Packages —8-Lead MSOP —8-Lead PDIP —8-Lead SOIC

DESCRIPTION

The X24001 is a CMOS 128 bit serial E2PROM, inter- nally organized as 16 x 8. The X24001 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24001 is ideally suited for identification applica- tions such as serial numbers or device revision numbers which need to be stored and retrieved electronically. V PGM is used to enable writes to the device. This provides full protection of the data in the user’s environ- ment where V PGM is not available. Xicor E2PROMs are designed and tested for applica- tions requiring extended endurance. Inherent data re- tention is greater than 100 years. The X24001 is fabricated with Xicor’s Advanced CMOS Floating Gate technology. IDENTI™ PROM is a trademark of Xicor, Inc. FUNCTIONAL DIAGRAM CONTROL LOGIC INPUT/ OUTPUT BUFFER SCL SDA COMMAND/ADDRESS REGISTER SHIFT REGISTER MEMORY ARRAY

3830 FHD F01

3830 FHD F02.1 NC NC NC VSS X24001 MSOP/DIP/SOIC

Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is a push/pull output and does not require the use of a pull-up resistor. During the program- ming operation, SDA is an input. PIN NAMES Symbol Description NC No Connect VSS Ground VCC Supply Voltage SDA Serial Data SCL Serial Clock

3830 PGM T01

The X24001 supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. There- fore, the X24001 will be considered a slave in all appli- cations. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are re- served for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24001 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. A start may be issued to terminate the input of a control word or the input of data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are also inhibited while a write is in progress. Stop Condition The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is used to reset the device during a command or data input sequence and will leave the device in the standby mode. As with starts, stops are inhibited when outputting data and while a write is in progress.

Figure 1. Data Validity

3830 FHD F03

Figure 2. Definition of Start and Stop Conditions

3830 FHD F04

lowed by the 8-bit data byte. Figure 3. Programming Sequence

The byte read operation is initiated with a start condition. and transfer data into the shift register from the array. outputting data (Figures 4 and 5).

3830 FHD F07

Figure 4. Read Sequence

3830 FHD F06

Figure 5. Read Cycle Timing

*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions C I/O(2) Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN(2) Input Capacitance (SCL) 6 pF V IN = 0V 3830 PGM T05.1 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. ABSOLUTE MAXIMUM RATINGS* Temperature under Bias Voltage on any Pin with Respect to V Voltage on SCL with Lead Temperature D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Supply Current Read 1 mA SCL = V CC x 0.1/VCC x 0.9 Levels @ 1MHz, SDA = Open ISB1 VCC Standby Current 100 µA SCL = SDA = V CC VCC = 5V ±10% ISB2 VCC Standby Current 50 µA SCL = SDA = V CC VCC = 3V ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VlL(1) Input LOW Voltage –1.0 V CC x 0.3 V VIH(1) Input HIGH Voltage V CC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 2.1mA VOH Output HIGH Voltage V CC – 0.8 V I OH = 1mA VPGM Program Enable Voltage 12 15 V 3830 PGM T04.3 Supply Voltage Limits X24001 5V ±10% X24001-3 3V to 5.5V X24001-2.7 2.7V to 5.5V 3830 PGM T03.1 RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 3830 PGM T02.1

Symbol Parameter Max. Units tPUR (3) Power-up to Read Operation 2 ms tPUW (3) Power-up to Write Operation 5 ms

3830 PGM T06

A.C. CONDITIONS OF TEST Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels V CC x 0.5 3830 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 1 MHz tAA SCL LOW to SDA Data Out Valid 350 ns tBUF Time the Bus Must Be Free Before a 500 ns New Transmission Can Start tHD:STA Start Condition Hold Time 250 ns tLOW Clock LOW Period 500 ns tHIGH Clock HIGH Period 500 ns tSU:STA Start Condition Setup Time 250 ns tHD:DAT Data In Hold Time 0 µs tSU:DAT Data in Setup Time 250 ns tR SDA and SCL Rise Time 1 µs tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 250 ns tDH Data Out Hold Time 50 ns 3830 PGM T08.1 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read & Write Cycle Limits 3830 FHD F08.2 2.16KΩ 100pF OUTPUT 3.07KΩ

tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDHtAA tF tHIGH

3830 FHD F09

Symbol Parameter Min. Max. Units tWR (4) Write Cycle Time 5 ms

3830 PGM T09

Note: (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24001 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start conditions. 3830 ILL F10.1 SDA tWR SCL START CONDTION X24001 ADDRESS

0.118 – 0.002 (3.00 – 0.05) 0.040 – 0.002 (1.02 – 0.05) 0.150 (3.81) REF. 0.193 (4.90) REF. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7° TYP R 0.014 (0.36) 0.118 – 0.002 (3.00 – 0.05) 8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3926 ILL F49

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62) PACKAGING INFORMATION

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. X24001 X X Blank = 8-Lead SOIC P = 8-Lead Plastic DIP Blank = 5V ±10%, 0°C to +70°C D = 3V to 5.5V, 0°C to +70°C E = 3V to 5.5V, –40°C to +85°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C

ORDERING INFORMATION

Blank = 5V ±10% 3 = 3V to 5.5V 2.7 = 2.7V to 5.5V Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C M = –55°C to +125°C Package M = 8-Lead MSOP P = 8-Lead Plastic DIP S = 8-Lead SOIC Part Mark Convention

X24001 PROGRAMMING ORDER INFORMATION Address Data Pattern MSB First 67 543210 A B C D E F Matrix A Address Data Pattern MSB First 67 543210 A B C D E F Matrix B Static Pattern Fill in matrix A below Incrementing Pattern Indicate in Matix A any static pattern and indicate in Matrix B beginning sequence value to be incremented. Totally Random Pattern AUTHORIZATION Programming Information Supplied By Print or Type Clearly Full Name Title Signature Date