X2212

X2212 XICOR | Alldatasheet

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Commercial X2212 " 4 B 1k Industrial X22121 256 x 4 Bit SE Nonvoiatile Static RAM 1 | ee FEATURES in all Xicor 5V nonvolatile memories. The X2212 fea- © Single 5V Supply tures the JEDEC approved pinout for 4-bit-wide memo- © Fully TTL Compatible ries, compatible with industry standard RAMs. ¢ Infinite E2PROM Array Recall, RAM Read The NOVRAM design allows data to be easily trans- and Write Cycles ferred from RAM to E2PROM (store) and from © Access Time of 300 ns Max. E2PROM to RAM (recall). The store operation is com- © Nonvolatile Store Inhibit: Veg = 3V Typical pleted in 10 ms or less and the recall is typically com- © High Reliability Pleted in 1 ps. —Store Cycles: 100,000 Xicor NOVRAMSs are designed for unlimited write oper- —Data Retention: 100 Years ations to RAM, either from the host or recalls from JEDEC Standard 18-Pin Package E2PROM. The E2PROM array is designed for a mini- mum 100,000 store cycles and inherent data retention DESCRIPTION is specified to be greater than 100 years. Refer to The Xicor X2212 is a 256 x 4 NOVRAM featuring a RR.520 and RA-515 for details on Xicor nonvolatile high-speed static RAM overlaid bit-for-bit with anonvol- memory endurance and data retention characteristics. atile E2PROM. The X2212 is fabricated with the same reliable N-channel floating gate MOS technology used eS PIN CONFIGURATION FUNCTIONAL DIAGRAM dq h een ” Me senor | a. “ — [AH srone ad wo. ” | 1 | ie Fives — Hope a Fo, rs —| lea sore] ae ecm ea |} 2“ St soem, JL 0058-1 t— “ Hy [4 H $ PIN NAMES oy re aie || ea Ao-A7 Address Inputs Wo. aite@ } q 1/04-1/04 Data Inputs/Outputs (L [<4 We Write Enable ————P cs Chip Select a es STORE Store we D Voc +5V 0058-2 Vss Ground NC No Connect SSSSSSSSSSSSsSssSSssSssSsssssssSe 1-25

X2212, X22121 ABSOLUTE MAXIMUM RATINGS" *COMMENT Temperature Under Bias Stresses above those listed under “Absolute Maximum Rat- X2212 eee eee eee ee [10°C to + 85°C ings" may cause permanent Gamage to the device. This is a K2212 eee cece cece cece sees 65°C to +135°C stress rating only and the functi ‘operation of the device at Voltage on ane, Pin with erational sections of this specification is not implied. Exposure DC. Output Current 22220000 .5mA may affect device reliability. Lead Temperature D.C. OPERATING CHARACTERISTICS X2212 Ta = 0°C to +70°C, Voc = +5V +10%, unless otherwise specified. X22121 Ta = —40°C to +85°C, Voc = +5V + 10%, unless otherwise specified. lec Power Supply Current 70 mA | All Inputs = Voc vo = OmA Inputtoadurent || 10 | | 0 | A Vin = GND to Voc OutputLeakage Curent | | 10 | | 10 nA_| Vour = GND t0 Voc InputtowVotage | -10[ 08 | -10] o8 [| v | | Inputigh Voltage | 20 | Voc+10| 20 |vec+to] v | | OutputlowVotage | | oa || oe Tv | = 42ma | ENDURANCE AND DATA RETENTION |__Parameter | in. | Units 10,000 | DataChanges Per Bit | _Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RA-504 |_DataRetention | 100 | Years | _Xicor Reliability Report AA-515 CAPACITANCE Ta = 25°C, f = 1.0 MHz, Voc = 5V symbol | Test, | Max. | Units | Conditions | Input/Output Capacitance | 8 | | Wo =v Lewy | tnputcapacitance | |r Tv Notes: (1) This parameter is periodically sampled and not 100% tested. (2) Vi. min. and Vijq max. are for reference only and are not tested. 1-26

X2212, X22121 ee A.C. CONDITIONS OF TEST MODE SELECTION [inputs [input utp Fat Times [Hix |W |W [ouatin2 [no Sees lo Load 1 TTL Gate and fee | ouattanz A.C. CHARACTERISTICS X2212 Ta = 0°C to +70°C, Veg = +5V +10%, unless otherwise specified. X22121 Ta = —40°C to +85°C, Voc = +5V +10%, unless otherwise specified. Read Cycle Limits Pg pccesotine ans | Read Cycle ADDRESS CD cs —— isd DATAI/O ROOOOK bata van O>XX XX we ‘Notes: (3) Chip is deselected but may be automatically completing a store cycle. (4) STORE = L is required only to initiate the store cycle, after which the store cycle will be automatically completed (STORE = x), (5) tz min. and t}4z min. are periodically sampled and not 100% tested. ee 1-27

X2212, X2212I ——— Write Cycle Limits Write Cycie Time | soo fT ts Chip Select to End of Write ee [ret fittest tine ee Write Pulse Width piso Ps | eo ee | tow __|__ Data Vat to End of wate ee ee Data Hold Time mere | oT rs xerrai | 0 | Ts Write EnabletoOutputinHighZ | to | t00 | ns Ouiputaciivetromendotwrte | 0 Ts | Write Cycle ae ADDRESS CD a TE AZZA7 a — WE XN _ ™ DATA IN —, tee ow DATA OUT OOO Cee cose-4 1-28

X2212, X22121 Early Write Cycle ADDRESS Ce DATA IN XXKXKKXOOK DATA VALIO KX Mian z DATA OUT re _cweO cose Store Cycle Limits [re | Sete Store Cycle Sees STORE | Hl tosr DATA 1/0 rz 088-6 eee 1-29

X2212, X22121 Array Recall Cycle Limits Recall to Outputin High Z ps0 ns | Output Active from End of Recall pt fs Recalled Data Access TimetromEndot Recall | | 750 | ns Array Recall Cycle jp Fe. appress XXX XXXXKXNK ADDRESSES ALOK ARRAY RECALL + & | ta —>| trez tone DATAI/0 Higne cose- Note: (6) Array Recall rise time must be less than 1 us. 1-30

X2212, X22121 PIN DESCRIPTIONS AND DEVICE OPERATION WRITE PROTECTION Addresses (Ap-A7) The X2212 has three write protect features that are The address inputs select a 4-bit memory location dur- employed to protect the contents of the nonvolatile ing a read or write operation. memory. Chip Select (CS) * Voc Sense—All functions are inhibited when Vog is The Chip Select input must be LOW to enable read/ <3V, typically. operations wi RAM array. CS HIGH will ace the 70 pins the Mish we aray. oS wile Write Inhibit—Holding either STORE HIGH or a : ARRAY RECALL LOW during power-up or power- Write Enable (WE) down will prevent an inadvertent store operation The Write Enable input controls the I/O butters, deter- and E2PROM data integrity will be maintained. It mining whether a RAM read or write operation is en- should be noted; whichever method is employed, abled. WE HIGH enables a read and WE LOW enables all contro! inputs should be stable and the device a write. deselected prior to release of the controlling pro- tection signal. Data In/Data Out (1/04=1/04) fection signal Data is written to or read from the X2212 through the _® Noise Protection—A STORE pulse of less than 20 ns. W/O pins. The I/O pins are placed in the high imped- (typical) will not initiate a store cycle. ance state when either CS is HIGH or during either a store or recall operation. Data Changes STORE x2212 of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibit- X2212/5 | 0000 | s000 | ed during the store cycle. The store operation will be X22121/5 I in less. completed in 10 ms or less. xeate/s0 100,000 A store operation has priority over RAM read/write op- erations. it STORE is asserted during a read operation, SYMBOL TABLE the read will be discontinued. If STORE is asserted dur- ing a RAM write operation, the write will be immediately WAVEFORM INPUTS OUTPUTS terminated and the store performed. The data at the a Must be Will be RAM address that was being written will be unknown in _— steady steady both the RAM and E2PROM. May change Will change ARRAY RECALL DD from Low to from Low to The ARRAY RECALL input, when LOW, will initiate the High High transfer of the entire contents of the E2PROM array to May change Will change the RAM array. The transfer of data will typically be a ae rem High to fren High to completed in 1 us or less. ° Don't Care: Changing: An array recall has priority over RAM read/write opera- XXXXX Changes State Not tions and will terminate both operations when ARRAY. Allowed Known RECALL is asserted. ARRAY RECALL LOW will also Center Line inhibit the STORE input. »>«K N/A is High Impedance SSS 1-31

X2212, X22121 Normalized Active Supply Current Normalized Access Time vs. Ambient Temperature vs. Ambient Temperature 1s — 18 — Vee=5.0V f Yoo=5.0¥ 3% } a4“ g | 8 S10 £10 Fi 3 | § § = || o4 02 “ss “5 +125 *55 +25 +125 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) ones voto 1-32