X20C17 XICOR | Alldatasheet
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1©Xicor, Inc. 1992, 1995 Patents Pending Characteristics subject to change without notice 2015-2.5 8/1/97 T1/C0/D0 SH AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. High Speed AUTOSTORE™ NOVRAM
DESCRIPTION
The Xicor X20C17 is a 2K x 8 NOVRAM featuring a high- speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E 2PROM) and the AUTOSTORE feature which automatically saves the RAM contents to E 2PROM at power-down. The X20C17 is fabricated with advanced CMOS floating gate technol- ogy to achieve high speed with low power and wide power-supply margin. The X20C17 features a compat- ible JEDEC approved byte-wide memory pinout for industry standard SRAMs. The NOVRAM design allows data to be easily trans- ferred from RAM to E 2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 2.5ms or less. An automatic array recall operation reloads the contents of the E 2PROM into RAM upon power-up. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E 2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.
FEATURES
- 24-Pin Standard SRAM DIP Pinout
- Fast Access Time: 35ns, 45ns, 55ns
- High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum
- AUTOSTORE™ NOVRAM —Automatically Stores SRAM Data Into the E 2PROM Array When V CC Low Threshold is Detected —E 2PROM Data Automatically Recalled Into RAM Upon Power-up
- Low Power CMOS —Standby: 250 µA
- Infinite E2PROM Array Recall, and RAM Read and Write Cycles 16K X20C17 2K x 8 Bit PIN CONFIGURATION 2015 ILL F02.1 I/O0 I/O1 I/O2 VSS
1 VCC
Addresses (A0–A 10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE. Data In/Data Out (I/O 0–I/O7) Data is written to or read from the X20C17 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. FUNCTIONAL DIAGRAM 2015 FHD F01.1 PIN NAMES Symbol Description A0–A10 Address Inputs I/O0–I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground
2015 PGM T01
A3–A8 I/O0–I/O7 A0–A2 A9–A10 RECALL STORE
The CE, OE, and WE inputs control the X20C17 opera- tion. The X20C17 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW. A write operation requires CE and WE to be LOW. There is no limit to the number of read or write operations performed to the RAM portion of the X20C17. Memory Transfer Operations There are two memory transfer operations: a recall operation whereby the data stored in the E 2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E 2PROM array. Recall operations are performed automatically upon power-up. Store operations are performed automatically upon power-down. The store operation take a maximum of 2.5ms. Write Protection The X20C17 supports two methods of protecting the nonvolatile data. —If after power-up no RAM write operations have occured, no AUTOSTORE operation can be initiated. CC Sense – All functions are inhibited when VCC is ≤ 3V typical. SYMBOL TABLE The following symbol table provides a key to under- standing the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user’s application. WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Current (Active) 100 mA WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V Levels @ f = 20MHz, All I/Os = Open ICC2 (2) VCC Current During 2.5 mA All I/Os = Open AUTOSTORE ISB1 VCC Standby Current 10 mA All Inputs = V IH, All I/Os = Open (TTL Input) ISB2 VCC Standby Current 250 µA All Inputs = V CC – 0.3V (CMOS Input) All I/Os = Open ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC , CE = VIH VIL(1) Input LOW Voltage –1 0.8 V VIH(1) Input HIGH Voltage 2 V CC + 1 V VOL Output LOW Voltage 0.4 V I OL = 4mA VOH Output HIGH Voltage 2.4 V I OH = –4mA 2015 PGM T04.3 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 2015 PGM T02.1 Supply Voltage Limits X20C17 4.5V to 5.25V 2015 PGM T03.1 POWER-UP TIMING Symbol Parameter Max. Units tPUR (2) Power-Up to RAM Operation 100 µs tPUW (2) Power-Up to Nonvolatile Operation 5 ms
2015 PGM T05
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions C I/O(2) Input/Output Capacitance 10 pF V I/O = 0V C IN(2) Input Capacitance 6 pF V IN = 0V 2015 PGM T06.2
ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance 100,000 Data Changes Per Bit Store Cycles 1,000,000 Store Cycles Data Retention 100 Years 2015 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V 2015 PGM T08.1
2015 FHD F04
H X X Not Selected Output High Z Standby L H L Read RAM Output Data Active L L H Write “1” RAM Input Data High Active L L H Write “0” RAM Input Data Low Active L L L Not Allowed Output High Z Active L H H No Operation Output High Z Active
2015 PGM T09
893Ω 347Ω OUTPUT 30pF
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C17-35 -40°C to +85°C X20C17-45 X20C17-55 tRC Read Cycle Time 35 45 55 ns tCE Chip Enable Access Time 35 45 55 ns tAA Address Access Time 35 45 55 ns tOE Output Enable Access Time 20 25 30 ns tLZ(3) Chip Enable to Output in Low Z 0 0 0 ns tOLZ (3) Output Enable to Output in Low Z 0 0 0 ns tHZ (3) Chip Disable to Output in High Z 0 15 0 20 0 25 ns tOHZ (3) Output Disable to Output in High Z 0 15 0 20 0 25 ns tOH Output Hold From Address Change 0 0 0 ns
2015 PGM T10
2015 FHD F05
C L = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the Outputs are no longer driven. tCE tRC ADDRESS CE OE WE DATA VALID DATA VALID tOE tLZ tOLZ tOH tAA tHZ tOHZ DATA I/O tOE
X20C17-35 X20C17-45 X20C17-55 tWC Write Cycle Time 35 45 55 ns tCW Chip Enable to End of Write Input 30 35 40 ns tAS Address Setup Time 0 0 0 ns tWP Write Pulse Width 30 35 40 ns tWR Write Recovery Time 0 0 0 ns tDW Data Setup to End of Write 15 20 25 ns tDH Data Hold Time 3 3 3 ns tOEH OE High Hold Time 0 0 0 ns tOES OE High Setup Time 0 0 0 ns tOZ (4) Output Enable to Output in High Z 15 20 25 ns
2015 PGM T11
Note: (4) tOW , tOZ are periodically sampled and not 100% tested. 2015 FHD F06.1 tWC tCW tAS tOZ tWP tDW tDH tOEH tWR DATA VALID ADDRESS OE CE WE DATA OUT DATA IN
The AUTOSTORE feature automatically saves the con- tents of the X20C17’s static RAM to the on-board bit-for- bit shadow E 2PROM at power-down. This circuitry in- sures that no data is lost during accidental power-downs or general system crashes, and is ideal for microproces- sor caching systems, embedded software systems, and general system back-up memory. AUTOSTORE CYCLE LIMITS X20C17 Symbol Parameter Min. Max. Units tASTO (5) AUTOSTORE Cycle Time 2.5 ms VASTH AUTOSTORE Threshold Voltage 4.0 4.3 V VASEND (5) AUTOSTORE Cycle End Voltage 3.5 V
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VOLTS (V) TIME (ms) VASTH VASEND AUTOSTORE CYCLE IN PROGRESS tASTO STORE TIME AUTOSTORE CYCLE Timing Diagram and Suggested AUTOSTORE Implementation Circuit Note: (5) tASTO and VASEND are periodically sampled and not 100% tested. The X20C17 automatically initiates a nonvolatile store cycle whenever Vcc falls below the AUTOSTORE thresh- old voltage (V ASTH ). VCC must remain above the AUTOSTORE Cycle End Voltage (VASEND ) for the dura- tion of the store cycle (tASTO ). The detailed timing for this feature is illustrated in the AUTOSTORE timing dia- gram, below. Once the AUTOSTORE cycle is initiated, all other device functions are inhibited.
2015 FHD F14
2015 ILL F30.4 X20C17 V CC 22µF CCV
Normalized ICC by Temperature over the VCC Range and Frequency Normalized ICC by Temperature over Frequency 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0 2.0 ICC (NORMALIZED) FREQUENCY (MHz) 2015 FHD F33.2 -55°C +25°C +125°C 0.0 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0 2.0 ICC (NORMALIZED) FREQUENCY (MHz) 2015 FHD F31.1 VCC = 5.5V VCC = 5.0V VCC = 4.5V 0.0
3926 FHD F03
NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. P ACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) REF. PIN 1 INDEX 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.065 (1.65) 15° 24-LEAD PLASTIC DUAL IN-LINE P ACKAGE TYPE P TYP. 0.010 (0.25)
ORDERING INFORMATION
–35 = 35ns –45 = 45ns –55 = 55ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 24 Lead Plastic Dip Device LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.