X20C16SMB-35

X20C16 XICOR | Alldatasheet

Document overview

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Technical content

©Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice 3826-2.9 7/31/97 T4/C0/D0 SH AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. High Speed AUTOSTORE™ NOVRAM

DESCRIPTION

The Xicor X20C16 is a 2K x 8 NOVRAM featuring a high- speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E 2PROM) and the AUTOSTORE feature which automatically saves the RAM contents to E 2PROM at power-down. The X20C16 is fabricated with advanced CMOS floating gate technol- ogy to achieve high speed with low power and wide power-supply margin. The X20C16 features a compat- ible JEDEC approved pinout for byte-wide memories, for industry standard RAMs, ROMs, EPROMs, and E 2PROMs. The NOVRAM design allows data to be easily trans- ferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 10µs or less. An automatic array recall operation reloads the contents of the E 2PROM into RAM upon power-up. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E 2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.

FEATURES

• Fast Access Time: 35ns, 45ns, 55ns
• High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum
• AUTOSTORE™ NOVRAM —Automatically Stores RAM Data Into the E 2PROM Array When V CC Low Threshold is Detected —User Enabled Option —Open Drain AUTOSTORE Status Output Pin
• Power-on Recall 2PROM Data Automatically Recalled Into RAM Upon Power-up
• Software Data Protection —Locks Out Inadvertent Store Operations
• Low Power CMOS —Standby: 250 µA
• Infinite E2PROM Array Recall, and RAM Read and Write Cycles 16K X20C16 2K x 8 Bit PIN CONFIGURATION NE NC I/O0 I/O1 I/O2 VSS

1 VCC

(TOP VIEW) PLASTIC CERDIP LCC PLCC

3826 FHD F02

3826 FHD F15.1

3826 FHD F03

3826 ILL F17.2 NC OE AS WE VCC NE NC A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 X20C16 X20C16 N/C I/O0 I/O1 I/O2 VSS VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 NC NE V CC VCC WE AS NC A NC OE A PPLICA TION NOTE A V AILABLE AN56

A3–A8 I/O0–I/O7 AS A0–A2 A9–A10 RECALL STORE PIN DESCRIPTIONS Addresses (A0–A 10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O 0–I/O7) Data is written to or read from the X20C16 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. Nonvolatile Enable (NE) The Nonvolatile Enable input controls the recall function to the E 2PROM array. AUTOSTORE Output ( AS) AS is an open drain output which, when asserted indi- cates VCC has fallen below the AUTOSTORE threshold (VASTH ). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller. PIN NAMES Symbol Description A0–A10 Address Inputs I/O0–I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable NE Nonvolatile Enable AS AUTOSTORE Output VCC +5V VSS Ground NC No Connect

3826 PGM T01

3826 FHD F01

The CE, OE, WE, and NE inputs control the X20C16 operation. The X20C16 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C16. Memory Transfer Operations There are two memory transfer operations: a recall operation whereby the data stored in the E 2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E 2PROM array. Recall operations are performed automatically upon power-up and under host system control when NE, OE and CE are LOW and WE is HIGH. The recall operation takes a maximum of 5µs. SDP (Software Data Protection) There are two methods of initiating a store operation. The first is the software store command. This command takes the place of the hardware store employed on the X20C04. This command is issued by entering into the special command mode: NE, CE, and WE strobe LOW while at the same time a specific address and data combination is sent to the device. This is a three step operation: the first address/data combination is 555[H]/ AA[H]; the second combination is 2AA[H]/55[H]; and the final command combination is 555[H]/33[H]. This se- quence of pseudo write operations will immediately initiate a store operation. Refer to the software com- mand timing diagrams for details on set and hold times for the various signals. The second method of storing data is with the AUTOSTORE command. When enabled, data is auto- matically stored from the RAM into the E 2PROM array whenever VCC falls below the preset Autostore thresh- old. This feature is enabled by performing the first two steps for the software store with the command combina- tion being 555[H]/CC[H]. The AUTOSTORE feature is disabled by issuing the three step command sequence with the command com- bination being 555[H]/CD[H]. The AUTOSTORE feature will also be reset if V CC falls below the power-up reset threshold (approximately 3.5V) and is then raised back into the operation range. Write Protection The X20C16 supports two methods of protecting the nonvolatile data. —If after power-up the AUTOSTORE feature is not enabled, no AUTOSTORE can occur. CC Sense – All functions are inhibited when VCC is ≤ 3.0V typical. SYMBOL TABLE The following symbol table provides a key to under- standing the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user’s application. WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Current (Active) 100 mA NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V Levels @ f = 20MHz All I/Os = Open ICC2 VCC Current During Store 5 mA All Inputs = V IH ICC3 (2) VCC Current During 2.5 mA All I/Os = Open AUTOSTORE ISB1 VCC Standby Current 10 mA CE = VIH, All Other Inputs = VIH (TTL Input) All I/Os = Open ISB2 VCC Standby Current 250 µA All Inputs = V CC – 0.3V (CMOS Input) All I/Os = Open ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC , CE = VIH VIL(1) Input LOW Voltage –1 0.8 V VIH(1) Input HIGH Voltage 2 V CC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 4mA VOLAS AUTOSTORE Output 0.4 V I OLAS = 1mA VOH Output HIGH Voltage 2.4 V I OH = –4mA 3826 PGM T04.3 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions C I/O(2) Input/Output Capacitance 10 pF V I/O = 0V C IN(2) Input Capacitance 6 pF V IN = 0V 3826 PGM T06.1 RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 3826 PGM T02.1 Supply Voltage Limits X20C16 5V ±10% 3826 PGM T03.1 POWER-UP TIMING Symbol Parameter Max. Units tPUR (2) Power-Up to RAM Operation 100 µs tPUW (2) Power-Up to Nonvolatile Operation 5 ms

3826 PGM T05

ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance 100,000 Data Changes Per Bit Store Cycles 1,000,000 Store Cycles Data Retention 100 Years 3826 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V 3826 PGM T08.1 735Ω 318Ω OUTPUT 30pF

3826 FHD F04

CE WE NE OE Mode I/O Power H X X X Not Selected Output High Z Standby L H H L Read RAM Output Data Active L L H H Write “1” RAM Input Data High Active L L H H Write “0” RAM Input Data Low Active L H L L Array Recall Output High Z Active L L L H Software Command Input Data Active L H H H Output Disabled Output High Z Active L L L L Not Allowed Output High Z Active L H L H No Operation Output High Z Active

3826 PGM T09

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C16-35 –40 to +85°C X20C16-45 X20C16-55 tRC Read Cycle Time 35 45 55 ns tCE Chip Enable Access Time 35 45 55 ns tAA Address Access Time 35 45 55 ns tOE Output Enable Access Time 20 25 30 ns tLZ(3) Chip Enable to Output in Low Z 0 0 0 ns tOLZ (3) Output Enable to Output in Low Z 0 0 0 ns tHZ (3) Chip Disable to Output in High Z 0 15 0 20 0 25 ns tOHZ (3) Output Disable to Output in High Z 0 15 0 20 0 25 ns tOH Output Hold From Address Change 0 0 0 ns

3826 PGM T10

3826 FHD F05

C L = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.

X20C16-35 X20C16-45 X20C16-55 tWC Write Cycle Time 35 45 55 ns tCW Chip Enable to End of Write Input 30 35 40 ns tAS Address Setup Time 0 0 0 ns tWP Write Pulse Width 30 35 40 ns tWR Write Recovery Time 0 0 0 ns tDW Data Setup to End of Write 15 20 25 ns tDH Data Hold Time 3 3 3 ns tWZ (4) Write Enable to Output in High Z 15 20 25 ns tOW (4) Output Active from End of Write 5 5 5 ns tOZ (4) Output Enable to Output in High Z 15 20 25 ns

3826 PGM T11

3826 FHD F06

Note: (4) tWZ , tOW , tOZ are periodically sampled and not 100% tested.

3826 FHD F07.2 tWC tCW tAS tWP tDW tDH tWR DATA VALID ADDRESS OE CE WE DATA OUT DATA IN tWZ tOW VIH

X20C16-35 X20C16-45 X20C16-55 tRCC Array Recall Cycle Time 10 10 10 µs tRCP (5) Recall Pulse Width to 0.6 1000 40 1000 50 1000 ns InitiateRecall tRWE WE Setup Time to NE 000 n s

3826 PGM T13

Note: (5) The Recall Pulse Width (tRCP ) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE. Array Recall Cycle ADDRESS NE OE WE CE DATA I/O tRCC tRCP tRWE

3826 FHD F10

CE Controlled Software Command Sequence Note: (6) The Store Pulse Width (tSP ) is a minimum time that NE, WE and CE must be LOW simultaneously. (7) tSOE , tOEST and tNHZ are periodically sampled and not 100% tested. 3826 FHD F08.2 CMD ADDRESS 555 2AA 555 55AA OE CE WE NE DATA OUT DATA IN tWC tAS tSP tSPH tAH tNHZtSOE tDHtDS tSTO tOEST tNEHtNES Software Command Timing Limits X20C16-35 X20C16-45 X20C16-55 tSTO Store Cycle Time 5 5 5 ms tSP (6) Store Pulse Width 30 40 50 ns tSPH Store Pulse Hold Time 35 45 55 ns tWC Write Cycle Time 35 45 55 ns tAS Address Setup Time 0 0 0 ns tAH Address Hold time 0 0 0 ns tDS Data Setup Time 15 20 25 ns tDH Data Hold Time 3 3 3 ns tSOE (7) OE Disable to Store Function 20 20 20 ns tOEST (7) Output Enable from End of Store 10 10 10 ns tNHZ (7) Nonvolatile Enable to Output in 15 20 25 ns High Z tNES NE Setup Time 5 5 5 ns tNEH NE Hold Time 5 5 5 ns 3826 PGM T12.2

WE Controlled Software Command Sequence 3826 FHD F09.2 CMD ADDRESS 555 2AA 555 55AA OE CE WE NE DATA OUT DATA IN tWC tSP tSPH tAH tNHZtSOE tDHtDS tSTO tOEST tAS tNES tNEH

The AUTOSTORE feature automatically saves the con- tents of the X20C16’s static RAM to the on-board bit-for- bit shadow E 2PROM at power-down. This circuitry in- sures that no data is lost during accidental power-downs or general system crashes, and is ideal for microproces- sor caching systems, embedded software systems, and general system back-up memory. The AUTOSTORE instruction (EAS) to the SDP register sets the AUTOSTORE enable latch, allowing the X20C16 to automatically perform a store operation whenever V CC falls below the AUTOSTORE threshold (VASTH ). VCC must remain above the AUTOSTORE Cycle End Voltage (VASEND ) for the duration of the store cycle (tASTO ). The detailed timing for this feature is illustrated in the AUTOSTORE timing diagram, below. Once the AUTOSTORE cycle is initiated, all other device func- tions are inhibited. AUTOSTORE CYCLE Timing Diagrams

3826 FHD F14

Symbol Parameter Min. Max. Units tASTO AUTOSTORE Cycle Time 2.5 ms VASTH AUTOSTORE Threshold Voltage 4.0 4.3 V VASEND AUTOSTORE Cycle End Voltage 3.5 V

3826 PGM T15

VOLTS (V) TIME (ms) VASTH VASEND AUTOSTORE CYCLE IN PROGRESS tASTO STORE TIME

SOFTWARE DATA PROTECTION COMMANDS Command Data EAS Enable AUTOSTORE CC[H] RAS Reset AUTOSTORE CD[H] SS Software Store 33[H] 3826 PGM T14.1 SDP (Software Data Protection) Store State Diagram 3826 FHD F12.1 POWER UP STORE ON SS OR ENABLE/RESET AUTOSTORE NO STORE NO STORE NO STORE ADDR 555, DATA AAADDR 555, DATA AA ADDR 555, DATA AA ADDR 2AA, DATA 55 WRITE: ADDR 555, DATA=COMMAND RAM Write or Recall POWER UP Software Store Enabled Software Store & AUTOSTORE Enabled Power Down EAS SS RAS Power Down (AUTOSTORE) EAS SS Power On Recall 3826 FHD F13.1

0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 1.30 (33.02) REF. 0.026 (0.66) 0.014 (0.36) TYP. 0.018 (0.46) 0.225 (5.72) 0.140 (3.56) 0.060 (1.52) 0.015 (0.38)

3926 FHD F08

0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) TYP. 0.055 (1.40) 0.610 (15.49) 0.035 (0.89) TYP. 0.010 (0.25) 15° 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 1.490 (37.85) 1.435 (36.45)

0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.17) 0.610 (15.49) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.460 (37.08) 1.400 (35.56) 1.300 (33.02) REF. PIN 1 INDEX 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38)

3926 FHD F04

0.062 (1.57) 0.050 (1.27) 0.550 (13.97) 0.040 (1.02) 15° 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) TYP. 0.010 (0.25) PACKAGING INFORMATION

0.150 (3.81) BSC 0.300 (7.62) BSC 0.458 (11.63) 0.458 (11.63) 0.442 (11.22) PIN 1 0.400 (10.16) BSC 0.560 (14.22) 0.540 (13.71)

3926 FHD F14

0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. TYP. (3) PLCS.0.050 (1.27) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.200 (5.08) BSC 0.015 (0.38) 0.003 (0.08) 0.558 (14.17) 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) PIN 1 INDEX CORDER132 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NTL ±0.005 (0.127) PACKAGING INFORMATION

0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) TYP. 0.300 (7.62) REF. 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) PIN 1 0.400 (10.16)REF. 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 3° TYP. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) SEATING PLANE ±0.004 LEAD CO – PLANARITY

3926 FHD F13

32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY PACKAGING INFORMATION

0.2980 (7.5692) 0.2920 (7.4168) 0.4160 (10.5664) 0.3980 (10.1092) 0.0192 (0.4877) 0.0138 (0.3505) 0.0160 (0.4064) 0.0100 (0.2540) 0.050 (1.270) BSC 0.7080 (17.9832) 0.7020 (17.8308) 0.0110 (0.2794) 0.0040 (0.1016) 0.1040 (2.6416) 0.0940 (2.3876) 0.0350 (0.8890) 0.0160 (0.4064) 0.0125 (0.3175) 0.0090 (0.2311) 0° – 8° X 45°

3926 FHD F17

28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3. BACK EJECTOR PIN MARKED “KOREA” 4. CONTROLLING DIMENSION: INCHES (MM) SEATING PLANE BASE PLANE PACKAGING INFORMATION

3926 ILL F38.1 8.02 (0.315) 7.98 (0.314) 1.18 (0.046) 1.02 (0.040) 0.17 (0.007) 0.03 (0.001) 0.26 (0.010) 0.14 (0.006) 0.50 (0.0197) BSC 0.58 (0.023) 0.42 (0.017) 14.15 (0.557) 13.83 (0.544) 12.50 (0.492) 12.30 (0.484) PIN #1 IDENT. O 0.76 (0.03) SEATING PLANE SEE NOTE 2 SEE NOTE 2 0.50 ± 0.04 (0.0197 ± 0.0016) 0.30 ± 0.05 (0.012 ± 0.002) 14.80 ± 0.05 (0.583 ± 0.002) 1.30 ± 0.05 (0.051 ± 0.002) 0.17 (0.007) 0.03 (0.001) TYPICAL

32 PLACES

15 EQ. SPC. 0.50 ± 0.04 0.0197 ± 0.016 = 7.50 ± 0.06 (0.295 ± 0.0024) OVERALL TOL. NON-CUMULATIVE SOLDER PADS FOOTPRINT NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.

ORDERING INFORMATION

–35 = 35ns –45 = 45ns –55 = 55ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MB = Mil. STD 883 Package D = 28-Lead Cerdip P = 28 Lead Plastic Dip E = 32-Pad Ceramic LCC J = 32-Lead PLCC S = 28-Lead SOIC T = 32-Lead TSOP Device X20C16 X X -X