X20C04 XICOR | Alldatasheet

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©Xicor, Inc. 1992, 1995, 1996 Patents Pending Characteristics subject to change without notice 3825-2.8 7/31/97 T4/C0/D0 SH Nonvolatile Static RAM

DESCRIPTION

The Xicor X20C04 is a 512 x 8 NOVRAM featuring a static RAM overlaid bit-for-bit with a nonvolatile electri- cally erasable PROM (E 2PROM). The X20C04 is fabri- cated with advanced CMOS floating gate technology to achieve low power and wide power-supply margin. The X20C04 features the JEDEC approved pinout for byte- wide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E 2PROMs. The NOVRAM design allows data to be easily trans- ferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5µs or less. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E 2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.

FEATURES

  • High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum
  • Power-on Recall 2PROM Data Automatically Recalled Into SRAM Upon Power-up
  • Lock Out Inadvertent Store Operations
  • Low Power CMOS —Standby: 250 µA
  • Infinite E2PROM Array Recall, and RAM Read and Write Cycles
  • Compatible with X2004 4K X20C04 512 x 8 Bit PIN CONFIGURATION NC I/O0 NC NC NC OE NC CE I/O7 I/O6 NC NE NC VCC WE NC I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 4321 3 2 3 1 3 0 14 15 16 17 18 19 20 X20C04 (TOP VIEW)

3825 FHD F03

1 VCC

3825 FHD F02

Addresses (A0–A 8) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O 0–I/O7) Data is written to or read from the X20C04 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to both the static RAM and stores to the E 2PROM. Nonvolatile Enable (NE) The Nonvolatile Enable input controls all accesses to the E2PROM array (store and recall functions). PIN NAMES Symbol Description A0–A8 Address Inputs I/O0–I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable NE Nonvolatile Enable VCC +5V VSS Ground NC No Connect

3825 PGM T01

A3–A6 I/O0–I/O7 A0–A2 A7–A8 RECALL STORE

3825 FHD F01

Upon power-up (VCC ), the X20C04 performs an auto- matic array recall. When VCC minimum is reached, the recall is initiated, regardless of the state of CE, OE, WE and NE. Write Protection The X20C04 has five write protect features that are employed to protect the contents of both the nonvolatile memory and the RAM. CC Sense—All functions are inhibited when VCC is ≤ 3.5V.

  • A RAM write is required before a Store Cycle is initiated.
  • Write Inhibit—Holding either OE LOW, WE HIGH, CE HIGH, or NE HIGH during power-up and power- down will prevent an inadvertent store operation.
  • Noise Protection—A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a Store Cycle.
  • Noise Protection—A combined WE, NE, OE and CE pulse of less than 20ns will not initiate a recall cycle. DEVICE OPERATION The CE, OE, WE and NE inputs control the X20C04 operation. The X20C04 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C04. Nonvolatile Operations With NE LOW, recall operation is performed in the same manner as RAM read operation. A recall operation causes the entire contents of the E 2PROM to be written into the RAM array. The time required for the operation to complete is 5µs or less. A store operation causes the entire contents of the RAM array to be stored in the nonvolatile E 2PROM. The time for the operation to complete is 5ms or less. SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Current (Active) 100 mA NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V levels @ f = 5MHz. All I/Os = Open ICC2 VCC Current During Store 10 mA All Inputs = V IH All I/Os = Open ISB1 VCC Standby Current 10 mA CE = VIH (TTL Input) All Other Inputs = V IH, All I/Os = Open ISB2 VCC Standby Current 250 µA All Inputs = VCC – 0.3V (CMOS Input) All I/Os = Open ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC , CE = VIH VIL(1) Input LOW Voltage –1 0.8 V VIH(1) Input HIGH Voltage 2 V CC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 2.1mA VOH Output HIGH Voltage 2.4 V I OH = –400µA 3825 PGM T04.3 POWER-UP TIMING Symbol Parameter Max. Units tPUR (2) Power-Up to RAM Operation 100 µs tPUW (2) Power-Up to Nonvolatile Operation 5 ms

3825 PGM T05

Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. CAPACITANCE TA = +25°C, F = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions C I/O(2) Input/Output Capacitance 10 pF V I/O = 0V C IN(2) Input Capacitance 6 pF V IN = 0V 3825 PGM T06.1 RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 3825 PGM T02.1 Supply Voltage Limits X20C04 5V ±10%

3825 PGM T03

1.92KΩ 1.37KΩ OUTPUT 100pF ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance 100,000 Data Changes Per Bit Store Cycles 1,000,000 Store Cycles Data Retention 100 Years 3825 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input and Output Timing Levels 1.5V 3825 PGM T08.2 3825 FHD F04.1 MODE SELECTION CE WE NE OE Mode I/O Power H X X X Not Selected Output High Z Standby L H H L Read RAM Output Data Active L L H H Write “1” RAM Input Data High Active L L H H Write “0” RAM Input Data Low Active L H L L Array Recall Output High Z Active L L L H Nonvolatile Storing Output High Z Active L H H H Output Disabled Output High Z Active L L L L Not Allowed Output High Z Active L H L H No Operation Output High Z Active 3825 PGM T09.1

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C04-15 X20C04-20 X20C04-25 X20C04 tRC Read Cycle Time 150 200 250 300 ns tCE Chip Enable Access Time 150 200 250 300 ns tAA Address Access Time 150 200 250 300 ns tOE Output Enable Access Time 50 70 100 150 ns tLZ(3) Chip Enable to Output in Low Z 0 0 0 0 ns tOLZ (3) Output Enable to Output in Low Z 0 0 0 0 ns tHZ (3) Chip Disable to Output in High Z 80 100 100 100 ns tOHZ (3) Output Disable to Output in High Z 80 100 100 100 ns tOH Output Hold From Address Change 0 0 0 0 ns

3825 PGM T10

3825 FHD F05

C L = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven. tCE tRC ADDRESS CE OE WE DATA VALID DATA VALID tOE tLZ tOLZ tOH tAA tHZ tOHZ DATA I/O tOE VIH

X20C04-15 X20C04-20 X20C04-25 X20C04 tWC Write Cycle Time 150 200 250 300 ns tCW Chip Enable to End of Write Input 150 200 250 300 ns tAS Address Setup Time 0 0 0 0 ns tWP Write Pulse Width 100 120 150 200 ns tWR Write Recovery Time 0 0 0 0 ns tDW Data Setup to End of Write 100 120 150 200 ns tDH Data Hold Time 0 0 0 0 ns tWZ (4) Write Enable to Output in High Z 80 100 100 100 ns tOW (4) Output Active from End of Write 5 5 5 5 ns tOZ (4) Output Enable to Output in High Z 80 100 100 100 ns

3825 PGM T11

3825 FHD F06

Note: (4) tWZ , tOW , and tOZ are periodically sampled and not 100% tested.

3825 FHD F07.1 tWC tCW tAS tWP tDW tDH tWR DATA VALID ADDRESS OE CE WE DATA OUT DATA IN tWZ tOW VIH CE Controlled Write Cycle

VCC VCC MIN (5) tSOE STORE CYCLE LIMITS X20C04-15 X20C04-20 X20C04-25 X20C04 tSTC Store Cycle Time 5 5 5 5 ms tSP Store Pulse Width 100 120 150 200 ns tNHZ Nonvolatile Enable to 80 100 100 100 ns Output in High Z tOEST Output Enable From 10 10 10 10 ns End of Store tSOE OE Disable to Store 20 20 20 20 ns Function tNS NE Setup Time from WE 0000n s

3825 PGM T09

3825 FHD F15.1 Note: (5) X20C04 VCC min. = 4.5V The Store Pulse Width (tSP ) is a minimum time that NE, WE and CE must be LOW simultaneously.

X20C04-15 X20C04-20 X20C04-25 X20C04 tRCC Array Recall Cycle Time 5 5 5 5 µs tRCP (6) Recall Pulse Width to 0.1 1 0.12 1 0.15 1 0.2 1 µs InitiateRecall tRWE WE Setup Time to NE 000 0 n s 3825 PGM T13.1 Array Recall Cycle ADDRESS NE OE WE CE DATA I/O tRCC tRCP tRWE

3825 FHD F10

Note: (6) The Recall Pulse Width (tRCP ) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE.

0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46) 0.060 (1.52) 0.015 (0.38)

3926 FHD F08

0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.038 (0.97) TYP. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) MAX. 0.015 (0.38) 0.008 (0.20) 15° 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 1.490 (37.85) MAX. SEATING PLANE 0.005 (0.127) MIN. 0.232 (5.90) MAX. 0.150 (3.81) MIN.

3926 FHD F04

NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. P ACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.160 (4.06) 0.120 (3.05) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.470 (37.34) 1.400 (35.56) 1.300 (33.02) REF. PIN 1 INDEX 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.040 (1.02) 15° 28-LEAD PLASTIC DUAL IN-LINE P ACKAGE TYPE P TYP. 0.010 (0.25)

0.150 (3.81) BSC 0.458 (11.63) 0.458 (11.63) 0.442 (11.22) PIN 1

3926 FHD F14

0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. TYP. (3) PLCS.0.050 (1.27) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.200 (5.08) BSC 0.558 (14.17) 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) PIN 1 INDEX CORNER 32-P AD CERAMIC LEADLESS CHIP CARRIER P ACKAGE TYPE E NOTE: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NL T ±0.005 (0.127) 0.300 (7.62) BSC 0.015 (0.38) MIN. 0.400 (10.16) BSC 0.560 (14.22) 0.540 (13.71) DIA. 0.015 (0.38) 0.003 (0.08)

0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) TYP. 0.300 (7.62) REF. 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) PIN 1 0.400 (10.16)REF. 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 3° TYP. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) SEATING PLANE ±0.004 LEAD CO – PLANARITY

3926 FHD F13

32-LEAD PLASTIC LEADED CHIP CARRIER P ACKAGE TYPE J NOTES: 1. ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONL Y 0.510" TYPICAL 0.050" TYPICAL 0.050" TYPICAL 0.300" REF FOOTPRINT 0.400" 0.410" 0.030" TYPICAL

32 PLACES

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.

ORDERING INFORMATION

–15 = 150ns –20 = 200ns –25 = 250ns Blank = 300ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MB = MIL-STD-833 Package D = 28-Lead Cerdip P = 28 Lead Plastic DIP E = 32-Pad Ceramic LCC J = 32-Lead PLCC Device X20C04 X X -X