Sensor

X1642BIGABL

Texas Instruments

Single-Chip 77- and 79-GHz FMCW Radar Sensor

Manufacturer: Texas Instruments

Document: 84 Pages / 3Mb

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AWR1642 TI1 | Alldatasheet

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ADVANCE□INFORMATION Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. AWR1642 SWRS203 – MAY 2017 AWR1642Single-Chip77-and79-GHzFMCWRadarSensor

1 Device Overview

1.1 Features

FMCW Transceiver – Integrated PLL, Transmitter, Receiver, Baseband, and A2D – 76- to 81-GHz Coverage With 4 GHz Available Bandwidth – Four Receive Channels – Two Transmit Channels – Ultra-Accurate Chirp (Timing) Engine Based on Fractional-N PLL – TX Power: 12 dBm – RX Noise Figure: – 15 dB (76 to 77 GHz) – 16 dB (77 to 81 GHz) – Phase Noise at 1 MHz: – –94 dBc/Hz (76 to 77 GHz) – –91 dBc/Hz (77 to 81 GHz)
Built-in Calibration and Self-Test (Monitoring) – ARM® Cortex®-R4F-Based Radio Control System – Built-in Firmware (ROM) – Self-calibrating System Across Frequency and Temperature
C674x DSP for FMCW Signal Processing – On-Chip Memory: 1.5MB
Cortex-R4F Microcontroller for Object Tracking and Classification, AUTOSAR, and Interface Control – Supports Autonomous Mode (Loading User Application from QSPI Flash Memory)
Integrated Peripherals – Internal Memories With ECC
Host Interface – CAN (Two Instances, One Being CAN-FD)
Other Interfaces Available to User Application – Up to 6 ADC Channels – Up to 2 SPI Channels – Up to 2 UARTs – I2C – GPIOs – 2-Lane LVDS Interface for Raw ADC Data and Debug Instrumentation
ASIL B Capable
AECQ100 Qualified
AWR1642 Advanced Features – Embedded Self-monitoring With No Host Processor Involvement – Complex Baseband Architecture – Embedded Interference Detection Capability
Power Management – Built-in LDO Network for Enhanced PSRR – I/Os Support Dual Voltage 3.3 V/1.8 V
Clock Source – 40.0-MHz Crystal With Internal Oscillator – Supports External Oscillator at 40 and 50 MHz – Supports Externally Driven Clock (Square/Sine) at 40 and 50 MHz
Easy Hardware Design – 0.65-mm Pitch, 161-Pin 10.4 mm × 10.4 mm Flip Chip BGA Package for Easy Assembly and Low-Cost PCB Design – Small Solution Size
Supports Automotive Temperature Operating Range

1.2 Applications

Blind Spot Detection
Lane Change Assistance
Cross Traffic Alert
Parking Assistance
Occupancy Detection
Simple Gesture Recognition
Car Door Opener Applications

ADVANCE□INFORMATION RX1 RX2 RX3 RX4 TX2 Antenna Structure TX1 Radar Front End Integrated MCU ARM Cortex-R4F CAN Power Management 40-MHz Crystal Serial FLASH DCAN PHY Automotive Network Integrated DSP TI C674x AWR1642 CAN FD MCAN PHY Automotive Network QSPI AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Device Overview Copyright © 2017, Texas Instruments Incorporated (1) For more information, see Section 10, Mechanical Packaging and Orderable Information. Figure 1-1. Autonomous Radar Sensor For Automotive Applications

1.3 Description

The AWR1642 device is an integrated single-chip FMCW radar sensor capable of operation in the 76- to 81-GHz band. The device is built with TI’s low-power 45-nm RFCMOS process and enables unprecedented levels of integration in an extremely small form factor. The AWR1642 is an ideal solution for low-power, self-monitored, ultra-accurate radar systems in the automotive space. The AWR1642 device is a self-contained FMCW radar sensor single-chip solution that simplifies the implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45- nm RFCMOS process, which enables a monolithic implementation of a 2TX, 4RX system with built-in PLL and A2D converters. It integrates the DSP subsystem, which contains TI's high performance C674x DSP for the Radar Signal processing. The device includes an ARM R4F-based processor subsystem, which is responsible for radio configuration, control, and calibration. Simple programming model changes can enable a wide variety of sensor implementation (Short, Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally, the device is provided as a complete platform solution including reference hardware design, software drivers, sample configurations, API guide, and user documentation. Device Information(1) PART NUMBER PACKAGE BODY SIZE X1642BIGABL (Tray) FCBGA (161) 10.4 mm × 10.4 mm

ADVANCE□INFORMATION Serial Flash interface Optional External MCU interface PMIC control Primary communication interfaces (automotive) For debug JTAG for debug/ development High-speed ADC output interface (for recording) High-speed input for hardware-in-loop verification IF ADC Digital Front End (Decimation filter chain) LNA IF ADCLNA IF ADCLNA IF ADCLNA PA PA Synth (20 GHz) Ramp Generatorx4 Osc. GPADC VMON Temp Cortex-R4F @ 200-MHz (User programmable) Prog RAM (256kB*) Data RAM (192kB*) Boot ROM QSPI SPI SPI / I2C Debug UARTs DCAN DMA Test/ Debug ADC Buffer LVDS RF/Analog subsystem Master subsystem (Customer programmed) * Up to 512KB of Radar Data Memory can be switched to the Master R4F if required DSP subsystem (Customer programmed) Mailbox Bus Matrix HILC674x DSP @600 MHz L1P (32KB) L1D (32KB) (256KB) DMA CRC Radar Data Memory (L3) 768KB* RF Control/ BIST CAN-FD Copyright © 2017, Texas Instruments Incorporated AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Device OverviewCopyright © 2017, Texas Instruments Incorporated

1.4 Functional Block Diagram

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Revision History Copyright © 2017, Texas Instruments Incorporated Table of Contents

5.9 Thermal Resistance Characteristics for FCBGA

10 Mechanical, Packaging, and Orderable

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2017 * Initial Release

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Device ComparisonCopyright © 2017, Texas Instruments Incorporated (1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

3 Device Comparison

Table 3-1. Device Features Comparison FUNCTION AWR1243 AWR1443 AWR1642 Number of receivers 4 4 4 Number of transmitters 3 3 2 On-chip memory — 576KB 1.5MB ASIL B-Capable — B-Capable Max interface (MHz) 15 5 5 Max real sampling rate (Msps) 37.5 12.5 12.5 Processor MCU (R4F) — Yes Yes DSP (C674x) — — Yes Peripherals Serial Peripheral Interface (SPI) ports 1 1 2 Quad Serial Peripheral Interface (QSPI) — Yes Yes Inter-Integrated Circuit (I2C) interface — 1 1 Controller Area Network (DCAN) interface — Yes Yes CAN FD — — Yes Trace — — Yes PWM — — Yes Hardware In Loop (HIL/DMM) — — Yes GPADC — Yes Yes LVDS/Debug Yes Yes Yes CSI2 Yes — — Hardware accelerator — Yes — 1-V bypass mode Yes Yes Yes Cascade (20-GHz sync) Yes — — JTAG — Yes Yes Product status(1) PRODUCT PREVIEW (PP), ADVANCE INFORMATION (AI), or PRODUCTION DATA (PD) AI AI AI

3.1 Related Products

For information about other devices in this family of products or related products see the links that follow. mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less power using the smallest footprint mmWave sensor portfolio for automotive applications. Automotive mmWave Sensors TI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor portfolio enables design and development of ADAS system solution for every performance, application and sensor configuration ranging from comfort functions to safety functions in all vehicles. Companion Products for AWR1642 Review products that are frequently purchased or used in conjunction with this product. Reference Designs for AWR1642 TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

ADVANCE□INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R Not to scale VSSA VOUT_PA VSSA VSSA VSSA GPIO_46 VOUT _14APLL1 VOUT _14SYNTH OSC _CLKOUT VSSA VSSA VOUT_PA VSSA TX1 VSSA TX2 VSSA GPIO_45 GPIO_44 VBGAP VIN _18CLK VIN _18VCO GPADC5 GPIO_40 GPIO_41 VSSA VIN _13RF2 VSSA VSSA VSSA VSSA VSSA GPIO_43 GPIO_42 SPIA_cs_n GPADC6 CLKP VIN _13RF2 SPIA_mosi GPIO_39 CLKM VSSA VSSA VSSA VSS VSS VSS VSS VSS SPIA_clk SPIA_miso VIOIN _18DIFF RX4 VSSA VIN_18BB VSS VSS SPIB_mosi SPIB_clk VIOIN VSSA VSSA VSSA VIN _13RF1 VSS VSS VSS VSS SYNC_OUT SPIB_miso VIN_SRAM RX3 VSSA VIN _13RF1 VSS VSS VSS GPIO_0 SPIB_cs_n VDDIN VSSA VSSA VSSA VIN _13RF1 VSS VSS VSS VSS GPIO_1 LVDS_TXP0 LVDS_TXM0 RX2 VSSA VIN_18BB VSS VSS VSS VSS VSS GPIO_2 LVDS_TXP1 LVDS_TXM1 VSSA VSSA VSSA VSS VSS VSS VSS VPP LVDS_CLKP LVDS_CLKM RX1 VSSA LVDS _FRCLKP LVDS _FRCLKM VSSA VSSA VSSA rs232_rx rs232_tx nERROR_OUT nERROR_IN MCU _CLKOUT Warm _Reset TMS VDDIN QSPI[1] TDO GPIO_48 GPIO_47 GPADC1 GPADC2 GPADC3 SYNC_in GPIO_32 GPIO_34 GPIO_36 GPIO_38 PMIC _CLKOUT TCK QSPI_cs_n QSPI[3] SPI_HOST_INTR VNWA VDDIN VSSA GPADC4 NRESET GPIO_31 GPIO_33 VDDIN GPIO_35 GPIO_37 VIOIN_18 VIOIN TDI QSPI_clk QSPI[0] QSPI[2] VSS AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and FunctionsCopyright © 2017, Texas Instruments Incorporated

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5 show the same pins, but split into four quadrants. Figure 4-1. Pin Diagram

ADVANCE□INFORMATION 1 2 3 4 5 6 7 8 A B C D E F G Not to scale VSSA VOUT_PA VSSA VSSA VSSA VSSA VOUT_PA VSSA TX1 VSSA TX2 VSSA GPIO_45 VSSA VIN _13RF2 VSSA VSSA VSSA VSSA VSSA GPIO_43 VIN _13RF2 VSSA VSSA VSSA VSS VSS VSS RX4 VSSA VIN_18BB VSSA VSSA VSSA VIN _13RF1 VSS VSS VSS AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Figure 4-2. Top Left Quadrant

ADVANCE□INFORMATION 9 10 11 12 13 14 15 A B C D E F G Not to scale VSSA VOUT _14APLL1 VOUT _14SYNTH OSC _CLKOUT VSSA VSSA VBGAP VIN _18CLK VIN _18VCO VSSA VSSA FM_CW _CLKOUT VSSA VSSA VIOIN _18DIFF FM_CW _SYNCIN2 VSS VSS VSSA CLKP VSSA VSS VSS VDDIN CLKM VSS Reserved CSI2 _TXM[0] CSI2 _TXP[0] ANAMUX/ GPADC5 VSENSE/ GPADC6 AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and FunctionsCopyright © 2017, Texas Instruments Incorporated Figure 4-3. Top Right Quadrant

ADVANCE□INFORMATION 1 2 3 4 5 6 7 8 H J K L M N P R Not to scale RX3 VSSA VIN _13RF1 VSS VSSA VSSA VSSA VIN _13RF1 VSS VSS VSS RX2 VSSA VIN_18BB VSS VSS VSSA VSSA VSSA VSS VSS VSS RX1 VSSA VSSA VSSA VSSA rs232_rx rs232_tx nERROR_OUT nERROR_IN MCU _CLKOUT GPADC1 GPADC2 GPADC3 SYNC_in GPIO_32 GPIO_34 GPIO_36 GPIO_38 VSSA GPADC4 NRESET GPIO_31 GPIO_33 VDDIN GPIO_35 GPIO_37 AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Figure 4-4. Bottom Left Quadrant

ADVANCE□INFORMATION 9 10 11 12 13 14 15 H J K L M N P R Not to scale VSS VSS GPIO_0 SPIB_cs_n VDDIN VSS GPIO_1 LVDS_TXP0 LVDS_TXM0 VSS VSS VSS GPIO_2 LVDS_TXP1 LVDS_TXM1 VSS VPP LVDS_CLKP LVDS_CLKM LVDS _FRCLKP LVDS _FRCLKM Warm _Reset TMS VDDIN QSPI[1] TDO GPIO_48 GPIO_47 PMIC _CLKOUT TCK QSPI_cs_n QSPI[3] SPI_HOST_INTR VNWA VDDIN VIOIN_18 VIOIN TDI QSPI_clk QSPI[0] QSPI[2] VSS AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and FunctionsCopyright © 2017, Texas Instruments Incorporated Figure 4-5. Bottom Right Quadrant

4.2 Pin Attributes

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 SWRS203 – MAY 2017 www.ti.com Table 4-1. Pin Attributes (ABL0161 Package) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] H13 GPIO_0 GPIO_13 0xFFFFEA04 0 IO Output Disabled Pull Down GPIO_0 1 IO PMIC_CLKOUT 2 O ePWM1b 10 O ePWM2a 11 O J13 GPIO_1 GPIO_16 0xFFFFEA08 0 IO Output Disabled Pull Down GPIO_1 1 IO SYNC_OUT 2 O DMM_MUX_IN 12 I SPIB_cs_n_1 13 IO SPIB_cs_n_2 14 IO ePWM1SYNCI 15 I K13 GPIO_2 GPIO_26 0xFFFFEA64 0 IO Output Disabled Pull Down GPIO_2 1 IO OSC_CLKOUT 2 O MSS_uartb_tx 7 O BSS_uart_tx 8 O SYNC_OUT 9 O PMIC_CLKOUT 10 O R4 GPIO_31 TRACE_DATA_0 0xFFFFEA7C 0 O Output Disabled Pull Down GPIO_31 1 IO DMM0 2 I MSS_uarta_tx 4 IO P5 GPIO_32 TRACE_DATA_1 0xFFFFEA80 0 O Output Disabled Pull Down GPIO_32 1 IO DMM1 2 I R5 GPIO_33 TRACE_DATA_2 0xFFFFEA84 0 O Output Disabled Pull Down GPIO_33 1 IO DMM2 2 I P6 GPIO_34 TRACE_DATA_3 0xFFFFEA88 0 O Output Disabled Pull Down GPIO_34 1 IO DMM3 2 I ePWM3SYNCO 4 O R7 GPIO_35 TRACE_DATA_4 0xFFFFEA8C 0 O Output Disabled Pull Down GPIO_35 1 IO DMM4 2 I ePWM2SYNCO 4 O

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 Table 4-1. Pin Attributes (ABL0161 Package) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] P7 GPIO_36 TRACE_DATA_5 0xFFFFEA90 0 O Output Disabled Pull Down GPIO_36 1 IO DMM5 2 I MSS_uartb_tx 5 O R8 GPIO_37 TRACE_DATA_6 0xFFFFEA94 0 O Output Disabled Pull Down GPIO_37 1 IO DMM6 2 I BSS_uart_tx 5 O P8 GPIO_38 TRACE_DATA_7 0xFFFFEA98 0 O Output Disabled Pull Down GPIO_38 1 IO DMM7 2 I DSS_uart_tx 5 O D14 GPIO_39 TRACE_DATA_8 0xFFFFEA9C 0 O Output Disabled Pull Down GPIO_39 1 IO DMM8 2 I CAN_FD_tx 4 IO ePWM1SYNCI 5 I B14 GPIO_40 TRACE_DATA_9 0xFFFFEAA0 0 O Output Disabled Pull Down GPIO_40 1 IO DMM9 2 I CAN_FD_rx 4 IO ePWM1SYNCO 5 O B15 GPIO_41 TRACE_DATA_10 0xFFFFEAA4 0 O Output Disabled Pull Down GPIO_41 1 IO DMM10 2 I ePWM3a 4 O C9 GPIO_42 TRACE_DATA_11 0xFFFFEAA8 0 O Output Disabled Pull Down GPIO_42 1 IO DMM11 2 I ePWM3b 4 O C8 GPIO_43 TRACE_DATA_12 0xFFFFEAAC 0 O Output Disabled Pull Down GPIO_43 1 IO DMM12 2 I ePWM1a 4 O CAN_tx 5 IO

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 SWRS203 – MAY 2017 www.ti.com Table 4-1. Pin Attributes (ABL0161 Package) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] B9 GPIO_44 TRACE_DATA_13 0xFFFFEAB0 0 O Output Disabled Pull Down GPIO_44 1 IO DMM13 2 I ePWM1b 4 O CAN_rx 5 I B8 GPIO_45 TRACE_DATA_14 0xFFFFEAB4 0 O Output Disabled Pull Down GPIO_45 1 IO DMM14 2 I ePWM2a 4 O A9 GPIO_46 TRACE_DATA_15 0xFFFFEAB8 0 O Output Disabled Pull Down GPIO_46 1 IO DMM15 2 I ePWM2b 4 O N15 GPIO_47 TRACE_CLK 0xFFFFEABC 0 O Output Disabled Pull Down GPIO_47 1 IO DMM_CLK 2 I N14 GPIO_48 TRACE_CTL 0xFFFFEAC0 0 O Output Disabled Pull Down GPIO_48 1 IO DMM_SYNC 2 I N8 MCU_CLKOUT GPIO_25 0xFFFFEA60 0 IO Output Disabled Pull Down MCU_CLKOUT 1 O ePWM1a 12 O N7 nERROR_IN nERROR_IN 0xFFFFEA44 0 I Input N6 nERROR_OUT nERROR_OUT 0xFFFFEA4C 0 O Hi-Z (Open Drain) P9 PMIC_CLKOUT SOP[2] 0xFFFFEA68 During Power Up I Output Disabled Pull Down GPIO_27 0 IO PMIC_CLKOUT 1 O ePWM1b 11 O ePWM2a 12 O R13 QSPI[0] GPIO_8 0xFFFFEA2C 0 IO Output Disabled Pull Down QSPI[0] 1 IO SPIB_miso 2 IO N12 QSPI[1] GPIO_9 0xFFFFEA30 0 IO Output Disabled Pull Down QSPI[1] 1 IO SPIB_mosi 2 IO SPIB_cs_n_2 8 IO R14 QSPI[2] GPIO_10 0xFFFFEA34 0 IO Output Disabled Pull Down QSPI[2] 1 I CAN_FD_tx 8 O

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 Table 4-1. Pin Attributes (ABL0161 Package) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] P12 QSPI[3] GPIO_11 0xFFFFEA38 0 IO Output Disabled Pull Down QSPI[3] 1 IO CAN_FD_rx 8 I R12 QSPI_clk GPIO_7 0xFFFFEA3C 0 IO Output Disabled Pull Down QSPI_clk 1 IO SPIB_clk 2 IO DSS_uart_tx 6 O P11 QSPI_cs_n GPIO_6 0xFFFFEA40 0 IO Output Disabled Pull Up QSPI_cs_n 1 IO SPIB_cs_n 2 IO N4 rs232_rx GPIO_15 0xFFFFEA74 0 IO Input Enabled Pull Up rs232_rx 1 I MSS_uarta_rx 2 I BSS_uart_tx 6 IO MSS_uartb_rx 7 IO CAN_FD_rx 8 I I2C_scl 9 IO ePWM2a 10 O ePWM2b 11 O ePWM3a 12 O N5 rs232_tx GPIO_14 0xFFFFEA78 0 IO Output Enabled rs232_tx 1 O MSS_uarta_tx 5 IO MSS_uartb_tx 6 IO BSS_uart_tx 7 IO CAN_FD_tx 10 O I2C_sda 11 IO ePWM1a 12 O ePWM1b 13 O NDMM_EN 14 I ePWM2a 15 O E13 SPIA_clk GPIO_3 0xFFFFEA14 0 IO Output Disabled Pull Up SPIA_clk 1 IO CAN_rx 6 I DSS_uart_tx 7 O C13 SPIA_cs_n GPIO_30 0xFFFFEA18 0 IO Output Disabled Pull Up SPIA_cs_n 1 IO CAN_tx 6 O

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 SWRS203 – MAY 2017 www.ti.com Table 4-1. Pin Attributes (ABL0161 Package) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] E14 SPIA_miso GPIO_20 0xFFFFEA10 0 IO Output Disabled Pull Up SPIA_miso 1 IO CAN_FD_tx 2 O D13 SPIA_mosi GPIO_19 0xFFFFEA0C 0 IO Output Disabled Pull Up SPIA_mosi 1 IO CAN_FD_rx 2 I DSS_uart_tx 8 O F14 SPIB_clk GPIO_5 0xFFFFEA24 0 IO Output Disabled Pull Up SPIB_clk1 1 IO MSS_uarta_rx 2 I MSS_uartb_tx 6 O BSS_uart_tx 7 O CAN_FD_rx 8 I H14 SPIB_cs_n GPIO_4 0xFFFFEA28 0 IO Output Disabled Pull Up SPIB_cs_n 1 IO MSS_uarta_tx 2 O MSS_uartb_tx 6 O BSS_uart_tx 7 IO QSPI_clk_ext 8 I CAN_FD_tx 9 O G14 SPIB_miso GPIO_22 0xFFFFEA20 0 IO Output Disabled Pull Up SPIB_miso 1 IO I2C_scl 2 IO DSS_uart_tx 6 O F13 SPIB_mosi GPIO_21 0xFFFFEA1C 0 IO Output Disabled Pull Up SPIB_mosi 1 IO I2C_sda 2 IO P13 SPI_HOST_INTR GPIO_12 0xFFFFEA00 0 IO Output Disabled Pull Down SPI_HOST_INTR 1 O SPIB_cs_n_1 6 IO P4 SYNC_in GPIO_28 0xFFFFEA6C 0 IO Output Disabled Pull Down SYNC_IN 1 I MSS_uartb_rx 6 IO DMM_MUX_IN 7 I SYNC_OUT 9 O

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 Table 4-1. Pin Attributes (ABL0161 Package) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8] G13 SYNC_OUT SOP[1] 0xFFFFEA70 During Power Up I Output Disabled Pull Down GPIO_29 0 IO SYNC_OUT 1 O DMM_MUX_IN 9 I SPIB_cs_n_1 10 IO SPIB_cs_n_2 11 IO P10 TCK GPIO_17 0xFFFFEA50 0 IO Input Enabled Pull Down TCK 1 I MSS_uartb_tx 2 O CAN_FD_tx 8 O R11 TDI GPIO_23 0xFFFFEA58 0 IO Input Enabled Pull Up TDI 1 I MSS_uarta_rx 2 I N13 TDO SOP[0] 0xFFFFEA5C During Power Up I Output Enabled GPIO_24 0 IO TDO 1 O MSS_uarta_tx 2 O MSS_uartb_tx 6 O BSS_uart_tx 7 O NDMM_EN 9 I N10 TMS GPIO_18 0xFFFFEA54 0 IO Input Enabled Pull Down TMS 1 I BSS_uart_tx 2 O CAN_FD_rx 6 I N9 Warm_Reset Warm_Reset 0xFFFFEA48 0 IO Hi-Z Input (Open Drain) The following list describes the table column headers: 1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom. 2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0). 3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0). 4. PINCNTL ADDRESS: MSS Address for PinMux Control 5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value. 6. TYPE: Signal type and direction: – I = Input – O = Output

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 SWRS203 – MAY 2017 www.ti.com – IO = Input or Output 7. BALL RESET STATE: The state of the terminal at power-on reset 8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. – Pull Up: Internal pullup – Pull Down: Internal pulldown – An empty box means No pull.

4.3 Signal Descriptions

Table 4-2. Signal Descriptions - Digital SIGNAL NAME PIN TYPE DESCRIPTION BALL NO. BSS_UART_TX O Debug UART Transmit [Radar Block] F14, H14, K13, N10, N13, N4, N5, R8 CAN_FD_RX I CAN FD (MCAN) Receive Signal B14, D13, F14, N10, N4, P12 CAN_FD_TX O CAN FD (MCAN) Transmit Signal D14, E14, H14, N5, P10, R14 CAN_RX I CAN (DCAN) Receive Signal B9, E13 CAN_TX IO CAN (DCAN) Transmit Signal C13, C8 DMM0 I Debug Interface (Hardware In Loop) - Data Line R4 DMM1 I Debug Interface (Hardware In Loop) - Data Line P5 DMM2 I Debug Interface (Hardware In Loop) - Data Line R5 DMM3 I Debug Interface (Hardware In Loop) - Data Line P6 DMM4 I Debug Interface (Hardware In Loop) - Data Line R7 DMM5 I Debug Interface (Hardware In Loop) - Data Line P7 DMM6 I Debug Interface (Hardware In Loop) - Data Line R8 DMM7 I Debug Interface (Hardware In Loop) - Data Line P8 DMM8 I Debug Interface (Hardware In Loop) - Data Line D14 DMM9 I Debug Interface (Hardware In Loop) - Data Line B14 DMM10 I Debug Interface (Hardware In Loop) - Data Line B15 DMM11 I Debug Interface (Hardware In Loop) - Data Line C9 DMM12 I Debug Interface (Hardware In Loop) - Data Line C8 DMM13 I Debug Interface (Hardware In Loop) - Data Line B9 DMM14 I Debug Interface (Hardware In Loop) - Data Line B8 DMM15 I Debug Interface (Hardware In Loop) - Data Line A9 DMM_CLK I Debug Interface (Hardware In Loop) - Clock N15 DMM_MUX_IN I Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) G13, J13, P4 DMM_SYNC I Debug Interface (Hardware In Loop) - Sync N14 DSS_UART_TX O Debug UART Transmit [DSP] D13, E13, G14, P8, R12 EPWM1A O PWM Module 1 - OutPut A C8, N5, N8 EPWM1B O PWM Module 1 - OutPut B B9, H13, N5, P9 EPWM1SYNCI I D14, J13 EPWM1SYNCO O B14 EPWM2A O PWM Module 2- OutPut A B8, H13, N4, N5, P9 EPWM2B O PWM Module 2 - OutPut B A9, N4 EPWM2SYNCO O R7 EPWM3A O PWM Module 3 - OutPut A B15, N4 EPWM3B O PWM Module 3 - OutPut B C9 EPWM3SYNCO O P6 GPIO_0 IO General-Purpose IO H13 GPIO_1 IO General-Purpose IO J13 GPIO_2 IO General-Purpose IO K13 GPIO_3 IO General-Purpose IO E13 GPIO_4 IO General-Purpose IO H14 GPIO_5 IO General-Purpose IO F14 GPIO_6 IO General-Purpose IO P11 GPIO_7 IO General-Purpose IO R12

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Table 4-2. Signal Descriptions - Digital (continued) SIGNAL NAME PIN TYPE DESCRIPTION BALL NO. GPIO_8 IO General-Purpose IO R13 GPIO_9 IO General-Purpose IO N12 GPIO_10 IO General-Purpose IO R14 GPIO_11 IO General-Purpose IO P12 GPIO_12 IO General-Purpose IO P13 GPIO_13 IO General-Purpose IO H13 GPIO_14 IO General-Purpose IO N5 GPIO_15 IO General-Purpose IO N4 GPIO_16 IO General-Purpose IO J13 GPIO_17 IO General-Purpose IO P10 GPIO_18 IO General-Purpose IO N10 GPIO_19 IO General-Purpose IO D13 GPIO_20 IO General-Purpose IO E14 GPIO_21 IO General-Purpose IO F13 GPIO_22 IO General-Purpose IO G14 GPIO_23 IO General-Purpose IO R11 GPIO_24 IO General-Purpose IO N13 GPIO_25 IO General-Purpose IO N8 GPIO_26 IO General-Purpose IO K13 GPIO_27 IO General-Purpose IO P9 GPIO_28 IO General-Purpose IO P4 GPIO_29 IO General-Purpose IO G13 GPIO_30 IO General-Purpose IO C13 GPIO_31 IO General-Purpose IO R4 GPIO_32 IO General-Purpose IO P5 GPIO_33 IO General-Purpose IO R5 GPIO_34 IO General-Purpose IO P6 GPIO_35 IO General-Purpose IO R7 GPIO_36 IO General-Purpose IO P7 GPIO_37 IO General-Purpose IO R8 GPIO_38 IO General-Purpose IO P8 GPIO_39 IO General-Purpose IO D14 GPIO_40 IO General-Purpose IO B14 GPIO_41 IO General-Purpose IO B15 GPIO_42 IO General-Purpose IO C9 GPIO_43 IO General-Purpose IO C8 GPIO_44 IO General-Purpose IO B9 GPIO_45 IO General-Purpose IO B8 GPIO_46 IO General-Purpose IO A9 GPIO_47 IO General-Purpose IO N15 GPIO_48 IO General-Purpose IO N14 I2C_SCL IO I2C Clock G14, N4 I2C_SDA IO I2C Data F13, N5 LVDS_TXP[0] O Differential data Out – Lane 0 J14 LVDS_TXM[0] O J15 LVDS_CLKP O Differential data Out – Lane 1 L14 LVDS_CLKM O L15

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and FunctionsCopyright © 2017, Texas Instruments Incorporated Table 4-2. Signal Descriptions - Digital (continued) SIGNAL NAME PIN TYPE DESCRIPTION BALL NO. LVDS_TXP[1] O Differential clock Out K14 LVDS_TXM[1] O K15 LVDS_FRCLKP O Differential Frame Clock M14 LVDS_FRCLKM O M15 MCU_CLKOUT O Programmable clock given out to external MCU or the processor N8 MSS_UARTA_RX I Master Subsystem - UART A Receive F14, N4, R11 MSS_UARTA_TX O Master Subsystem - UART A Transmit H14, N13, N5, R4 MSS_UARTB_RX IO Master Subsystem - UART B Receive N4, P4 MSS_UARTB_TX O Master Subsystem - UART B Transmit F14, H14, K13, N13, N5, P10, P7 NDMM_EN I Debug Interface (Hardware In Loop) Enable - Active Low Signal N13, N5 nERROR_IN I Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware nERROR_OUT O Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. PMIC_CLKOUT O Output Clock from AWR1642 device for PMIC H13, K13, P9 QSPI[0] IO QSPI Data Line #0 (Used with Serial Data Flash) R13 QSPI[1] IO QSPI Data Line #1 (Used with Serial Data Flash) N12 QSPI[2] I QSPI Data Line #2 (Used with Serial Data Flash) R14 QSPI[3] IO QSPI Data Line #3 (Used with Serial Data Flash) P12 QSPI_CLK IO QSPI Clock (Used with Serial Data Flash) R12 QSPI_CLK_EXT I QSPI Clock (Used with Serial Data Flash) H14 QSPI_CS_N IO QSPI Chip Select (Used with Serial Data Flash) P11 RS232_RX I Debug UART (Operates as Bus Master) - Receive Signal N4 RS232_TX O Debug UART (Operates as Bus Master) - Receive Signal N5 SOP[0] I Sense On Power - Line#0 N13 SOP[1] I Sense On Power - Line#1 G13 SOP[2] I Sense On Power - Line#2 P9 SPIA_CLK IO SPI Channel A - Clock E13 SPIA_CS_N IO SPI Channel A - Chip Select C13 SPIA_MISO IO SPI Channel A - Master In Slave Out E14 SPIA_MOSI IO SPI Channel A - Master Out Slave In D13 SPIB_CLK IO SPI Channel B - Clock F14, R12 SPIB_CS_N IO SPI Channel B Chip Select (Instance ID 0) H14, P11 SPIB_CS_N_1 IO SPI Channel B Chip Select (Instance ID 1) G13, J13, P13 SPIB_CS_N_2 IO SPI Channel B Chip Select (Instance ID 2) G13, J13, N12 SPIB_MISO IO SPI Channel B - Master In Slave Out G14, R13 SPIB_MOSI IO SPI Channel B - Master Out Slave In F13, N12 SPI_HOST_INTR O Out of Band Interrupt to an external host communicating over SPI P13 SYNC_IN I Low frequency Synchronization signal input P4 SYNC_OUT O Low Frequency Synchronization Signal output G13, J13, K13, P4 TCK I JTAG Test Clock P10 TDI I JTAG Test Data Input R11 TDO O JTAG Test Data Output N13 TMS I JTAG Test Mode Signal N10 TRACE_CLK O Debug Trace Output - Clock N15 TRACE_CTL O Debug Trace Output - Control N14

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Table 4-2. Signal Descriptions - Digital (continued) SIGNAL NAME PIN TYPE DESCRIPTION BALL NO. TRACE_DATA_0 O Debug Trace Output - Data Line R4 TRACE_DATA_1 O Debug Trace Output - Data Line P5 TRACE_DATA_2 O Debug Trace Output - Data Line R5 TRACE_DATA_3 O Debug Trace Output - Data Line P6 TRACE_DATA_4 O Debug Trace Output - Data Line R7 TRACE_DATA_5 O Debug Trace Output - Data Line P7 TRACE_DATA_6 O Debug Trace Output - Data Line R8 TRACE_DATA_7 O Debug Trace Output - Data Line P8 TRACE_DATA_8 O Debug Trace Output - Data Line D14 TRACE_DATA_9 O Debug Trace Output - Data Line B14 TRACE_DATA_10 O Debug Trace Output - Data Line B15 TRACE_DATA_11 O Debug Trace Output - Data Line C9 TRACE_DATA_12 O Debug Trace Output - Data Line C8 TRACE_DATA_13 O Debug Trace Output - Data Line B9 TRACE_DATA_14 O Debug Trace Output - Data Line B8 TRACE_DATA_15 O Debug Trace Output - Data Line A9 WARM_RESET IO Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. Table 4-3. Signal Descriptions - Analog INTERFACE SIGNAL NAME PIN TYPE DESCRIPTION BALL NO. Transmitters TX1 O Single ended transmitter1 o/p B4 TX2 O Single ended transmitter2 o/p B6 Receivers RX1 I Single ended receiver1 i/p M2 RX2 I Single ended receiver2 i/p K2 RX3 I Single ended receiver3 i/p H2 RX4 I Single ended receiver4 i/p F2 Reset NRESET I Power on reset for chip. Active low R3 Reference Oscillator CLKP I Differential input ports for reference crystal C15 CLKM I D15 Reference clock OSC_CLKOUT O Reference clock output from clocking sub system after cleanup PLL (1.8V output voltage swing). A14 Bandgap voltage VBGAP O B10 Power supply VDDIN Power 1.2V digital power supply H15, N11, P15, R6 VIN_SRAM Power 1.2V power rail for internal SRAM G15 VNWA Power 1.2V power rail for SRAM array back bias P14 VIOIN Power I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply R10, R14, F15 VIOIN_18 Power 1.8V supply for CMOS IO R9 VIN_18CLK Power 1.8V supply for clock module B11 VIOIN_18DIFF Power 1.8V supply for LVDS port E15 VPP Power Voltage supply for fuse chain L13

4.4 Pin Multiplexing

Table 4-4. Pin Multiplexing (ABL0161 Package) ADDRESS REGISTE R NAME BALL NUMBER MUXMODE[15:During Power Up] SETTINGS During Power Up 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 0xFFFFEA00 P13 GPIO_12 SPI_HOST _INTR SPIB_cs_n 0xFFFFEA04 H13 GPIO_13 GPIO_0 PMIC_CLK OUT ePWM1b ePWM2a 0xFFFFEA08 J13 GPIO_16 GPIO_1 SYNC_OU T DMM_MU X_IN SPIB_cs_n SPIB_cs_n ePWM1SY NCI 0xFFFFEA0C D13 GPIO_19 SPIA_mosi CAN_FD_r x DSS_uart_ tx 0xFFFFEA10 E14 GPIO_20 SPIA_miso CAN_FD_t x 0xFFFFEA14 E13 GPIO_3 SPIA_clk CAN_rx DSS_uart_ tx 0xFFFFEA18 C13 GPIO_30 SPIA_cs_n CAN_tx 0xFFFFEA1C F13 GPIO_21 SPIB_mosi I2C_sda 0xFFFFEA20 G14 GPIO_22 SPIB_miso I2C_scl DSS_uart_ tx 0xFFFFEA24 F14 GPIO_5 SPIB_clk MSS_uarta _rx MSS_uartb _tx BSS_uart_ tx CAN_FD_r x 0xFFFFEA28 H14 GPIO_4 SPIB_cs_n MSS_uarta _tx MSS_uartb _tx BSS_uart_ tx QSPI_clk_ ext CAN_FD_t x 0xFFFFEA2C R13 GPIO_8 QSPI[0] SPIB_miso 0xFFFFEA30 N12 GPIO_9 QSPI[1] SPIB_mosi SPIB_cs_n 0xFFFFEA34 R14 GPIO_10 QSPI[2] CAN_FD_t x 0xFFFFEA38 P12 GPIO_11 QSPI[3] CAN_FD_r x 0xFFFFEA3C R12 GPIO_7 QSPI_clk SPIB_clk DSS_uart_ tx 0xFFFFEA40 P11 GPIO_6 QSPI_cs_n SPIB_cs_n 0xFFFFEA44 N7 nERROR_I N 0xFFFFEA48 N9 Warm_Res et 0xFFFFEA4C N6 nERROR_ OUT 0xFFFFEA50 P10 GPIO_17 TCK MSS_uartb _tx CAN_FD_t x 0xFFFFEA54 N10 GPIO_18 TMS BSS_uart_ tx CAN_FD_r x 0xFFFFEA58 R11 GPIO_23 TDI MSS_uarta _rx

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 Table 4-4. Pin Multiplexing (ABL0161 Package) (continued) ADDRESS REGISTE R NAME BALL NUMBER MUXMODE[15:During Power Up] SETTINGS During Power Up 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 0xFFFFEA5C N13 SOP[0] GPIO_24 TDO MSS_uarta _tx MSS_uartb _tx BSS_uart_ tx NDMM_EN 0xFFFFEA60 N8 GPIO_25 MCU_CLK OUT ePWM1a 0xFFFFEA64 K13 GPIO_26 GPIO_2 OSC_CLK OUT MSS_uartb _tx BSS_uart_ tx SYNC_OU T PMIC_CLK OUT 0xFFFFEA68 P9 SOP[2] GPIO_27 PMIC_CLK OUT ePWM1b ePWM2a 0xFFFFEA6C P4 GPIO_28 SYNC_IN MSS_uartb _rx DMM_MU X_IN SYNC_OU T 0xFFFFEA70 G13 SOP[1] GPIO_29 SYNC_OU T DMM_MU X_IN SPIB_cs_n SPIB_cs_n 0xFFFFEA74 N4 GPIO_15 rs232_rx MSS_uarta _rx BSS_uart_ tx MSS_uartb _rx CAN_FD_r x I2C_scl ePWM2a ePWM2b ePWM3a 0xFFFFEA78 N5 GPIO_14 rs232_tx MSS_uarta _tx MSS_uartb _tx BSS_uart_ tx CAN_FD_t x I2C_sda ePWM1a ePWM1b NDMM_EN ePWM2a 0xFFFFEA7C R4 TRACE_D ATA_0 GPIO_31 DMM0 MSS_uarta _tx 0xFFFFEA80 P5 TRACE_D ATA_1 GPIO_32 DMM1 0xFFFFEA84 R5 TRACE_D ATA_2 GPIO_33 DMM2 0xFFFFEA88 P6 TRACE_D ATA_3 GPIO_34 DMM3 ePWM3SY NCO 0xFFFFEA8C R7 TRACE_D ATA_4 GPIO_35 DMM4 ePWM2SY NCO 0xFFFFEA90 P7 TRACE_D ATA_5 GPIO_36 DMM5 MSS_uartb _tx 0xFFFFEA94 R8 TRACE_D ATA_6 GPIO_37 DMM6 BSS_uart_ tx 0xFFFFEA98 P8 TRACE_D ATA_7 GPIO_38 DMM7 DSS_uart_ tx 0xFFFFEA9C D14 TRACE_D ATA_8 GPIO_39 DMM8 CAN_FD_t x ePWM1SY NCI 0xFFFFEAA0 B14 TRACE_D ATA_9 GPIO_40 DMM9 CAN_FD_r x ePWM1SY NCO 0xFFFFEAA4 B15 TRACE_D ATA_10 GPIO_41 DMM10 ePWM3a 0xFFFFEAA8 C9 TRACE_D ATA_11 GPIO_42 DMM11 ePWM3b 0xFFFFEAAC C8 TRACE_D ATA_12 GPIO_43 DMM12 ePWM1a CAN_tx 0xFFFFEAB0 B9 TRACE_D ATA_13 GPIO_44 DMM13 ePWM1b CAN_rx 0xFFFFEAB4 B8 TRACE_D ATA_14 GPIO_45 DMM14 ePWM2a

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted.

5 Specifications

5.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDDIN 1.2 V digital power supply –0.5 1.4 V VIN_SRAM 1.2 V power rail for internal SRAM –0.5 1.4 V VNWA 1.2 V power rail for SRAM array back bias –0.5 1.4 V VIOIN I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. –0.5 3.8 V VIOIN_18 1.8 V supply for CMOS IO –0.5 2 V VIN_18CLK 1.8 V supply for clock module –0.5 2 V VIOIN_18DIFF 1.8 V supply for LVDS port –0.5 2 V VIN_13RF1 1.3 V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board. –0.5 1.45 V VIN_13RF2 –0.5 1.45 V VIN_13RF1 (1-V LDO bypass mode) Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. –0.5 1.4 V VIN_13RF2 (1-V Internal LDO bypass mode) –0.5 1.4 V VIN_18BB 1.8-V Analog baseband power supply –0.5 2 V VIN_18VCO supply 1.8-V RF VCO supply –0.5 2 V Input and output voltage range Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State) –0.3V VIOIN + 0.3 VDual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V (Transient Overshoot/Undershoot) VIOIN + 20% up to 20% of signal period CLKP, CLKM Input ports for reference crystal –0.5 2 V Clamp current Input or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O. –20 20 mA TJ Operating junction temperature range –40 125 ºC TSTG Storage temperature range after soldered onto PC board –55 150 ºC (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1000 V Charged-device model (CDM), per AEC Q100-011 ±250 (1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.

5.3 Power-On Hours (POH)(1)

CONDITION NOMINAL CVDD VOLTAGE (V) JUNCTION TEMPERATURE (Tj) POWER-ON HOURS [POH] (HOURS) 100% duty cycle 1.2 –40°C 600 (6%) 75°C 2000 (20%) 95°C 6500 (65%) 125°C 900 (9%)

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDDIN 1.2 V digital power supply 1.14 1.2 1.32 V VIN_SRAM 1.2 V power rail for internal SRAM 1.14 1.2 1.32 V VNWA 1.2 V power rail for SRAM array back bias 1.14 1.2 1.32 V VIOIN I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. 3.15 3.3 3.45 V 1.71 1.8 1.89 VIOIN_18 1.8 V supply for CMOS IO 1.71 1.8 1.9 V VIN_18CLK 1.8 V supply for clock module 1.71 1.8 1.9 V VIOIN_18DIFF 1.8 V supply for LVDS port 1.71 1.8 1.9 V VIN_13RF1 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board 1.23 1.3 1.36 V VIN_13RF2 1.23 1.3 1.36 V VIN_13RF1 (1-V Internal LDO bypass mode) Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. 0.95 1 1.05 V VIN_13RF2 (1-V Internal LDO bypass mode) 0.95 1 1.05 V VIN18BB 1.8-V Analog baseband power supply 1.71 1.8 1.9 V VIN_18VCO 1.8V RF VCO supply 1.71 1.8 1.9 V VIH Voltage Input High (1.8 V mode) 1.17 V Voltage Input High (3.3 V mode) 2.25 VIL Voltage Input Low (1.8 V mode) 0.63 V Voltage Input Low (3.3 V mode) 0.8 VOH High-level output threshold (IOH = 6 mA) 85%*VIOIN mV VOL Low-level output threshold (IOL = 6 mA) 350 mV CLKP,CLKM Voltage Input High 0.96 V Voltage Input Low 0.24

5.5 Power Supply Specifications

Table 5-1 describes the four rails from an external power supply block of the AWR1642 device. Table 5-1. Power Supply Rails Characteristics SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT IOS IN THE DEVICE

1.8 V Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, LVDS Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18IO LDO Output: VOUT_14SYNTH, VOUT_14APLL

1.3 V (or 1 V in internal

LDO bypass mode) Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution Input: VIN_13RF2, VIN_13RF1 LDO Output: VOUT_PA 3.3 V (or 1.8 V for 1.8 V I/O mode) Digital I/Os Input VIOIN

1.2 V Core Digital and SRAMs Input: VDDIN, VIN_SRAM

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated Table 5-2 lists tolerable ripple specifications for 1.3-V (1.0-V) and 1.8-V supply rails. Table 5-2. Ripple Specifications FREQUENCY (kHz) RF RAIL VCO/IF RAIL

1.0 V (INTERNAL LDO BYPASS)

(µVRMS) 1.3 V (µVRMS) 1.8 V (µVRMS) 137.5 7.76 648.73 83.41 275 5.83 76.48 21.27 550 3.44 22.74 11.43 1100 2.53 4.05 6.73 2200 11.29 82.44 13.39 4200 13.65 93.35 19.70 6600 22.91 117.78 29.63

5.6 Power Consumption Summary

Table 5-3 and Table 5-4 summarize the power consumption at the power terminals. Table 5-3. Maximum Current Ratings at Power Terminals PARAMETER SUPPLY NAME DESCRIPTION MIN TYP MAX UNIT Current consumption VDDIN, VIN_SRAM, VNWA Total current drawn by all nodes driven by 1.2V rail 1000 mA VIN_13RF1, VIN_13RF2 Total current drawn by all nodes driven by 1.3V rail 2000 VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO Total current drawn by all nodes driven by 1.8V rail 850 VIOIN Total current drawn by all nodes driven by 3.3V rail Table 5-4. Average Power Consumption at Power Terminals PARAMETER CONDITION DESCRIPTION MIN TYP MAX UNIT Average power consumption 1.0-V internal LDO bypass mode 1TX, 4RX Sampling: 3.2 MSps complex Transceiver, 25-ms frame time, 256 Chirps, 128 Samples/chirp, 8-μs interchirp time (50 duty cycle), DSP active 1.91 W 2TX, 4RX 2.05 1.3-V internal LDO enabled mode 1TX, 4RX 2.1 2TX, 4RX 2.27

ADVANCE□INFORMATION RX Gain (dB) NF (dB) IB P1dB (dBm) 24 26 28 30 32 34 36 38 40 42 44 46 48 13.5 -48 13.8 -44 14.1 -40 14.4 -36 14.7 -32 15 -28 15.3 -24 15.6 -20 NF (db) IB P1db (dBm) AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated (1) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of available HPF corners is summarized as follows: Available HPF Corner Frequencies (kHz) HPF1 HPF2 175, 235, 350, 700 350, 700, 1400, 2800 The filtering performed by the baseband chain is targeted to provide:

Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

5.7 RF Specification

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT Receiver Noise figure 76 to 77 GHz 15 dB 77 to 81 GHz 16 1-dB compression point –5 dBm Maximum gain step 48 dB Gain range 24 dB Gain step size 2 dB IQ gain mismatch 1 dB IQ phase mismatch 2 degree IF bandwidth(1) 5 MHz A2D sampling rate (real) 12.5 Msps A2D sampling rate (complex) 6.25 Msps A2D resolution 12 Bits Transmitter Output power 12 dBm Amplitude noise –145 dBc/Hz Clock subsystem Frequency range 76 81 GHz Ramp rate 100 MHz/µs Phase noise at 1-MHz offset 76 to 77 GHz –94 dBc/Hz 77 to 81 GHz –91 Figure 5-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed. Figure 5-1. Noise Figure, In-band P1dB vs Receiver Gain

5.8 CPU Specifications

over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT DSP Subsystem (C674 Family) Clock Speed 600 MHz L1 Code Memory 32 KB L1 Data Memory 32 KB L2 Memory 256 KB Master Controller Subsystem (R4F Family) Clock Speed 200 MHz Tightly Couple Memory - A (Program) 256 KB Tightly Coupled Memory - B (Data) 192 KB Shared Memory Shared L3 Memory 768 KB (1) N/A = not applicable (2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. (3) °C/W = degrees Celsius per watt. (4) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements A junction temperature of 125ºC is assumed.

5.9 Thermal Resistance Characteristics for FCBGA Package ABL0161

THERMAL METRICS(2) °C/W(3) (4) RΘJC Junction-to-case 4.92 RΘJB Junction-to-board 6.57 RΘJA Junction-to-free air 22.3 RΘJMA Junction-to-moving air N/A(1) PsiJT Junction-to-package top 4.92 PsiJB Junction-to-board 6.4

ADVANCE□INFORMATION Reference Clock Stabilization time ~5mS FUSE_SHIFT_EN PORZ_1P8V Controls HHV of IO PORZ_TOP/ GEN_TOP EFC_READY XTAL_DET_STAT XTAL_EN/ SLICER_EN SLICER_REF_CLK (CLKP+CLKM thru’ SLICER) LIMP_MODE_STATUS CPU CLK is REF CLK if STATUS is 1 ELSE INT_RCOSC_CLK if STATUS is 0 Reset Control to Top Digital and Analog Wake Up Done Reset Control to Digital Processor and Analog/RF Internal Signals Mentioned for reference only *Names are representative CPU_CLK ~400 cycles PORZ_CPU/ PORZ_DIG/ GEN_ANA

1 IF REF CLK is NOT PRESENT

XTAL STATUS 1 if XTAL FOUND/ ‘0’ if EXTERNAL CLK is FORCED ~5mS (VDDIN) (VIN_*) (VIOIN_18DIFF) (VIOIN) (NRESET) PMIC_OUT, SYNC_OUT, TDO 001 (Functional) CAN BE CHANGED. Includes ramping of all other supplies VIN_18BB, VIN_18CLK, VIN_13RF*,VIOIN_18DIFF MCU_CLK_OUT Includes ramping of VIOIN_18 External Signals 3mS (1) AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated

5.10 Timing and Switching Characteristics

5.10.1 Power Supply Sequencing and Reset Timing

The AWR1642 device expects all external voltage rails to be stable before reset is deasserted. Figure 5-2 describes the device wake-up sequence. (1) MCU_CLK_OUT in autonomous mode, where AWR1642 application is booted from the serial flash, MCU_CLK_OUT is not enabled by default by the device bootloader. Figure 5-2. Device Wake-up Sequence

ADVANCE□INFORMATION f 2 L f1 P f1 f 2 C C C C C C/c61 /c180 /c43 /c43 40 / 50 MHz XTALP XTALM C f1 C f2 C p AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated (1) The crystal manufacturer's specification must satisfy this requirement. (2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

5.10.2 Input Clocks and Oscillators

5.10.2.1 Clock Specifications

The AWR1642 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device pins. Figure 5-3 shows the crystal implementation. Figure 5-3. Crystal Implementation NOTE The load capacitors, Cf1 and Cf2 in Figure 5-3, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins. (1) Table 5-5 lists the electrical characteristics of the clock crystal. Table 5-5. Crystal Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT fP Parallel resonance crystal frequency 40, 50 MHz CL Crystal load capacitance 5 8 12 pF ESR Crystal ESR 50 Ω Temperature range Expected temperature range of operation –40 150 ºC Frequency tolerance Crystal frequency tolerance(1)(2) –50 50 ppm Drive level 50 200 µW

5.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

5.10.3.1 Peripheral Description

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Standard and MibSPI modules have the following features:

16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source (slave mode)
Each word transferred can have a unique format.
SPI I/Os not used in the communication can be used as digital input/output signals

5.10.3.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each. Table 5-7 to Table 5-10 assume the operating conditions stated in Table 5-6. Table 5-6. SPI Timing Conditions MIN TYP MAX UNIT Input Conditions tR Input rise time 1 3 ns tF Input fall time 1 3 ns Output Conditions CLOAD Output load capacitance 2 15 pF

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Specifications Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 (1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared ( where x= 0 or 1). (2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, please refer to the Technical Reference Manual. (3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Table 5-7. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT 1 tc(SPC)M Cycle time, SPICLK(4) 25 256tc(VCLK) ns 2(4) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 3(4) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 4(4) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 3 ns td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 3 5(4) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 10.5 ns tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 10.5 6(5) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 (C2TDELAY+2)*tc(VCLK ) – 7.5 (C2TDELAY+2) * tc(VCLK) + 7 ns CSHOLD = 1 (C2TDELAY +3) * tc(VCLK) – 7.5 (C2TDELAY+3) * tc(VCLK) + 7 Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 (C2TDELAY+2)*tc(VCLK ) – 7.5 (C2TDELAY+2) * tc(VCLK) + 7 CSHOLD = 1 (C2TDELAY +3) * tc(VCLK) – 7.5 (C2TDELAY+3) * tc(VCLK) + 7 7(5) tT2CDELAY Hold time, SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 7 0.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5 ns Hold time, SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 7 0.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated Specifications Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 (1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ). (2) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, please refer to the Technical Reference Manual. (3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Table 5-9. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT 1 tc(SPC)M Cycle time, SPICLK(4) 25 256tc(VCLK) ns 2(4) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 3(4) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 4 0.5tc(SPC)M + 4 4(4) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 3 ns td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 3 5(4) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0) 0.5tc(SPC)M – 10.5 ns tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1) 0.5tc(SPC)M – 10.5 6(5) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 ns CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2)*tc( VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5 CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3)*tc( VCLK) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) + 7.5 7(5) tT2CDELAY Hold time, SPICLK low until CS inactive (clock polarity = 0) (T2CDELAY + 1) *tc(VCLK) – 7.5 (T2CDELAY + 1) *tc(VCLK) + 7 ns Hold time, SPICLK high until CS inactive (clock polarity = 1) (T2CDELAY + 1) *tc(VCLK) – 7.5 (T2CDELAY + 1) *tc(VCLK) + 7

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated (1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ). (2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively. (3) tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, please refer to the Technical Reference Manual. (4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns. (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

5.10.3.3 SPI Slave Mode I/O Timings

Table 5-11. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT 1 tc(SPC)S Cycle time, SPICLK(4) 25 ns 2(5) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 10 ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 10 3(5) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 10 ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 10 4(5) td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) 10 ns td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) 10 5(5) th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0) 2 ns th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1) 2 (1) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Table 5-12. SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output) NO. MIN TYP MAX UNIT 6(1) tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 3 ns tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 3 7(1) th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0 ns th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0

ADVANCE□INFORMATION CS CLK MOSI MISO IRQ 0x56780x1234 0x4321 CRC 0xDCBA 0xABCD CRC 0x8765 16 bytes

2 SPI clocks

5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)

Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock. 2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI. Figure 5-10 shows the SPI communication timing of the typical interface protocol. Figure 5-10. SPI Communication

ADVANCE□INFORMATION twH1 LVDS_CLK twL1 twH2 twL2 Calculation showing tw parameters: Freq = 900MHz, Period = 1.11ns At 50% twH1/twL1 = 1.11ns/2 = 0.55ns Rise time = Fall time = 200ps (as per LVDS IO spec @1pF load) twH2/twL2 = (1.11ns-2*200ps)/2 = 0.35ns 200ps 200ps 200ps LVDS_CLK LVDS_TXP/M LVDS_FRCLKP/M 1100ps Clock Jitter = 6sigma = 60ps LVDS_FRCLKP/M LVDS_TXP/M Data bitwidth LVDS_CLKP/M AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated

5.10.4 LVDS Interface Configuration

The AWR1642 supports four differential LVDS IOs/Lanes. The lane configuration supported is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:

900 Mbps (450 MHz DDR Clock)
600 Mbps (300 MHz DDR Clock)
450 Mbps (225 MHz DDR Clock)
400 Mbps (200 MHz DDR Clock)
300 Mbps (150 MHz DDR Clock)
225 Mbps (112.5 MHz DDR Clock)
150 Mbps (75 MHz DDR Clock) Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data. Figure 5-11. LVDS Interface Lane Configuration And Relative Timings

5.10.4.1 LVDS Interface Timings

Figure 5-12. Timing Parameters

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated Table 5-13. LVDS Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT twH1 / twL1 0.55 ns twH2 / twL2 0.35 ns Duty Cycle Requirements max 1 pF lumped capacitive load on LVDS lanes 48% 52% VOH 1475 mV VOL 925 mV Output Differential Voltage peak-to-peak single-ended with 100 Ω resistive load between differential pairs 250 450 mV Output Offset Voltage 1125 1275 mV

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated (1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate). (2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

5.10.5 General-Purpose Input/Output

Table 5-14 lists the switching characteristics of output timing relative to load capacitance. Table 5-14. Switching Characteristics for Output Timing versus Load Capacitance (CL)(1)(2) PARAMETER TEST CONDITIONS VIOIN = 1.8V VIOIN = 3.3V UNIT tr Max rise time Slew control = 0 CL = 20 pF 2.878 3.013 nsCL = 50 pF 6.446 6.947 CL = 75 pF 9.43 10.249 tf Max fall time CL = 20 pF 2.827 2.883 nsCL = 50 pF 6.442 6.687 CL = 75 pF 9.439 9.873 tr Max rise time Slew control = 1 CL = 20 pF 3.307 3.389 nsCL = 50 pF 6.77 7.277 CL = 75 pF 9.695 10.57 tf Max fall time CL = 20 pF 3.128 3.128 nsCL = 50 pF 6.656 6.656 CL = 75 pF 9.605 9.605

5.10.6 Controller Area Network Interface (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable serial communication or multiplexed wiring. The DCAN has the following features:

Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbps
Configurable Message objects
Individual identifier masks for each message object
Programmable FIFO mode for message objects
Suspend mode for debug support
Programmable loop-back modes for self-test operation
Direct access to Message RAM in test mode
Supports two interrupt lines - Level 0 and Level 1
Automatic Message RAM initialization (1) These values do not include rise/fall times of the output buffer. Table 5-15. Dynamic Characteristics for the DCANx TX and RX Pins PARAMETER MIN TYP MAX UNIT td(CAN_tx) Delay time, transmit shift register to CAN_tx pin(1) 15 ns td(CAN_rx) Delay time, CAN_rx pin to receive shift register(1) 10 ns

5.10.7 Controller Area Network - Flexible Data-rate (CAN-FD)

The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices can coexist on the same network without any conflict. The CAN-FD has the following features:

Conforms with CAN Protocol 2.0 A, B and ISO 11898-1
Full CAN FD support (up to 64 data bytes per frame)
AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 11-bit filter elements
Internal Loopback mode for self-test
Mask-able interrupts, two interrupt lines
Two clock domains (CAN clock / Host clock)
Parity / ECC support - Message RAM single error correction and double error detection (SECDED) mechanism
Full Message Memory capacity (4352 words). (1) These values do not include rise/fall times of the output buffer. Table 5-16. Dynamic Characteristics for the DCANx TX and RX Pins PARAMETER MIN TYP MAX UNIT td(CAN_FD_tx) Delay time, transmit shift register to CAN_FD_tx pin(1) 15 ns td(CAN_FD_rx) Delay time, CAN_FD_rx pin to receive shift register(1) 10 ns

5.10.8 Serial Communication Interface (SCI)

The SCI has the following features:

Standard universal asynchronous receiver-transmitter (UART) communication
Standard non-return to zero (NRZ) format
Double-buffered receive and transmit functions
Asynchronous or iso-synchronous communication modes with no CLK pin
Capability to use Direct Memory Access (DMA) for transmit and receive data
Two external pins: RS232_RX and RS232_TX Table 5-17. SCI Timing Requirements MIN TYP MAX UNIT f(baud) Supported baud rate at 20 pF 921.6 kHz

5.10.9 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus™ . This module will support any slave or master I2C compatible device. The I2C has the following features:

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398 393 40011) – Bit/Byte format transfer – 7-bit and 10-bit device addressing modes – General call – START byte – Multi-master transmitter/ slave receiver mode – Multi-master receiver/ slave transmitter mode – Combined master transmit/receive and receive/transmit mode – Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode NOTE This I2C module does not support:
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second byte every time it sends the slave address first byte)

ADVANCE□INFORMATION SDA SCL tw(SDAH) tw(SCLL) tw(SCLH) tw(SP) th(SCLL-SDAL) th(SDA-SCLL) th(SCLL-SDAL) tsu(SCLH-SDAL) tf(SCL)tc(SCL) tr(SCL) tsu(SCLH-SDAH) Stop Start Repeated Start Stop tsu(SDA-SCLH) AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal. (3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed. Table 5-18. I2C Timing Requirements(1) STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX tc(SCL) Cycle time, SCL 10 2.5 μs tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 μs th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 μs tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs tw(SCLH) Pulse duration, SCL high 4 0.6 μs tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 μs th(SCLL-SDA) Hold time, SDA valid after SCL low 0 3.45(1) 0 0.9 μs tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 μs tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 μs tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns Cb (2)(3) Capacitive load for each bus line 400 400 pF Figure 5-13. I2C Timing Diagram NOTE

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).

5.10.10 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI™ ) module is a kind of SPI module that allows single, dual, or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash memories. The QSPI supports the following features:

Programmable clock divider
Six-pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles Table 5-20 and Table 5-21 assume the operating conditions stated in Table 5-19. Table 5-19. QSPI Timing Conditions MIN TYP MAX UNIT Input Conditions tR Input rise time 1 3 ns tF Input fall time 1 3 ns Output Conditions CLOAD Output load capacitance 2 15 pF (1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation. (2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non- standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI sevices that launch data on the falling edge in Clock Mode 0. (3) P = SCLK period in ns. Table 5-20. Timing Requirements for QSPI Input (Read) Timings(1)(2) MIN TYP MAX UNIT tsu(D-SCLK) Setup time, d[3:0] valid before falling sclk edge 6.2 ns th(SCLK-D) Hold time, d[3:0] valid after falling sclk edge 1 ns tsu(D-SCLK) Setup time, final d[3:0] bit valid before final falling sclk edge 6.2 – P(3) ns th(SCLK-D) Hold time, final d[3:0] bit valid after final falling sclk edge 1 + P(3) ns

ADVANCE□INFORMATION cs sclk d[0] d[3:1] Bit n-1 Bit n-2 Bit 1 Bit 0 PHA=0 POL=0 Command Command Read Data Read Data Bit 1 Bit 0 Read Data Read Data Q7 Q9 Q2 Q3 SPRS85v_TIMING_OSPI1_02 Q12 Q13 Q12 Q13 Q12 Q13 Q12 Q13 AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated (1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual. (2) P = SCLK period in ns. (3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2 Table 5-21. QSPI Switching Characteristics NO. PARAMETER MIN TYP MAX UNIT Q1 tc(SCLK) Cycle time, sclk 25 ns Q2 tw(SCLKL) Pulse duration, sclk low Y*P – 3(1)(2) ns Q3 tw(SCLKH) Pulse duration, sclk high Y*P – 3(1)(1) ns Q4 td(CS-SCLK) Delay time, sclk falling edge to cs active edge –M*P – 1(1)(3) –M*P + 2.5(1)(3) ns Q5 td(SCLK-CS) Delay time, sclk falling edge to cs inactive edge N*P – 1(1)(3) N*P + 2.5(1)(3) ns Q6 td(SCLK-D1) Delay time, sclk falling edge to d[1] transition –3.5 7 ns Q7 tena(CS-D1LZ) Enable time, cs active edge to d[1] driven (lo-z) –P – 4(3) –P +1(3) ns Q8 tdis(CS-D1Z) Disable time, cs active edge to d[1] tri-stated (hi-z) –P – 4(3) –P +1(3) ns Q9 td(SCLK-D1) Delay time, sclk first falling edge to first d[1] transition (for PHA = 0 only) –3.5 – P(3) 7 – P(3) ns Figure 5-14. QSPI Read (Clock Mode 0)

ADVANCE□INFORMATION cs sclk d[0] d[3:1] Bit n-1 Bit n-2 Bit 1 Bit 0 PHA=0 POL=0 Command Command Write Data Write Data Q2 Q3 Q6 Q6 SPRS85v_TIMING_OSPI1_04 Q8Q9 Q6 AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated Figure 5-15. QSPI Write (Clock Mode 0)

ADVANCE□INFORMATION tr(ETM) th(ETM) tl(ETM) tf(ETM) tcyc(ETM) AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated

5.10.11 ETM Trace Interface

Table 5-23 and assume the recommended operating conditions stated in Table 5-22. Table 5-22. ETMTRACE Timing Conditions MIN TYP MAX UNIT Output Conditions CLOAD Output load capacitance 2 20 pF Table 5-23. ETM TRACE Switching Characteristics NO. PARAMETER MIN TYP MAX UNIT 1 tcyc(ETM) Cycle time, TRACECLK period 20 ns 2 th(ETM) Pulse Duration, TRACECLK High 9 ns 3 tl(ETM) Pulse Duration, TRACECLK Low 9 ns 4 tr(ETM) Clock and data rise time 3.3 ns 5 tf(ETM) Clock and data fall time 3.3 ns td(ETMTRAC ECLKH- ETMDATAV) Delay time, ETM trace clock high to ETM data valid 1 7 ns td(ETMTRAC ECLKl- ETMDATAV) Delay time, ETM trace clock low to ETM data valid 1 7 ns Figure 5-16. ETMTRACECLKOUT Timing Figure 5-17. ETMDATA Timing

ADVANCE□INFORMATION DMMSYNC DMMCLK DMMDA T A tssu(DMM) tsh(DMM) tdsu(DMM) tdh(DMM) tcyc(DMM) tr tfth(DMM) tl(DMM) AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 SpecificationsCopyright © 2017, Texas Instruments Incorporated

5.10.12 Data Modification Module (DMM)

A Data Modification Module (DMM) gives the ability to write external data into the device memory. The DMM has the following features:

Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the RAM trace port [RTP] module)
Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined by direct data mode of RTP module)
Configurable port width (1, 2, 4, 8, 16 pins)
Up to 65 Mbit/s pin data rate Table 5-24. DMM Timing Requirements MIN TYP MAX UNIT tcyc(DMM) Clock period 15.4 ns tR Clock rise time 1 3 ns tF Clock fall time 1 3 ns th(DMM) High pulse width 6 ns tl(DMM) Low pulse width 6 ns tssu(DMM) SYNC active to clk falling edge setup time 2 ns tsh(DMM) DMM clk falling edge to SYNC deactive hold time 3 ns tdsu(DMM) DATA to DMM clk falling edge setup time 2 ns tdh(DMM) DMM clk falling edge to DATA hold time 3 ns Figure 5-18. DMMCLK Timing Figure 5-19. DMMDATA Timing

ADVANCE□INFORMATION TCK TDO TDI/TMS 1a 1b SPRS91v_JT AG_01 AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Specifications Copyright © 2017, Texas Instruments Incorporated

5.10.13 JTAG Interface

Table 5-26 and Table 5-27 assume the operating conditions stated in Table 5-25. Table 5-25. JTAG Timing Conditions MIN TYP MAX UNIT Input Conditions tR Input rise time 1 3 ns tF Input fall time 1 3 ns Output Conditions CLOAD Output load capacitance 2 15 pF Table 5-26. Timing Requirements for IEEE 1149.1 JTAG NO. MIN TYP MAX UNIT 1 tc(TCK) Cycle time TCK 66.66 ns 1a tw(TCKH) Pulse duration TCK high (40% of tc) 26.67 ns 1b tw(TCKL) Pulse duration TCK low(40% of tc) 26.67 ns tsu(TDI-TCK) Input setup time TDI valid to TCK high 2.5 ns tsu(TMS-TCK) Input setup time TMS valid to TCK high 2.5 ns th(TCK-TDI) Input hold time TDI valid from TCK high 18 ns th(TCK-TMS) Input hold time TMS valid from TCK high 18 ns Table 5-27. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER MIN TYP MAX UNIT 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 25 ns Figure 5-20. JTAG Timing

ADVANCE□INFORMATION Serial Flash interface Optional External MCU interface PMIC control Primary communication interfaces (automotive) For debug JTAG for debug/ development High-speed ADC output interface (for recording) High-speed input for hardware-in-loop verification IF ADC Digital Front End (Decimation filter chain) LNA IF ADCLNA IF ADCLNA IF ADCLNA PA PA Synth (20 GHz) Ramp Generatorx4 Osc. GPADC VMON Temp Cortex-R4F @ 200-MHz (User programmable) Prog RAM (256kB*) Data RAM (192kB*) Boot ROM QSPI SPI SPI / I2C Debug UARTs DCAN DMA Test/ Debug ADC Buffer LVDS RF/Analog subsystem Master subsystem (Customer programmed) * Up to 512KB of Radar Data Memory can be switched to the Master R4F if required DSP subsystem (Customer programmed) Mailbox Bus Matrix HILC674x DSP @600 MHz L1P (32KB) L1D (32KB) (256KB) DMA CRC Radar Data Memory (L3) 768KB* RF Control/ BIST CAN-FD Copyright © 2017, Texas Instruments Incorporated AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Detailed DescriptionCopyright © 2017, Texas Instruments Incorporated

6 Detailed Description

6.1 Overview

The AWR1642 device includes the entire Millimeter Wave blocks and analog baseband signal chain for two transmitters and four receivers, as well as a customer-programmable MCU. This device is applicable as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity and application code size. These could be cost-sensitive automotive applications that are evolving from 24 GHz narrowband implementation and some emerging simple ultra-short-range radar applications. Typical application examples for this device include basic Blind Spot Detect, Parking Assist, and so forth. In terms of scalability, the AWR1642 device could be paired with a low-end external MCU, to address more complex applications that might require additional memory for larger application software footprint and faster interfaces. Because the AWR1642 device also provides high speed data interfaces like Serial- LVDS, it is suitable for interfacing with more capable external processing blocks. Here system designers can choose the AWR1642 to provide raw ADC data.

6.2 Functional Block Diagram

6.3 Subsystems

6.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit channels can be operated up to a maximum of two at a time (simultaneously) for transmit beamforming purpose as required; whereas the four receive channels can all be operated simultaneously.

ADVANCE□INFORMATION Self Test RESYNTH MULT PA EnvelopeTX Phase Mod.ADCs Timing Engine Approx. 1 GHz (fixed clock domain) Lock Detect SoC Clock CLK Detect Clean- Up PLL XO/ Slicer RX LOTX LO SYNCIN REFOUT 40 and 50 MHz Lock Detect AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Detailed Description Copyright © 2017, Texas Instruments Incorporated

6.3.1.1 Clock Subsystem

The AWR1642 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X4 multiplier to create the required frequency in the 76- to 81-GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor operation. The clean-up PLL also provides a reference clock for the host processor after system wakeup. The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the quality of the generated clock. Figure 6-1 describes the clock subsystem. Figure 6-1. Clock Subsystem

ADVANCE□INFORMATION Self Test ChipPackage PCB GSG /c87 Loopback Path DAC /c68/c83M /c68/c83M RSSII Q LO Saturation Detect DAC Decimation Image Rejection ADC BufferI/Q Correction Self Test Chip /c68/c70 0 or 180 (from Timing Engine) /c176 Loopback Path LO Package PCB 12 dBm at 50 /c87 AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Detailed DescriptionCopyright © 2017, Texas Instruments Incorporated

6.3.1.2 Transmit Subsystem

The AWR1642 transmit subsystem consists of two parallel transmit chains, each with independent binary phase and amplitude control. The device supports binary phase modulation for MIMO radar and interference mitigation. Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also support programmable backoff for system optimization. Figure 6-2 describes the transmit subsystem. Figure 6-2. Transmit Subsystem (Per Channel)

6.3.1.3 Receive Subsystem

The AWR1642 receive subsystem consists of four parallel channels. A single receive channel consists of an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational at the same time an individual power-down option is also available for system optimization. Unlike conventional real-only receivers, the AWR1642 device supports a complex baseband architecture, which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver channel. The AWR1642 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff frequencies above 350 kHz and can support bandwidths up to 5 MHz. Figure 6-3 describes the receive subsystem. Figure 6-3. Receive Subsystem (Per Channel)

ADVANCE□INFORMATION DSP Interconnect ± 128 bit @ 200 MHz Master Interconnect Interconnect ADC Buffer Data Handshake Memory CRC LVDS DSP EDMA MSS DMA HIL JTAG CRC HIL Master R4F ROM TCM A TCM B L1P L1d Mail Box SPI UART 12C QSPI CAN FD CAN PWM, PMIC CLK BSS Interconnect Unified 128KB x 2 32KB 32KB 32 KB 32 KB 192KB 256KB Cache/ RAM 768KB (static sharing with R4F Space) AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Detailed Description Copyright © 2017, Texas Instruments Incorporated

6.3.2 Processor Subsystem

Figure 6-4. Processor Subsystem Figure 6-4 shows the block diagram for customer programmable processor subsystems in the AWR1642 device. At a high level there are two customer programmable subsystems, as shown separated by a dotted line in the diagram. Left hand side shows the DSP Subsystem which contains TI's high- performance C674x DSP, a high-bandwidth interconnect for high performance (128-bit, 200MHz) and associated peripherals – four DMAs for data transfer, LVDS interface for Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine, and data handshake memory (additional memory provided on interconnect). The right-hand side of the diagram shows the Master subsystem. Master subsystem as name suggests is the master of the device and controls all the device peripherals and house-keeping activities of the device. Master subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and house- keeping components such as DMAs, CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking module, PWM, and others) connected to Master Interconnect through Peripheral Central Resource (PCR interconnect). Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748. HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the captured data from outside into the device without involving the RF subsystem. HIL on master SS is for controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL modules uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of the two.

6.3.3 Automotive Interface

The AWR1642 communicates with the automotive network over the following main interfaces:

CAN (2 interfaces available, one of them being CAN-FD)

6.3.4 Master Subsystem Cortex-R4F Memory Map

Table 6-1 shows the master subsystem, Cortex-R4F memory map. NOTE There are separate Cortex-R4F addresses and DMA MSS addresses for the master subsystem. See the Technical Reference Manual for a complete list. Table 6-1. Master Subsystem, Cortex-R4F Memory Map Name Frame Address (Hex) Size Description Start End CPU Tightly-Coupled Memories TCMA ROM 0x0000_0000 0x0001_FFFF 128 KiB Program ROM TCM RAM-A 0x0020_0000 0x0023_FFFF (or 0x0027_FFFF)

512 KiB 256/512KB based on variant

TCM RAM-B 0x0800_0000 0x0802_FFFF 192 KiB Data RAM S/W Scratch Pad Memory SW_ Buffer 0x0C20_0000 0x0C20_1FFF 8 KiB S/W Scratchpad memory System Peripherals Mail Box MSS<->RADARSS 0xF060_1000 0xF060_17FF 2 KiB RADARSS to MSS mailbox memory space 0xF060_2000 0xF060_27FF MSS to RADARSS mailbox memory space 0xF060_8000 0xF060_80FF 188 B MSS to RADARSS mailbox Configuration registers 0xF060_8060 0xF060_86FF RADARSS to MSS mailbox Configuration registers Mail Box MSS<->DSPSS 0xF060_4000 0xF060_47FF 2 KiB DSPSS to MSS mailbox memory space 0xF060_5000 0xF060_57FF MSS to DSPSS mailbox memory space 0xF060_8400 0xF060_84FF 188 B MSS to DSPSS mailbox Configuration registers 0xF060_8300 0xF060_83FF DSPSS to MSS mailbox Configuration registers Mail Box RADARSS<- >DSPSS 0xF060_6000 0xF060_67FF 2 KiB RADARSS to DSPSS mailbox memory space 0xF060_7000 0xF060_7FFF DSPSS to RADARSS mailbox memory space 0xF060_8200 0xF060_82FF 188 B RADARSS to DSPSS mailbox Configuration registers 0xF060_8100 0xF060_81FF DSPSS to RADARSS mailbox Configuration registers PRCM and Control Module 0xFFFF_E100 0xFFFF_E2FF 756 B TOP Level Reset, Clock management registers 0xFFFF_FF00 0xFFFF_FFFF 256 B MSS Reset, Clock management registers 0xFFFF_EA00 0xFFFF_EBFF 512 KiB IO Mux module registers 0xFFFF_F800 0xFFFF_FBFF 352 B General purpose control registers GIO 0xFFF7_BC00 0xFFF7_BDFF 180 B GIO module configuration registers DMA-1 0xFFFF_F000 0xFFFF_F3FF 1 KiB DMA-1 module configuration registers DMA-2 0xFCFF_F800 0xFCFF_FBFF 1 KiB DMA-2 module configuration registers DMM-1 0xFCFF_F700 0xFCFF_F7FF 472 B DMM-1 module configuration registers DMM-2 0xFCFF_F600 0xFCFF_F6FF 472 B DMM-2 module configuration registers VIM 0xFFFF_FD00 0xFFFF_FEFF 512 B VIM module configuration registers RTI-A/WD 0xFFFF_FC00 0xFFFF_FCFF 192 B RTI-A module configuration registers RTI-B 0xFFFF_EE00 0xFFFF_EEFF 192 B RTI-B module configuration registers Serial Interfaces and Connectivity QSPI 0xC000_0000 0xC07F_FFFF 8 MB QSPI –flash memory space 0xC080_0000 0xC0FF_FFFF 116 B QSPI module configuration registers MIBSPI-A 0xFFF7_F400 0xFFF7_F5FF 512 B MIBSPI-A module configuration registers

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Detailed Description Copyright © 2017, Texas Instruments Incorporated Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued) Name Frame Address (Hex) Size Description Start End MIBSPI-B 0xFFF7_F600 0xFFF7_F7FF 512 B MIBSPI-B module configuration registers SCI-A 0xFFF7_E500 0xFFF7_E5FF 148 B SCI-A module configuration registers SCI-B 0xFFF7_E700 0xFFF7_E7FF 148 B SCI-B module configuration registers CAN 0xFFF7_DC00 0xFFF7_DDFF 512 B CAN module configuration registers CAN_FD(MCAN) 0xFFF7_C800 0xFFF7_CFFF 768 B CAN-FD module configuration registers 0xFFF7_A000 0xFFF7_A1FF 452 B MCAN ECC module registers I2C 0xFFF7_D400 0xFFF7_D4FF 112 B I2C module configuration registers Interconnects PCR-1 0xFFF7_8000 0xFFF7_87FF 1 KiB PCR-1 interconnect configuration port PCR-2 0xFCFF_1000 0xFCFF_17FF 1 KiB PCR-2 interconnect configuration port Safety Modules CRC 0xFE00_0000 0xFEFF_FFFF 16 KiB CRC module configuration registers PBIST 0xFFFF_E400 0xFFFF_E5FF 464 B PBIST module configuration registers STC 0xFFFF_E600 0xFFFF_E7FF 284 B STC module configuration registers DCC-A 0xFFFF_EC00 0xFFFF_ECFF 44 B DCC-A module configuration registers DCC-B 0xFFFF_F400 0xFFFF_F4FF 44 B DCC-B module configuration registers ESM 0xFFFF_F500 0xFFFF_F5FF 156 B ESM module configuration registers CCMR4 0xFFFF_F600 0xFFFF_F6FF 136 B CCMR4 module configuration registers Security Modules Crypto 0xFD00_0000 0XFDFF_FFFF 3 KiB Crypto module configuration registers Other Subsystems DSS_TPTC0 0x5000 0000 0x5000 0317 792 B TPTC0 module configuration space DSS_REG 0x5000 0400 0x5000 075F 864 B DSPSS control module registers DSS_TPTC1 0x5000 0800 0x5000 0B17 792 B TPTC1 module configuration space DSS_REG2 0x5000 0C00 0x5000 0EA3 676 B DSPSS control module registers DSS_TPCC0 0x5001 0000 0x5001 3FFF 16 KB TPCC0 module configuration space DSS_RTIA/WDT 0x5002 0000 0x5002 00BF 192 B DSS_RTIA/WDT configuration space DSS_SCI 0x5003 0000 0x5003 0093 148 B SCI memory space DSS_STC 0x5004 0000 0x5004 011B 284 B STC module configuration space DSS_CBUFF 0x5007 0000 0x5007 0233 564 B Common Buffer module configuration registers DSS_TPTC2 0x5009 0000 0x5009 0317 792 B TPTC2 module configuration space DSS_TPTC3 0x5009 0400 0x5009 0717 792 B TPTC3 module configuration space DSS_TPCC1 0x500A 0000 0x500A 3FFF 16 KB TPCC1 module configuration space DSS_ESM 0x500D 0000 0x500D 005B 92 B ESM module configuration registers DSS_RTIB 0x500F 0000 0x500F 00BF 192 B RTI-B module configuration registers DSS_L3RAM Shared memory 0x5100 0000 0x511F FFFF 2 MB L3 shared memory space DSS_ADCBUF Buffer 0x5200 0000 0x5200 7FFF 32 KB ADC buffer memory space DSS_CBUFF_FIFO 0x5202 0000 0x5202 3FFF 16 KB Common buffer FIFO space DSS_HSRAM1 0x5208 0000 0x5208 7FFF 32 KB Handshake memory space DSS_DSP_L2_UMA 0x577E 0000 0x577F FFFF 128 KB L2 RAM space DSS_DSP_L2_UMA 0x5780 0000 0x5781 FFFF 128 KB L2 RAM space DSS_DSP_L1P 0x57E0 0000 0x57E0 7FFF 32 KB L1 program memory space DSS_DSP_L1D 0x57F0 0000 0x57F0 7FFF 32 KB L1 data memory space

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Detailed DescriptionCopyright © 2017, Texas Instruments Incorporated Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued) Name Frame Address (Hex) Size Description Start End Peripheral Memories (System and Nonsystem) CAN RAM 0xFF1E_0000 0xFF1F_FFFF 128 KB CAN RAM memory space CAN-FD RAM 0xFF50_0000 0xFF51_FFFF 68 KB CAN-FD RAM memory space DMA1 RAM 0xFFF8_0000 0xFFF8_0FFF 4 KB DMA1 RAM memory space DMA2 RAM 0xFCF8 1000 0xFCF8_0FFF 4 KB DMA2 RAM memory space VIM RAM 0xFFF8_2000 0xFFF8_2FFF 2 KB VIM RAM memory space MIBSPIB-TX RAM 0xFF0C_0000 0xFF0C_01FF 0.5 KB MIBSPIB-TX RAM memory space MIBSPIB-RX RAM 0xFF0C_0200 0xFF0C_03FF 0.5 KB MIBSPIB-RX RAM memory space MIBSPIA-TX RAM 0xFF0E_0000 0xFF0E_01FF 0.5 KB MIBSPIA-TX RAM memory space MIBSPIA- RX RAM 0xFF0E_0200 0xFF0E_03FF 0.5 KB MIBSPIA- RX RAM memory space Debug Modules Debug subsystem 0xFFA0_0000 0xFFAF_FFFF 244 KiB Debug subsystem memory space and registers

6.3.5 DSP Subsystem Memory Map

Table 6-2 shows the DSP C674x memory map. Table 6-2. DSP C674x Memory Map Name Frame Address (Hex) Size Description Start End DSP Memories DSP_L1D 0x00F0_0000 0x00F0_7FFF 32 KiB L1 data memory space DSP_L1P 0x00E0_0000 0x00E0_7FFF 32 KiB L1 program memory space DSP_L2_UMAP0 0x0080_0000 0x0081_FFFF 128 KiB L2 RAM space DSP_L2_UMAP1 0x007E_0000 0x007F_FFFF 128 KiB L2 RAM space EDMA TPCC0 0x0201_0000 0x0201_3FFF 16 KiB TPCC0 module configuration space TPCC1 0x020A_0000 0x020A_3FFF 16 KiB TPCC1 module configuration space TPTC0 0x0200 0000 0x0200 03FF 1 KiB TPTC0 module configuration space TPTC1 0x0200 0800 0x0200 0BFF 1 KiB TPTC1 module configuration space TPTC2 0x0209_0000 0x0209_03FF 1 KiB TPTC2 module configuration space TPTC3 0x0209_0400 0x0209_07FF 1 KiB TPTC3 module configuration space Control Registers DSS_REG 0x0200_0400 0x0200_07FF 864 B DSPSS control module registers DSS_REG2 0x0200_0C00 0x0200_0FFF 624 B DSPSS control module registers System Memories ADC Buffer 0x2100_0000 0x2100_7FFC 32 KiB ADC buffer memory space CBUFF-FIFO 0x2102_0000 0x2102_3FFC 16 KiB Common buffer FIFO space L3-Shared memory 0x2000_0000 0x201F_FFFF 2 MB L3 shared memory space

6.4 Other Subsystems

6.4.1 ADC Channels (Service) for User Application

The AWR1642 device includes provision for an ADC service for user application, where the GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2, ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

ADVANCE□INFORMATION GPADCANALOG TEST 1-4, ANAMUX VSENSE AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Detailed DescriptionCopyright © 2017, Texas Instruments Incorporated

ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST subsystem. This API could be linked with the user application running on the Master R4.
BIST subsystem firmware will internally schedule these measurements along with other RF and Analog monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the readings will be reported for each of the monitored voltages. GPADC Specifications:
625 Ksps SAR ADC
0 to 1.8V input range
10-bit resolution and ENOB of ~9 bits.
For 5 out of the 6 inputs, an optional internal buffer (0.4-1.4V input range) is available. Without the buffer, the ADC has a switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic capacitance. [for ADC channel mapped to B12, the internal buffer is not available] Figure 6-5. ADC Path (1) Outside of given range, the buffer output will become nonlinear. Table 6-3. GP-ADC Parameter over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITION MIN TYP MAX UNIT ADC supply/reference voltage 1.8 ± 1% V ADC input voltage range 0 1.8 V ADC resolution 10 bit ADC STND 100 kHz input frequency 47 dB ADC offset error –5 5 LSB ADC gain error –5 5 LSB ADC DNL –1 3.5 LSB ADC INL –2.5 2.5 LSB ADC sample rate 625 Ksps ADC sampling time 400 ns ADC internal capacitance sampling 7 pF parasitic 12 ADC leakage current 3 µA Input buffer input range(1) 0.4 1.4 V Input buffer input capacitance 0.5 pF

7 Monitoring and Diagnostics

7.1 Monitoring and Diagnostic Mechanisms

Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR1642. Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 S No Feature Description Boot time LBIST For Master R4F Core and associated VIM AWR1642 architecture supports hardware logic BIST (LBIST) engine self-test Controller (STC). This logic is used to provide a very high diagnostic coverage (>90%) on the Master R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level. LBIST for the CPU and VIM is triggered by Bootloader at the boot time, before handing over the control to the downloaded application. CPU stays there in while loop and does not proceed further if a fault is identified. Periodic LBIST is not supported.

2 Boot time PBIST for Master

Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and TCMB1. AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the implemented Master R4F TCMs at a transistor level. PBIST for TCM memories is triggered by Bootloader at the boot time before starting download of application from Flash or peripheral interface. CPU stays there in while loop and does not proceed further if a fault is identified.

3 End to End ECC for Master

TCMs diagnostic is supported by Single error correction double error detection (SECDED) ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64- bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU can be configured to have predetermined response (Ignore or Abort generation) to single and double bit error conditions.

4 Master R4F TCM bit

Logical TCM word and its associated ECC code is split and stored in two physical SRAM banks. This scheme provides an inherent diagnostic mechanism for address decode failures in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an ECC fault. Further, bit multiplexing scheme implemented such that the bits accessed to generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word, this scheme improves the usefulness of the TCM ECC diagnostic. Both these features are hardware features and cannot be enabled or disabled by application software.

5 Clock Monitor

AWR1642 architecture supports Three Digital Clock Comparators (DCCs) and an internal RCOSC. Dual functionality is provided by these modules – Clock detection and Clock Monitoring. DCCint is used to check the availability/range of Reference clock at boot otherwise the device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This provides debug capability). DCCint is only used by boot loader during boot time. It is disabled once the APLL is enabled and locked. DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided version with the Reference input clock of the device. Initially (before configuring APLL), DCC1 is used by bootloader to identify the precise frequency of reference input clock against the internal RCOSC clock source. Failure detection for DCC1 would cause the device to go into limp mode. DCC2 module is one which is available for user software . From the list of clock options given in detailed spec, any two clocks can be compared. One example usage is to compare the CPU clock with the Reference or internal RCOSC clock source. Failure detection is indicated to the Master R4F CPU via Error Signaling Module (ESM).

6 Voltage Monitor

Voltage Monitor (VMON) can detect grossly out of range supply voltages. The VMON operates continuously and requires no software configuration or CPU overhead. VMON monitors are the primary supplies. If the supplies go out of range after the device is out of the safe operating state, it will be placed into the safe operating state by VMON. When power supplies are in range, the VMON will not interfere with the nRESET signal. Primary Supplies not responsible for right functionality of MCU (RF, ANA) are also monitored by VMON but MCU is triggered with error response and safe state transfer is responsibility of Master R4F. The VMON is a continuously operating diagnostic. It is not possible to disable the VMON diagnostic.

7 RTI/WD for Master R4F

AWR1642 architecture supports the use of an internal watchdog that is implemented in the real-time interrupt (RTI) module. The internal watchdog has two modes of operation: digital watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are mutually exclusive; the designer can elect to use one mode or the other but not both at the same time. Watchdog can issue either an internal (warm) system reset or a CPU non-mask able interrupt upon detection of a failure. The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot process. Once the application code takes up the control, Watchdog can be configured again for mode and timings based on specific customer requirements.

8 MPU for Master R4F

Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It is expected that the operating system controls the MPU and changes the MPU settings based on the needs of each task. A violation of a configured memory protection policy results in a CPU abort. PBIST for Peripheral interface SRAMs - SPIs, CANs AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for Peripheral SRAMs as well. PBIST for peripheral SRAM memories can be triggered by the application. User can elect to run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory contents, and as such are typically run only at boot time. However, the user has the freedom to initiate the tests at any time if peripheral communication can be hindered. Any fault detected by the PBIST results in an error indicated in PBIST status registers.

10 ECC for Peripheral interface

SRAMs – SPIs, CANs Peripheral interface SRAMs diagnostic is supported by Single error correction double error detection (SECDED) ECC diagnostic. When a single or double bit error is detected the Master R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset. Software must configure and enable this feature in the peripheral and ESM module. ECC failure (both single bit corrected and double bit uncorrectable error conditions) is reported to the Master R4F as an interrupt via ESM module. Configuration registers protection for Master SS peripherals All the Master SS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are connected to interconnect via Peripheral Central resource (PCR). This provides two diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated per peripheral chip select in the PCR. This can be utilized to disable unused features such that they cannot interfere. In addition, each peripheral chip select can be programmed to limit access based on privilege level of transaction. This feature can be used to limit access to entire peripherals to privileged operating system code only. These diagnostic mechanisms are disabled after reset. Software must configure and enable these mechanisms. Protection violation also generates an ‘aerror’that result in abort to Master R4F or error response to other masters such as DMAs.

12 Cyclic Redundancy Check

–Master SS AWR1642 architecture supports hardware CRC engine on Master SS implementing the below polynomials.

CRC16 CCITT - 0x10
CRC32 Ethernet - 0x04C11DB7
CRC64
CRC 32C- CASTAGNOLI - 0x1EDC6F4
CRC32P4 – E2E Profile4 - 0xF4ACFB1
CRC-8 – H2F Autosar - 0x2F
CRC-8 – VDA CAN - 0x1D The read operation of the SRAM contents to the CRC can be done by CPU or by DMA. The comparison of results, indication of fault, and fault response are the responsibility of the software managing the test.

13 MPU for DMAs

AWR1642 architecture supports MPUs on Master SS DMAs. Failure detection by MPU is reported to the Master R4F CPU core as an interrupt via ESM. DSPSS’s high performance EDMAs also includes MPUs on both read and writes master ports. EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP core as an interrupt via local ESM. Boot time LBIST For BIST R4F Core and associated VIM AWR1642 architecture supports hardware logic BIST (LBIST) even for BIST R4F core and associated VIM module. This logic provides very high diagnostic coverage (>90%) on the BIST R4F CPU core and VIM. This is triggered by Master R4F boot loader at boot time and it does not proceed further if the fault is detected.

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Monitoring and Diagnostics Copyright © 2017, Texas Instruments Incorporated Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 (continued) S No Feature Description

15 Boot time PBIST for BIST

AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST R4F TCMs. PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed further if the fault is detected.

16 End to End ECC for BIST

BIST R4F TCMs diagnostic is supported by Single error correction double error detection (SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while double bit error is communicated to Master R4F as an interrupt so that application code becomes aware of this and takes appropriate action.

17 BIST R4F TCM bit

18 RTI/WD for BIST R4F

AWR1642 architecture supports an internal watchdog for BIST R4F. Timeout condition is reported via an interrupt to Master R4F and rest is left to application code to either go for SW reset for BIST SS or warm reset for the AWR1642 device to come out of faulty condition.

19 Boot time PBIST for L1P,

L1D, L2 and L3 Memories AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic coverage (March-13n). PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed further if the fault is detected.

20 Parity on L1P

AWR1642 architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is reported to the CPU as an interrupt. Note:- L1D memory is not covered by parity or ECC and need to be covered by application level diagnostics.

21 ECC on DSP’s L2 Memory

AWR1642 architecture supports both Parity Single error correction double error detection (SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB of memory used to store program and Data sections for the DSP. A 12-bit code word is used to store the ECC data as calculated over the 256-bit data bus (logical instruction fetch size). The ECC logic for the L2 access is located in the DSP and evaluation is done by the ECC control logic inside the DSP. This scheme provides end-to-end diagnostics on the transmissions between DSP and L2. Byte aligned Parity mechanism is also available on L2 to take care of data section.

22 ECC on Radar Data Cube

(L3) Memory L3 memory is used as Radar data section in AWR1642. AWR1642 architecture supports Single error correction double error detection (SECDED) ECC diagnostic on L3 memory. An 8-bit code word is used to store the ECC data as calculated over the 64-bit data bus. Failure detection by ECC logic is reported to the Master R4F CPU core as an interrupt via ESM.

23 RTI/WD for DSP Core

AWR1642 architecture supports the use of an internal watchdog for BIST R4F that is implemented in the real-time interrupt (RTI) module – replication of same module as used in Master SS. This module supports same features as that of RTI/WD for Master/BIST R4F. This watchdog is enabled by customer application code and Timeout condition is reported via an interrupt to Master R4F and rest is left to application code in Master R4F to either go for SW reset for DSP SS or warm reset for the AWR1642 device to come out of faulty condition.

24 CRC for DSP Sub-System

AWR1642 architecture supports dedicated hardware CRC on DSPSS implementing the below polynomials.

CRC16 CCITT - 0x10
CRC32 Ethernet - 0x04C11DB7
CRC64 The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The comparison of results, indication of fault, and fault response are the responsibility of the software managing the test.

25 MPU for DSP

AWR1642 architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2 memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by MPU is reported to the DSP core as an abort.

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Monitoring and DiagnosticsCopyright © 2017, Texas Instruments Incorporated Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 (continued) S No Feature Description (1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the temperature sensed via API by customer application.

Report the temperature sensed after every N frames
Report the condition once the temperature crosses programmed threshold. It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox. (2) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the detected output power via API by customer application.
Report the power detected after every N frames
Report the condition once the output power degrades by more than configured threshold from the configured. It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.

26 Temperature Sensors

AWR1642 architecture supports various temperature sensors all across the device (next to power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame period.(1) 27 Tx Power Monitors AWR1642 architecture supports power detectors at the Tx output.(2)

28 Error Signaling

When a diagnostic detects a fault, the error must be indicated. The AWR1642 architecture provides aggregation of fault indication from internal monitoring/diagnostic mechanisms using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides mechanisms to classify errors by severity and to provide programmable error response. ESM module is configured by customer application code and specific error signals can be enabled or masked to generate an interrupt (Low/High priority) for the Master R4F CPU. AWR1642 supports Nerror output signal (IO) which can be monitored externally to identify any kind of high severity faults in the design which could not be handled by the R4F.

29 Synthesizer (Chirp)

Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if any, are detected and reported.

30 Ball break detection for TX

ports (TX Ball break monitor) AWR1642 architecture supports a ball break detection mechanism based on Impedance measurement at the TX output(s) to detect and report any large deviations that can indicate a ball break. Monitoring is done by TIs code running on BIST R4F and failure is reported to the Master R4F via Mailbox. It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F. 31 RX loopback test Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain/Noise figure, inter-RX balance, etc. 32 IF loopback test Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect failure.

33 RX saturation detect Provision to detect ADC saturation due to excessive incoming signal level and/or

interference.

34 Boot time LBIST for DSP

AWR1642 device supports boot time LBIST for the DSP Core. LBIST can be triggered by the Master R4F application code during boot time.

ADVANCE□INFORMATION Low Priority Interrupt Handing High Priority Interrupt Handing Error Signal Handling Error Group 1 Error Group 2 Error Group 3 Low Priority Interrupy High Priority Interrupy Device Output Pin Interrupt Enable Interrupt Priority Nerror Enable From Hardware Diagnostics AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Monitoring and Diagnostics Copyright © 2017, Texas Instruments Incorporated

7.1.1 Error Signaling Module

When a diagnostic detects a fault, the error must be indicated. AWR1642 architecture provides aggregation of fault indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling module (ESM). The ESM provides mechanisms to classify faults by severity and allows programmable error response. Below is the high level block diagram for ESM module. Figure 7-1. ESM Module Diagram

ADVANCE□INFORMATION RX1 RX2 RX3 RX4 TX2 Antenna Structure TX1 Radar Front End Integrated MCU ARM Cortex-R4F CAN Power Management 40-MHz Crystal Serial FLASH DCAN PHY Automotive Network Integrated DSP TI C674x AWR1642 CAN FD MCAN PHY Automotive Network QSPI AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Applications, Implementation, and LayoutCopyright © 2017, Texas Instruments Incorporated

8 Applications, Implementation, and Layout

Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

Key device features driving the following applications are:

Integration of Radar Front End and Programmable MCU
Flexible boot modes: Autonomous Application boot using a serial flash or external boot over SPI.

8.2 Short-Range Radar

Figure 8-1. Short-Range Radar

8.3 Reference Schematic

Figure 8-2 and Figure 8-3 show the reference schematic and low-noise LDO circuitry for the AWR1642 device.

ADVANCE□INFORMATION XTAL SRAM SUPPLY DIG SUPPLY 1V2 SUPPLY AWR1642 1V8 SUPPLY DIFF SUPPLY VCLK SUPPLYVCOLDO SUPPLY1P8V IO SUPPLYBB SUPPLY

50 OHMS RF TRACES

100 OHMS

THE POWERUP MODE. DURING BOOTUP TO DECIDE SOP LINES TO BE SET VNWA SUPPLY EP R15 G13 B15 B14 D14 N14 N15 C14 B13 D15 C15 A14 J1L1N1R1E2G2J2L2N2A3B3C3E3F3G3H3J3K3L3M3N3C4A5B5C5C6A7B7C7A15E5L5E6G6J6L6G7H7J7K7E8G8J8K8L8F9H9K9E10G10J10K10 A2B2B10A10A13K5F5B12B11C2D2G5H5J5G15P14R6P15N11H15R10F15E15R9L13 K13 J13 H13 F13 G14 H14 F14 D13 E14 C13 E13 P13 R11 N13 N10 P10 P12 R14 N12 R13 P11 R12 M15 M14 L15 L14 K15 K14 J15 J14 L10 E11 F11 H11 K11 C16 C34C31C27C26 R11 SOP1 R10 C30C24C11C4 0.22UF AR_1V4_SYNTH C12 AR_LVDS_CLKM AR_LVDS_FRCLKP AR_LVDS_1P AR_LVDS_1M AR_LVDS_CLKP AR_NERRIN AR_WARMRST AR_QSPI_D0 AR_1V8 AR_NRST AR_LVDS_FRCLKM AR_LVDS_0M AR_LVDS_0P AR_QSPI_D3 AR_QSPI_D2 AR_QSPI_D2 33.2 AR_QSPI_D3 AR_QSPI_SCLK R2 R7 33.2 33.2 10K AR_QSPI_D0 1UF 0.1UF 33.2 S25FL132K0XNFB01 R4AR_QSPI_D1 AR_QSPI_CS 47.5KR1 10K 4.7PF C15 AR_XTALM 4.7PF AR_ANAMUX 0.1UF AR_PMIC_CLKOUT_SOP2 AR_1V8 PMIC_1V2 AR_1P3_RF2 AR_1V8 AR_VBGAP SOP0 AR_SCL AR_BSS_LOGGER 10K AR_TDO_SOP0 AR_SYNC_OUT_SOP1 AR_MCUCLKOUT AR_ANATEST1 AR_ANATEST2 AR_ANATEST3 AR_ANATEST4 AR_VSENSE AR_DMM_CLK AR_DMM_SYNC AR_DP0 AR_DP1 AR_DP2 AR_DP3 AR_DP4 AR_DP5 AR_DP6 AR_DP8 AR_DP9 AR_DP10 AR_DP11 AR_GPIO_0 AR_MSS_LOGGER AR_MOSI1 +3.3VD AR_TDO_SOP0 AR_HOSTINTR1 +3.3VD 40MHZ AR_RS232TX AR_1V4_SYNTH AR_VOUT_PA AR_GPIO_1 AR_1P3_RF1 VPP_1P7 AR_XTALP AR_1V4_APLL PMIC_1V2 PMIC_1V2 AR_1V8 AR_1V8 AR_DP12 AR_DP15 AR_1V8 AR_TCK AR_QSPI_CS AR_XTALP AR_OSC_CLKOUT +3.3VD AR_MISO1 AR_SDA AR_CS1 AR_1V8 AR_1V8 AR_1V8 AR_QSPI_D1 AR_TMS AR_SPICLK1 1UF 10UF0.22UF AR_VBGAP AR_VOUT_PA AR_1V4_APLL 1UF +3.3VD 33.2 AR_QSPI_SCLK AR_RS232RX AR_NERR_OUT AR_DP7 AR_XTALM AR_DP14 AR_DP13 AR_TDI AR_GPIO_2 +3.3VD AR_SYNC_IN AR_SYNC_OUT_SOP1 10K 10KAR_PMIC_CLKOUT_SOP2 SOP2R12 AR_1V8 0.22UF C6C3 C10 C28 C33C14 C20 AR_1P3_RF2 10UF C35 +3.3VD 0.22UF AR_1P3_RF1 10UF 10UF C7C5 C29C13 C17 0.22UF 0.22UF C32 C87 2.2UF S25FL132K0XN EP SO/IO1 CS_N SCK HOLD_N/IO3 VCC SI/IO0VSS WP_N/IO2 AWR1642_PRELIMINARY VSS SYNC_OUT SYNC_IN DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 DMM_SYNC DMM_CLK GPADC_6 GPADC_5 GPADC_4 GPADC_3 GPADC_2 GPADC_1 MCU_CLKOUT PMIC_CLKOUT CLKM CLKP OSC_CLKOUT TX2 TX1 RX4 RX3 RX2 RX1 VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS VOUT_PAVOUT_PA VBGAP VOUT_14APLL VOUT_14SYNTH VIN_18BBVIN_18BBVIN_18VCOVIN_18CLKVIN_13RF2VIN_13RF2VIN_13RF1VIN_13RF1VIN_13RF1VIN_SRAM VNWAVDDINVDDINVDDINVDDINVIOINVIOIN VIOIN_18DIFF VIOIN_18 VPP VSSA VSSA VSSA VSSA VSSA GPIO_2 GPIO_1 GPIO_0 MOSI_2 MISO_2 SPI_CS_2 SPI_CLK_2 MOSI_1 MISO_1 SPI_CS_1 SPI_CLK_1 SPI_HOST_INTR_1 TDI TDO TMS TCK QSPI_3 QSPI_2 QSPI_1 QSPI_0 QSPI_CS QSPI_CLK RS232_TX RS232_RX NERROR_OUT NERROR_IN WARM_RESET NRESET LVDS_FRCLKM LVDS_FRCLKP LVDS_CLKM LVDS_CLKP LVDS_TXM_1 LVDS_TXP_1 LVDS_TXM_0 LVDS_TXP_0 VSS VSS VSS VSS VSS Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments IncorporatedApplications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 SWRS203 – MAY 2017 www.ti.com Figure 8-2. AWR1642 Reference Schematic

ADVANCE□INFORMATION LDO_01 (1.8V OUTPUT) LDO_02 (1.3V LDO) EP 20 19 18 17 16 109876 10UF0.01UF LDO_EN 10UF C46 1UF R132 TPS7A8801RTJ C39 1.96K C44 R15 PMIC_1V8 C37C36 10UF C22C23C25C21 C48 C47 C40 C38 SS_CTRL AR_1P3_RF1 22UF 22UF 0.01UF 1.96K 10UF PMIC_2V3 LDO_EN AR_1V8 PMIC_2V3 LDO_EN 10UF C19C18 0.47UF R82 12.7K 10K R81 10K R84 0.47UF10UF22UF0.1UF 10K DNI=TRUE R83 EP LDO_EN 0.01UF R14 SS_CTRL 0.01UF C45 10UF1UF R13 R121 C43 C41 C49 AR_1P3_RF2 10UF C42 TPS7A8801 GND EN1 NR/SS1 SS_CTRL1 PG1FB1 OUT1 OUT1 GND OUT2 OUT2 FB2PG2SS_CTRL2NR/SS2EN2 IN2 IN2 GND IN1 IN1 TPS7A8101 EPADEN NR IN IN GND FB/SNS OUT OUT Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: AWR1642 AWR1642 www.ti.com SWRS203 – MAY 2017 Figure 8-3. AWR1642 Low-Noise LDO Circuitry

ADVANCE□INFORMATION AWR1642 SWRS203 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1642 Applications, Implementation, and Layout Copyright © 2017, Texas Instruments Incorporated

8.4 Layout

The top layer routing, top layer closeup, and bottom layer routing are shown in Figure 8-4, Figure 8-5, and Figure 8-6, respectively.

8.4.1 Layout Guidelines

Figure 8-4. Top Layer Routing

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Applications, Implementation, and LayoutCopyright © 2017, Texas Instruments Incorporated Figure 8-5. Top Layer Routing Closeup

ADVANCE□INFORMATION 1 0.689 2.067 100.000 Rogers 4835 4mil coreH/1 Low Pro Rogers 4835 4.000 4.000 3.480 2 1.260 1.260 73.000 Iteq IT180A Prepreg 1080 Dielectric 4.195 2.830 3.700 Iteq IT180A Prepreg 1080 Dielectric 4.195 2.830 3.700 3 1.260 1.260 69.000 Iteq IT180A 28 mil core 1/1 FR4 28.000 28.000 4.280 4 1.260 1.260 48.000 Iteq IT180A Prepreg 1080 Dielectric 4.195 2.691 3.700 Iteq IT180A Prepreg 1080 Dielectric 4.195 2.691 3.700 5 1.260 1.260 72.000 Iteq IT180A 4 mil core 1/H FR4 4.000 4.000 3.790 6 0.689 2.067 100.000 56.21 AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Applications, Implementation, and LayoutCopyright © 2017, Texas Instruments Incorporated

8.4.2 Stackup Details

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions follow.

9.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, AWR1642). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ABL0161), the temperature range (for example, blank is the default commercial temperature range). Figure 9-1 provides a legend for reading the complete device name for any AWR1642 device. For orderable part numbers of AWR1642 devices in the ABL0161 package types, see the Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the AWR1642 Device Errata.

ADVANCE□INFORMATION X 1 6 42 B I G ABL Prefix X= Experimental Generation Variant Num RX/TX Channels

Features

1 = 76 to 81 GHz 2 = FE 4 = FE + FFT + MCU 6 = FE + MCU + DSP + 1.5 MB RX = 1,2,3,4 TX = 1,2,3 Blank = Baseline Blank = Rev 1.0 A = ASIL A Capable B = ASIL B Capable Tray or Tape & Reel Package Security Temperature (Tj) T = Small Reel R = Big Reel <Blank> = Tray ABL = BGA G = General S = Secure D = Development Secure C = 0° C to 70° C K = ±40° C to 85° C A = ±40° C to 105° C I = ±40° C to 125° C Copyright © 2017, Texas Instruments Incorporated AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Device and Documentation SupportCopyright © 2017, Texas Instruments Incorporated Figure 9-1. Device Nomenclature

9.2 Tools and Software

AWR1642 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the specific device. AWR1642 IBIS Model IO buffer information model for the IO buffers of the device. For simulation on a circuit board, see IBIS Open Forum. AWR1642 Checklist for Schematic Review, Layout Review, Bringup/Wakeup A set of steps in spreadsheet form to select system functions and pinmux options. Specific EVM schematic and layout notes to apply to customer engineering. A bringup checklist is suggested for customers.

9.3 Documentation Support

To receive notification of documentation updates— including silicon errata— go to the product folder for your device on ti.com (AWR1642). In the upper right-hand corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. The current documentation that describes the DSP, related peripherals, and other technical collateral follows. Errata AWR1642 Device Errata Describes known advisories, limitations, and cautions on silicon and provides workarounds.

9.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

9.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

9.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

ADVANCE□INFORMATION AWR1642 www.ti.com SWRS203 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1642 Mechanical, Packaging, and Orderable InformationCopyright © 2017, Texas Instruments Incorporated

10 Mechanical, Packaging, and Orderable Information

10.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. CAUTION The following package information is subject to change without notice.

www.ti.com PACKAGE OUTLINE C1.17 MAX TYP0.37 0.27 9.1 TYP

9.1 TYP

0.65 TYP

161X 0.45 0.35 A 10.5 10.3 B 10.5 10.3 (0.65) TYP (0.65) TYP FCBGA - 1.17 mm max heightABL0161B PLASTIC BALL GRID ARRAY 4223365/A 10/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.1 C

0.15 C A B

0.08 C PKG PKG BALL A1 CORNER R C D E F G H J K L M N P 1 2 3 4 5 6 7 8 9 10 11 A B 12 13 14 15 SCALE 1.400

www.ti.com EXAMPLE BOARD LAYOUT 161X ( 0.32) (0.65) TYP (0.65) TYP ( 0.32) METAL

0.05 MAX

( 0.32) SOLDER MASK OPENING

0.05 MIN

FCBGA - 1.17 mm max heightABL0161B PLASTIC BALL GRID ARRAY 4223365/A 10/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). PKG PKG LAND PATTERN EXAMPLE SCALE:10X 1 2 3 4 5 6 7 8 9 10 11 A C D E F G H J K L M N P R B 12 13 14 15 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.65) TYP 161X ( 0.32) (0.65) TYP FCBGA - 1.17 mm max heightABL0161B PLASTIC BALL GRID ARRAY 4223365/A 10/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X PKG PKG 1 2 3 4 5 6 7 8 9 10 11 A C D E F G H J K L M N P R B 12 13 14 15

www.ti.com 15-May-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples X1642BIGABL ACTIVE FC/CSP ABL 161 1 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

X1642BIGABL specifications and overview.

Summary

Single-Chip 77- and 79-GHz FMCW Radar Sensor

Description

Single-Chip 77- and 79-GHz FMCW Radar Sensor

Source title X1642BIGABL Datasheet(PDF) - Texas Instruments

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