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FN8099 Rev 2.00 Page 1 of 28 May 8, 2006 FN8099 Rev 2.00 May 8, 2006 X1227 2-Wire™ RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM DATASHEET

FEATURES

  • Real Time Clock/Calendar — Tracks Time in Hours, Minutes, and Seconds — Day of the Week, Day, Month, and Year
  • 2 Polled Alarms (Non-volatile) — Settable on the Second, Minute, Hour, Day of the Week, Day, or Month — Repeat Mode (periodic interrupts)
  • Oscillator Compensation on Chip — Internal Feedback Resistor and Compensation Capacitors — 64 Position Digitally Controlled Trim Capacitor — 6 Digital Frequency Adjustment Settings to ±30ppm
  • CPU Supervisor Functions — Power-On Reset, Low Voltage Sense — Watchdog Timer (SW Selectable: 0.25s, 0.75s, 1.75s, off)
  • Battery Switch or Super Cap Input
  • 512 x 8 Bits of EEPROM — 64-Byte Page Write Mode — 8 Modes of Block Lock™ Protection — Single Byte Write Capability
  • High Reliability — Data Retention: 100 Years — Endurance: 100,000 Cycles Per Byte
  • 2-Wire™ Interface Interoperable with I 2C* — 400kHz Data Transfer Rate
  • L o w P o w e r C M O S — 1.25µA Operating Current (Typical)
  • Small Package Options — 8 Ld SOIC and 8 Ld TSSOP
  • Repetitive Alarms
  • Temperature Compensation
  • Pb-Free Plus Anneal Available (RoHS Compliant)

APPLICATIONS

  • Utility Meters
  • HVAC Equipment
  • Audio/Video Components
  • Set Top Box/Television
  • M o d e m s
  • Network Routers, Hubs, Switches, Bridges
  • Cellular Infrastructure Equipment
  • Fixed Broadband Wireless Equipment
  • Pagers/PDA
  • POS Equipment
  • Test Meters/Fixtures
  • Office Automation (Copiers, Fax)
  • Home Appliances
  • Computer Products
  • Other Industrial/Medical/Automotive

DESCRIPTION

The X1227 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM, oscillator com pensation, CPU Supervisor (POR/LVS and WDT) and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. BLOCK DIAGRAM Oscillator Frequency Timer LogicDivider Calendar Control/ Registers 1Hz Time Keeping Registers Alarm Regs Compare Mask RESET Control Decode Logic Alarm (EEPROM) (EEPROM) SCL SDA Serial Interface Decoder EEPROM ARRAYWatchdog Timer Low Voltage Reset Registers Status (SRAM) VCC VBACK 32.768kHz (SRAM) Battery Circuitry Switch OSC Compensation NOT RECOMMENDED FOR NEW DESIGNS SEE ISL12027

FN8099 Rev 2.00 Page 2 of 28 May 8, 2006

ORDERING INFORMATION

PART NUMBER PART MARKING V CC RANGE (V) V TRIP TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # X1227S8-4.5A X1227AL 4.5 to 5.5 4.63V ± 112mV 0 to 70 8 Ld SOIC MDP00 27 X1227S8Z-4.5A (Note 1) X1227ZAL 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X1227S8I-4.5A X1227AM -40 to 85 8 Ld SOIC MDP0027 X1227S8IZ-4.5A (Note 1) X1227ZAM -40 to 85 8 Ld SOIC (Pb-free) MDP0 027 X1227V8-4.5A 1227AL 0 to 70 8 Ld TSSOP M8.173 X1227V8Z-4.5A (Note 1) 1227ALZ 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X1227V8I-4.5A 1227AM -40 to 85 8 Ld TSSOP M8.173 X1227V8IZ-4.5A (Note 1) 1227AMZ -40 to 85 8 Ld TSSOP (Pb-free) M8.1 73 X1227S8* X1227 4.38V ± 112mV 0 to 70 8 Ld SOIC MDP0027 X1227S8Z* (Note 1) X1227Z 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X1227S8I X1227I -40 to 85 8 Ld SOIC MDP0027 X1227S8IZ (Note 1) X1227ZI -40 to 85 8 Ld SOIC (Pb-free) MDP0027 X1227V8 1227 0 to 70 8 Ld TSSOP M8.173 X1227V8Z (Note 1) 1227Z 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X1227V8I 1227I -40 to 85 8 Ld TSSOP M8.173 X1227V8IZ (Note 1) 1227IZ -40 to 85 8 Ld TSSOP (Pb-free) M8.173 X1227S8-2.7A X1227AN 2.7 to 5.5 2.85V ± 100mV 0 to 70 8 Ld SOIC MDP0027 X1227S8Z-2.7A (Note 1) X1227ZAN 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X1227S8I-2.7A* X1227AP -40 to 85 8 Ld SOIC MDP0027 X1227S8IZ-2.7A* (Note 1) X1227ZAP -40 to 85 8 Ld SOIC (Pb-free) MDP 0027 X1227V8-2.7A 1227AN 0 to 70 8 Ld TSSOP M8.173 X1227V8Z-2.7A (Note 1) 1227ANZ 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X1227V8I-2.7A 1227AP -40 to 85 8 Ld TSSOP M8.173 X1227V8IZ-2.7A (Note 1) 1227APZ -40 to 85 8 Ld TSSOP (Pb-free) M8.1 73 X1227S8-2.7* X1227F 2.65V ± 100mV 0 to 70 8 Ld SOIC MDP0027 X1227S8Z-2.7 (Note 1) X1227ZF 0 to 70 8 Ld SOIC (Pb-free) MDP0027 X1227S8I-2.7* X1227G -40 to 85 8 Ld SOIC MDP0027 X1227S8IZ-2.7 (Note 1) X1227ZG -40 to 85 8 Ld SOIC (Pb-free) MDP002 7 X1227V8-2.7 1227F 0 to 70 8 Ld TSSOP M8.173 X1227V8Z-2.7 (Note 1) 1227FZ 0 to 70 8 Ld TSSOP (Pb-free) M8.173 X1227V8I-2.7 1227G -40 to 85 8 Ld TSSOP M8.173 X1227V8IZ-2.7 (Note 1) 1227GZ -40 to 85 8 Ld TSSOP (Pb-free) M8.173 *Add "T1" suffix for tape and reel. NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For appropriate volume, any V TRIP value from 2.6 to 4.7V may be ordered via Intersil’s Customer Specification Program (CSPEC).

FN8099 Rev 2.00 Page 3 of 28 May 8, 2006 PIN DESCRIPTIONS PIN ASSIGNMENTS Pin Number Symbol Brief DescriptionSOIC TSSOP 13 X 1 X1. The X1 pin is the input of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal. 24 X 2 X2. The X2 pin is the output of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal.. 35 R E S E T Reset Output – RESET. This is a reset signal output. This signal notifies a host processor that the watchdog time period has expired or that the voltage has dropped below a fixed V TRIP threshold. It is an open drain active LOW output. 46 V SS VSS. 57 S D A Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. 68 S C L Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). 71 V BACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. 82 V CC VCC. NC = No internal connection X1227 VBACK VCC RESET SCL SDA VSS

8 LD TSSOP

8 LD SOIC

FN8099 Rev 2.00 Page 4 of 28 May 8, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on V CC, VBACK pin Voltage on SCL, SDA, X1 and X2 above V CC or VBACK (whichever is higher) Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.) OPERATING CHARACTERISTICS Notes: (1) The device enters the Active state after any start, and rema ins active: for 9 clock cycles if the Device Select Bits i n the Slave Address Byte are incorrect or until 200nS after a stop ending a read or write operation. (2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC. (3) The device goes into the Timekeeping state 200nS after any stop , except those that initiate a nonvolatile write cycle; t WC after a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (4) For reference only and not tested. (5) V IL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz (6) V CC = 0V (7) V BACK = 0V (8) V SDA = VSCL=VCC, Others = GND or VCC Symbol Parameter Conditions Min Typ Max Unit Notes VCC Main Power Supply 2.7 5.5 V VBACK Backup Power Supply 1.8 5.5 V VCB Switch to Backup Supply V BACK -0.2 V BACK -0.1 V VBC Switch to Main Supply V BACK VBACK +0.2 V Symbol Parameter Conditions Min Typ Max Unit Notes ICC1 Read Active Supply Current VCC = 2.7V 400 µA 1, 5, 7, 14 VCC = 5.0V 800 µA ICC2 Program Supply Current (nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14 VCC = 5.0V 3.0 mA ICC3 Main Timekeeping Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15 VCC = 5.0V 20 µA IBACK Timekeeping Current – (Low Voltage Sense and Watchdog Timer disabled V BACK = 1.8V 1.25 µA 3, 6, 9, 14, 15 “See Perfor- mance Data”VBACK = 3.3V 1.5 µA ILI Input Leakage Current 10 µA 10 ILO Output Leakage Current 10 µA 10 VIL Input LOW Voltage -0.5 V CC x 0.2 or VBACK x 0.2 V1 3 VIH Input HIGH Voltage V CC x 0.7 or VBACK x 0.7 VCC + 0.5 or VBACK + 0.5 V1 3 VHYS Schmitt Trigger Input Hysteresis VCC related level .05 x V CC or .05 x VBACK V1 3 VOL1 Output LOW Voltage for SDA and RESET VCC = 2.7V 0.4 V 11 VCC = 5.5V 0.4

(13)Threshold voltages based on the higher of Vcc or Vback. (14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Notes: (1) This parameter is not 100% tested. Figure 1. Standard Output Load for testing the device with VCC = 5.0V

FN8099 Rev 2.00 Page 6 of 28 May 8, 2006 AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 (1) ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 s tBUF Time the bus must be free before a new transmission can start 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR

FN8099 Rev 2.00 Page 7 of 28 May 8, 2006 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (2) Typical values are for T A = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Notes: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS Watchdog/Low Voltage Reset Parameters SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min. Typ. (2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ. (1) Max. Units tWC(1) Write Cycle Time 5 10 ms Symbols Parameters Min. Typ. Max. Unit VPTRIP Programmed Reset Trip Voltage X1227-4.5A X1227 X1227-2.7A X1227-2.7 4.5 4.25 2.7 2.55 4.68 4.38 2.93 2.68 4.75 4.5 3.0 2.7 V t RPD VCC Detect to RESET LOW 500 ns tPURST Power-up Reset Time-out Delay 100 200 400 ms tF VCC Fall Time 10 µs tR VCC Rise Time 10 µs tWDO Watchdog Timer Period: WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 1, WD0 = 0 1.7 725 225 1.75 750 250 1.8 775 275 s ms ms t RST Watchdog Reset Time-out Delay 225 250 275 ms tRSP 2-Wire interface 1 µs VRVALID Reset Valid VCC 1.0 V

FN8099 Rev 2.00 Page 8 of 28 May 8, 2006 VTRIP Programming Timing Diagram VTRIP Programming Parameters 01234567 01234567 01234567 01234567 VCC (VTRIP) tVPHtVPS tVPO tRP SCL SDA AEh 03h/01h RESET VP = 15V 00h00h VCC VCC tTSU tTHD VTRIP Parameter Description Min. Max. Units tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0µ s tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 14 16 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V Vtv VTRIP Program variation after programming (Programmed at 25°C) -25 +25 mV VTRIP programming parameters are not 100% Tested.

automatic leap year correction. repeat mode for the alarms allowing a periodic interrupt. data, while allowing a large user storage area. puts. The input buffer is always active (not gated). put signal with the use of a slope controlled pull-down. tery, a Supercap or tied to ground if not used. the pullup resistor is 5k. If unused, tie to ground. recommended crystal is a Citizen CFS206-32.768KDZF. Figure 2. Recommended Crystal connection

power the device from VCC when VCC exceeds VBACK. Figure 3. Power Control written to the RTC without affecting the other bytes. translates into an accuracy of >1 minute per month. detail information see the Application section. addresses are not recommended.

  1. Alarm 0 (8 bytes; non-volatile)
  2. Alarm 1 (8 bytes; non-volatile)
  3. Control (4 bytes; non-volatile)
  4. Real Time Clock (8 bytes; volatile)
  5. Status (1 byte; volatile)

tinue reading the next Register. Table 1. Clock/Control Memory Map

0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT Unused

0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 18h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

MNAn* registers are set to 9:30 PM. These registers depict BCD re presentations of the time. MO (Month) is 1 to 12, YR (Year) is 0 to 99.

24 Hour Time

are not leap years, unless they are also divisible by 400. Clock/Control Registers (CCR). Table 2. Status Register (SR) CC, the device sets this bit to “0”. WEL bits to be set in a specific sequence. bit and zeroes to the other bi ts of the Status Register.

during a SR read will contain zeros in these bit locations. of the array. The partitions are described in Table 3 . Table 3. Block Protect Bits dog Timer. See Table 4 for options. Table 4. Watchdog Timer Time-Out Options error to achieve better accuracy. adjustment and DTR0 gives 20 ppm adjustment. Table 5. Digital Trimming Registers

FN8099 Rev 2.00 Page 14 of 28 May 8, 2006 Analog Trimming Register (ATR) (Non-volatile) Six analog trimming Bits from ATR5 to ATR0 are provided to adjust the on-chip loading capacitance range. The on- chip load capacitance ranges from 3.25pF to 18.75pF. Each bit has a different weight for capacitance adjust- ment. Using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm range from +116ppm to -37ppm to the nominal frequency compensa- tion. The combination of digital and analog trimming can give up to +146ppm adjustment. The on-chip capacitance can be calculated as follows: C ATR = [(ATR value, decimal) x 0.25pF] + 11.0pF Note that the ATR values ar e in two’s complement, with ATR(000000) = 11.0pF, so the entire range runs from 3.25pF to 18.75pF in 0.25pF steps. The values calculated above are typical, and total load capacitance seen by the cr ystal will include approxi- mately 2pF of package and board capacitance in addi- tion to the ATR value. See Application section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/control register requires the following steps: – Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). – Write a 06h to the Status Register to set both the Reg- ister Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). – Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the CCR changes EEPROM values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a nonvolatile write cycle, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. – Writing all zeros to the status register resets both the WEL and RWEL bits. – A read operation occurring between any of the previous operations will not interrupt the register write operation.

operate with insufficient voltage. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power-up. reduce the likelihood of data corruption. Figure 4. Watchdog Restart/Time Out Note: All inputs are ignored during the active reset period (tRST).

Figure 11. Slave Address, Word Address, and Data Bytes (64 Byte pages) from the master. The SDA output is at high impedance. cycle, and will continue to ACK commands. Figure 12. Byte Write Sequence Figure 13. Writing 30 bytes to a 64-byte memory page starting at address 40.

1 R/W1

23 Bytes

7 Bytes

one byte at a time. Refer to Figure 13. edge, and data transfer sequence. write. The contents of the array are not affected. Figure 14. Page Write Sequence

enable very high accuracy time keeping (<5ppm drift. available today. Table 6 summarizes these parameters.

  1. For an Epson MC-405 device, for

also include about 2pF of package related capacitance. Table 6. Crystal Parameters Required for Intersil RTC’s Table 7. Crystal Manufacturers Manufacturer Part Number Temp Range +25°C Freq Toler.

up with battery backup, the frequency drift is measured. note AN154 on Intersil’s website at www.intersil.com. layout for the X1226 or X1227 devices. Figure 19. Suggested Layout for Intersil RTC in SO-8 packages and pinouts are slightly different. pin to ground and the circuit will begin to oscillate. the X2 pin (oscillator output) and observe the waveform. real time clock as time advances. disappear intermittently for short periods of time.

Figure 20. Supercapacitor charging circuit Table 8. Battery Backup Operation

  1. Example Application, Vcc = 5V, Vback = 3.0V
  2. Example Application, Vcc=3.3V,Vback=3.0V

FN8099 Rev 2.00 Page 26 of 28 May 8, 2006 Referring to Figure 20, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip will be running from the battery. If Vback falls to lower than Vtrip, then the chip shuts down and all outputs are dis- abled except for the oscillato r and timekeeping circuitry. The fact that the chip can be powered from Vback is not necessarily an issue since standby current for the RTC devices is <2µA for this mode (called “main timekeeping current” in the data sheet). Only when the serial inter- face is active is there an increase in supply current, and with Vcc powered down, the serial interface will most likely be inactive. One way to prevent operation in battery backup mode above the Vtrip level is to add a diode drop (silicon diode preferred) to the battery to insure it is below Vtrip. This will also provide reverse leak age protection which may be needed to get safety agency approval. One mode that should always be avoided is the operation of the RTC device with Vback greater than both Vcc and Vtrip (Condition 2d in Table 8). This will cause the battery to drain quickly as serial bus communication and non-volatile writes will require higher supplier current. PERFORMANCE DATA I BACK Performance 1.4 1.2 1.0 0.8 0.6 0.4 0.2 IBACK vs. Temperature Multi-Lot Process Variation Data Temperature °C -40 25 60 85 IBACK (µA) 3.3V 1.8V

FN8099 Rev 2.00 Page 27 of 28 May 8, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8099 Rev 2.00 Page 28 of 28 May 8, 2006 X1227 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7  0o 8o 0o 8o - Rev. 1 12/00