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FN8098 Rev 3.00 Page 1 of 25 May 8, 2006 FN8098 Rev 3.00 May 8, 2006 X1226 4K (512 x 8), 2-Wire™ RTC Real Time Clock/Calendar with EEPROM DATASHEET
FEATURES
- Real Time Clock/Calendar —Tracks Time in Hours, Minutes, and Seconds —Day of the Week, Day, Month, and Year
- 2 Polled Alarms (Non-volatile) —Settable on the Second, Minute, Hour, Day of the Week, Day, or Month —Repeat Mode (periodic interrupts)
- Oscillator Compensation On Chip —Internal Feedback Resistor and Compensation Capacitors —64 Position Digitally Controlled Trim Capacitor —6 Digital Frequency Adjustment Settings to ±30ppm
- Battery Switch or Super Cap Input
- 512 x 8 Bits of EEPROM —64-Byte Page Write Mode —8 Modes of Block Lock™ Protection —Single Byte Write Capability
- High Reliability —Data Retention: 100 Years —Endurance: 100,000 Cycles Per Byte
- 2-Wire™ Interface Interoperable with I —400kHz Data Transfer Rate
- Frequency Output (SW Selectable: Off, 1Hz, 4096Hz or 32.768kHz)
- Low Power CMOS —1.25µA Operating Current (Typical)
- Small Package Options —8 Ld SOIC and 8 Ld TSSOP
- Repetitive Alarms
- Temperature Compensation
- Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
- Utility Meters
- HVAC Equipment
- Audio/Video Components
- Set Top Box/Television
- M o d e m s
- Network Routers, Hubs, Switches, Bridges
- Cellular Infrastructure Equipment
- Fixed Broadband Wireless Equipment
- Pagers/PDA
- POS Equipment
- Test Meters/Fixtures
- Office Automation (Copiers, Fax)
- Home Appliances
- Computer Products
- Other Industrial/Medical/Automotive
DESCRIPTION
The X1226 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. BLOCK DIAGRAM Oscillator Frequency Timer LogicDivider Calendar Control/ Registers 1Hz Time Keeping Registers Alarm Regs Compare Mask Control Decode Logic Alarm (EEPROM) (EEPROM) SCL SDA Serial Interface Decoder EEPROM ARRAY Registers Status (SRAM) SelectPHZ/IRQ VCC VBACK 32.768kHz (SRAM) Battery Circuitry Switch OSC Compensation
FN8098 Rev 3.00 Page 2 of 25 May 8, 2006 PIN CONFIGURATION
Ordering Information
PART NUMBER PART MARKING V DD (V) TEMP RANGE (°C) PACKAGE PKG. DWG. # X1226S8* X1226 2.7 to 5.5 0 to 70 8 Ld SOIC (150 mil) MDP0027 X1226S8Z* (Note) X1226Z 0 to 70 8 Ld SOIC (150 mil) (Pb-free) MDP00 27 X1226S8I* X1226I -40 to 85 8 Ld SOIC (150 mil) MDP0027 X1226S8IZ* (Note) X1226ZI -40 to 85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 X1226V8* 1226 0 to 70 8 Ld TSSOP (4.4mm) M8.173 X1226V8Z* (Note) 1226Z 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173 X1226V8I* 1226I -40 to 85 8 Ld TSSOP (4.4mm) M8.173 X1226V8IZ* (Note) 1226IZ -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) M8. 173 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VBACK VCC PHZ/IRQ SCL SDA VSS
8 LD TSSOP
8 LD SOIC
FN8098 Rev 3.00 Page 3 of 25 May 8, 2006 PIN ASSIGNMENTS Pin Number Symbol Brief DescriptionSOIC TSSOP 13X 1 X1. The X1pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1226 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X1 are highly recommended. See Application section for more recommendations. 24X 2 X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1226 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X2 are highly recommended. See Application section for more recommendations. 3 5 PHZ/IRQ Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from the internal oscillator or an interrupt signal output. It is an open drain output. When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz or inactive. When used as interrupt output, this signal notifies a host processor that an alarm has occurred and an action is required. It is an active LOW output. The control bits for this function are FO1 and FO0 and are found in address 0011h of the Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on page 8. 46 V SS VSS. 57 S D A Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz 2-wire interface speed. 68 S C L Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). 71 V BACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. 82 V CC VCC.
automatic leap year correction. the alarms allowing a periodic interrupt. frequency output of 1 Hz, 4096 Hz, or 32,768 Hz. data, while allowing a large user storage area. puts. The input buffer is always active (not gated). put signal with the use of a slope controlled pull-down. tery, a Supercap or tied to ground if not used. rupt signal output. It is an open drain output. of 32.768kHz, 4096Hz, 1Hz or inactive. required. It is an active LOW output. recommended crystal is a Citizen CFS206-32.768KDZF. Figure 1. Recommended Crystal Connection
power the device from VCC when VCC exceeds VBACK. Figure 2. Power Control written to the RTC without affecting the other bytes. translates into an accuracy of >1 minute per month. information see the Application section. addresses are not recommended.
- Alarm 0 (8 bytes; non-volatile)
- Alarm 1 (8 bytes; non-volatile)
- Control (4 bytes; non-volatile)
- Real Time Clock (8 bytes; volatile)
- Status (1 byte; volatile)
from this section terminates the operation. tinue reading the next Register. Table 1. Clock/Control Memory Map
0037 RTC
0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h
0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h
0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h
0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h
0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h
0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h
0013 Control
0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h
0011 INT IM AL1E AL0E FO1 FO0 X X X 00h
0010 BL BP2 BP1 BP0 0 0 0 0 0 00h
0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h
0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h
0007 Alarm0
0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0005 YRA0 Unused - De fault = RTC Year value (No EEPROM) - Future expansion
0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h
0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h
0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h
0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h
0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h
MNAn* registers are set to 9:30 PM. These registers depict BCD re presentations of the time. MO (Month) is 1 to 12, YR (Year) is 0 to 99.
24 Hour Time
are not leap years, unless they are also divisible by 400. Table 2. Status Register (SR) CC, the device sets this bit to “0”. RWEL and WEL bits to be set in a specific sequence.
bit and zeroes to the other bi ts of the Status Register. during a SR read will contain zeros in these bit locations. of the array. The partitions are described in Table 3. and AL0E bits are set to ‘1’, respectively. Table 3. Block Protect Bits alarms respectively, indicate if an alarm has happened. eighth clock of a read of the register containing the bits. nth hour, or n th date, or for the same day of the week. this pulse will be periodic. output function is disabled.
0 Single Time Event Set By Alarm
1 Repetitive/Recurring Time Event Set By
Table 4. Programmable Frequency Output Bits error to achieve better accuracy. adjustment and DTR0 gives 20 ppm adjustment. Table 5. Digital Trimming Registers vided to adjust the on-chip loading capacitance range. analog trimming can give up to +146ppm adjustment. by a start and ended with a stop). ister Write Enable Latch (RWEL) and the WEL bit.
00 A l a r m I R Q output
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages) from the master. The SDA output is at high impedance. Figure 7. Byte Write Sequence Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
1 R/W1
23 Bytes
7 Bytes
cycle, and will continue to ACK commands. causes the X1226 to begin the nonvolatile write cycle. write. The contents of the array are not affected. Figure 9. Page Write Sequence
FN8098 Rev 3.00 Page 16 of 25 May 8, 2006 ABSOLUTE MAXIMUM RATINGS Voltage on V CC, VBACK and PHZ/IRQ Voltage on SCL, SDA, X1 and X2 above V CC or VBACK (whichever is higher) COMMENT Stresses above those liste d under “Absolute Maximum Ratings” may cause perman ent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.) OPERATING CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Unit Notes VCC Main Power Supply 2.7 5.5 V VBACK Backup Power Supply 1.8 5.5 V VCB Switch to Backup Supply V BACK -0.2 V BACK -0.1 V VBC Switch to Main Supply V BACK VBACK +0.2 V Symbol Parameter Conditions Min Typ Max Unit Notes ICC1 Read Active Supply Cur- rent VCC = 2.7V 400 µA 1, 5, 7, 14VCC = 5.0V 800 µA ICC2 Program Supply Current (nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14VCC = 5.0V 3.0 mA ICC3 Main Timekeeping Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15VCC = 5.0V 20 µA IBACK Timekeeping Current VBACK = 1.8V 1.25 µA 3, 6, 9, 14, 15 “See Perfor- mance Data”VBACK = 3.3V 1.5 µA ILI Input Leakage Current 10 µA 10 ILO Output Leakage Current 10 µA 10 VIL Input LOW Voltage -0.5 VCC x 0.2 or VBACK x 0.2 V1 3 VIH Input HIGH Voltage VCC x 0.7 or VBACK x 0.7 VCC + 0.5 or VBACK + 0.5 V1 3 VHYS Schmitt Trigger Input Hysteresis VCC related level .05 x VCC or .05 x VBACK V1 3 VOL1 Output LOW Voltage for SDA VCC = 2.7V 0.4 V1 1VCC = 5.5V 0.4 VOL2 Output LOW Voltage for PHZ/IRQ VCC = 2.7V V CC x 0.3 V1 1VCC = 5.5V V CC x 0.3 VOH2 Output HIGH Voltage for PHZ/IRQ VCC = 2.7V V CC x 0.7 V1 2VCC = 5.5V V CC x 0.7
Byte are incorrect or until 200nS after a stop ending a read or write operation. (2) The device enters the Program state 200nS after a stop ending a write operation and continues for t WC. (4) For reference only and not tested. (13) Threshold voltages based on the higher of Vcc or Vback. (14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Notes: (1) This parameter is not 100% tested. Figure 14. Standard Output Load for testing the device with VCC = 5.0V
FN8098 Rev 3.00 Page 18 of 25 May 8, 2006 AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 (1) ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 s tBUF Time the bus must be free before a new transmission can start 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR
FN8098 Rev 3.00 Page 19 of 25 May 8, 2006 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time V CC is stable until the specified operation can be initiated. These parameters are not 100% tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec. (2) Typical values are for T A = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min. Typ. (2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ. (1) Max. Units tWC(1) Write Cycle Time 5 10 ms
enable very high accuracy time keeping (<5ppm drift). available today. Table 6 summarizes these parameters.
- For an Epson MC-405 device, for
also include about 2pF of package related capacitance. Table 6. Crystal Parameters Required for Intersil RTC’s Table 7. Crystal Manufacturers Manufacturer Part Number Temp Range +25°C Freq Toler.
note AN154 on Intersil’s website at www.intersil.com. layout for the X1226 or X1227 devices. Figure 15. Suggested Layout for Intersil RTC in SO-8 packages and pinouts are slightly different. pin to ground and the circuit will begin to oscillate. the X2 pin (oscillator output) and observe the waveform. when using the proper crystal and layout). ter, and using a pullup resistor for an open-drain output).
a battery (especially lithium batteries!). Figure 16. Supercapactor charging circuit the battery will be drained. Table 8. Battery Backup Operation
- Example Application, Vcc=5V, Vback=3.0V
- Example Application, Vcc=3.3V,Vback=3.0V
FN8098 Rev 3.00 Page 23 of 25 May 8, 2006 Referring to Figure 16, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip will be running from the battery. If Vback falls to lower than Vtrip, then the chip shuts down and all outputs are dis- abled except for the oscillato r and timekeeping circuitry. The fact that the chip can be powered from Vback is not necessarily an issue since standby current for the RTC devices is <2µA for this mode (called “main timekeeping current” in the data sheet). Only when the serial inter- face is active is there an increase in supply current, and with Vcc powered down, the serial interface will most likely be inactive. One way to prevent operation in battery backup mode above the Vtrip level is to add a diode drop (silicon diode preferred) to the battery to insure it is below Vtrip. This will also provide reverse leak age protection which may be needed to get safety agency approval. One mode that should always be avoided is the opera- tion of the RTC device with Vback greater than both Vcc and Vtrip (Condition 2d in Table 8). This will cause the battery to drain quickly as serial bus communication and non-volatile writes will require higher supplier cur- rent. PERFORMANCE DATA I BACK Performance 1.4 1.2 1.0 0.8 0.6 0.4 0.2 IBACK vs. Temperature Multi-Lot Process Variation Data Temperature °C -40 25 60 85 IBACK (µA) 3.3V 1.8V
FN8098 Rev 3.00 Page 24 of 25 May 8, 2006 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C
0.010 BM CA
B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES N 8 14 16 16 20 24 28 Reference - Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994
FN8098 Rev 3.00 Page 25 of 25 May 8, 2006 X1226 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7 0o 8o 0o 8o - Rev. 1 12/00