X1205 INTERSIL | Alldatasheet
Document overview
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Technical content
FN8097.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X1205 2-Wire™ RTC Real Time Clock/Calendar
FEATURES
- Real Time Clock/Calendar —Tracks time in Hours, Minutes, and Seconds —Day of the Week, Day, Month, and Year
- 2 Polled Alarms (Non-volatile) —Settable on the Second, Minute, Hour, Day of the Week, Day, or Month —Repeat Mode (periodic interrupts)
- Oscillator Compensation on chip —Internal feedback resistor and compensation capacitors —64 position Digitally Controlled Trim Capacitor —6 digital frequency adjustment settings to ±30ppm
- Battery Switch or Super Cap Input
- 2-Wire™ Interface interoperable with I2C* —400kHz data transfer rate
- Low Power CMOS —1.25µA Operating Current (Typical)
- Small Package Options —8-Lead SOIC and 8-Lead TSSOP
- Repetitive Alarms
- Temperature Compensation
- Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
- Utility Meters
- HVAC Equipment
- Audio/Video Components
- Set Top Box/Television
- M o d e m s
- Network Routers, Hubs, Switches, Bridges
- Cellular Infrastructure Equipment
- Fixed Broadband Wireless Equipment
- Pagers/PDA
- POS Equipment
- Test Meters/Fixtures
- Office Automation (Copiers, Fax)
- Home Appliances
- Computer Products
- Other Industrial/Medical/Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with clock/calendar, two pol led alarms, oscillator compensation, and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, and Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. BLOCK DIAGRAM Oscillator Frequency Timer LogicDivider Calendar 32.768kHz Control Registers 1Hz Time Keeping Registers Alarm Regs Compare Mask IRQ Control Decode Logic Alarm (EEPROM) (EEPROM)SCL SDA Serial Interface Decoder Interrupt Enable Registers Status (SRAM) Alarm Alarm (SRAM) OSC Compensation Data Sheet September 23, 2005
2 FN8097.2 September 23, 2005 PIN DESCRIPTIONS PIN ASSIGNMENTS NC = No internal connection VBACK VCC IRQ SCL SDA VSS
8 Ld TSSOP
8 Ld SOIC
Ordering Information
PART NUMBER PART MARKING V CC RANGE (V) TEMP RANGE (°C) PACKAGE X1205S8* X1205 2.7 to 5.5 0 to 70 8 Ld SOIC (150 mil) X1205S8Z* (Note) X1205 Z 0 to 70 8 Ld SOIC (150 mil) (Pb Free) X1205S8I* X1205 I -40 to 85 8 Ld SOIC (150 mil) X1205S8IZ* (Note) X1205 Z I -40 to 85 8 Ld SOIC (150 mil) (Pb Free) X1205V8* 1205 0 to 70 8 Ld TSSOP (4.4mm) X1205V8Z* (Note) 1205 Z 0 to 70 8 Ld TSSOP (4.4mm) (Pb-free) X1205V8I* 1205I -40 to 85 8 Ld TSSOP (4.4mm) X1205V8IZ* (Note) 1205I Z -40 to 85 8 Ld TSSOP (4.4mm) (Pb-free) *Add “T1” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Number Symbol Brief DescriptionSOIC TSSOP 13 X 1 X1. The X1 pin is the input of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal. 24 X 2 X2. The X2 pin is the output of an inverting amplifier and should be connected to one pin of a 32.768kHz quartz crystal. 35 I R Q Interrupt Output – IRQ. This is an interrupt signal output. This signal notifies a host proces- sor that an alarm has occurred and requests action. It is an open drain active low output. 46 V SS VSS. 57 S D A Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. 68 S C L Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. 71 V BACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. 82 V CC VCC. X1205
3 FN8097.2 September 23, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on V CC, VBACK and IRQ Voltage on SCL, SDA, X1 and X2 above V CC or VBACK (whichever is higher) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied. Exposure to absolute max- imum rating conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.) OPERATING CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Unit Notes VCC Main Power Supply 2.7 5.5 V VBACK Backup Power Supply 1.8 5.5 V VCB Switch to Backup Supply V BACK -0.2 V BACK -0.1 V VBC Switch to Main Supply V BACK VBACK +0.2 V Symbol Parameter Conditions Min Typ Max Unit Notes ICC1 Read Active Supply Current VCC = 2.7V 400 µA 1, 5, 7, 14 VCC = 5.0V 800 µA ICC2 Program Supply Current (nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14 VCC = 5.0V 3.0 mA ICC3 Main Timekeeping Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15 VCC = 5.0V 20 µA IBACK Timekeeping Current V BACK = 1.8V 1.25 µA 3, 6, 9, 14, 15 “See Perfor- mance Data”VBACK = 3.3V 1.5 µA ILI Input Leakage Current 10 µA 10 ILO Output Leakage Current 10 µA 10 VIL Input LOW Voltage -0.5 V CC x 0.2 or VBACK x 0.2 V1 3 VIH Input HIGH Voltage V CC x 0.7 or VBACK x 0.7 VCC + 0.5 or VBACK + 0.5 V1 3 VHYS Schmitt Trigger Input Hysteresis VCC related level .05 x V CC or .05 x VBACK V1 3 VOL Output LOW Voltage for SDA/IRQ VCC = 2.7V 0.4 V 11 VCC = 5.5V 0.4 X1205
Byte are incorrect or until 200nS after a stop ending a read or write operation. (2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC. (4) For reference only and not tested. (13)Threshold voltages based on the higher of Vcc or Vback. (14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Notes: (1) This parameter is not 100% tested. Figure 1. Standard Output Load for testing the device with VCC = 5.0V
5 FN8097.2 September 23, 2005 AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50 (1) ns tAA SCL LOW to SDA Data Out Valid 0.9 µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (1)(2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (1)(2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR X1205
6 FN8097.2 September 23, 2005 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time V CC is stable until the specified operation can be initiated. These parameters are not 100% tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec. (2) Typical values are for T A = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ. (1) Max. Units tWC(1) Write Cycle Time 5 10 ms SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition X1205
8 FN8097.2 September 23, 2005 on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. Writing to the Real Time Clock The time and date may be set by writing to the RTC registers. To avoid changing the current time by an uncompleted write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ACK bit before the RTC data input bytes, the clock continues to run. The new serial input data replaces the values in the buffer. This new RTC value is loaded back into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation the RTC will reflec t the newly loaded data beginning with the next “one second clock cycle” after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any nonvolatile write sequences. A single byte may be written to the RTC without affecting the other bytes. Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC perfor- mance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Inte rsil’s RTC family provides on-chip crystal compensation networks to adjust load- capacitance to tune oscilla tor frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section. CLOCK/CONTROL REGISTERS (CCR) The Control/Clock Registers are located in an area accessible following a slave byte of “1101111x” and reads or writes to addre sses [0000h:003Fh]. The clock/control memory map has memory addresses from 0000h to 003Fh. The defined addresses are described in the Table 1. Writing to and reading from the undefined addresses are not recommended. CCR access The contents of the CCR can be modified by perform- ing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a two step process (See section “Writing to the Clock/Control Registers.”) The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes; non-volatile) 2. Alarm 1 (8 bytes; non-volatile) 3. Control (4 bytes; non-volatile) 4. Real Time Clock (8 bytes; volatile) 5. Status (1 byte; volatile) Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another sec- tion requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read or write can begin at any address in the CCR. It is not necessary to set th e RWEL bit prior to writing the status register. Sect ion 5 supports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a ran- dom read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by perfor ming a sequential read. The read instructio n latches all Clock registers into a buffer, so an update of t he clock does not change the time being read. A sequential read of the CCR will not result in the output of dat a from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execut e a current address read of the CCR and continue reading the next Register. ALARM REGISTERS There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24 hour time selection bit. The enable bits specify which registers to use in the comparison between the Alarm and Real Time Registers. For example: – Setting the Enable Month Bit (EMOn*) bit in combi- nation with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year. *n = 0 for Alarm 0: N = 1 for Alarm 1 X1205
and MNAn* registers are set to 9:30PM. default value is defined as ‘0’.
24 Hour Time
for the leap year in the year 2100. the Clock/Control Registers (CCR). Table 1. Status Register (SR) bits that are set when an SR read starts will be reset.
Table 2. Clock/Control Memory Map
0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 20h
0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h
0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h
0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h
0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h
0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h
0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h
0013 Control
0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h
0011 INT IM AL1E AL0E 0 0 X X X 00h
0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h
0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h
0007 Alarm0
0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h
0005 YRA0 Unused – Default = RTC Ye ar value – Future expansion
0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h
0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h
0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h
0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h
0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h
during a SR read will contain zeros in these bit locations. AL1E and AL0E bits are set to “1”, respectively. regardless of whether the IRQ interrupt is enabled. register containing the bits. rate set by the time setting fo the alarm. is set, then this pulse will be periodic. the ppm error to achieve better accuracy. adjustment and DTR0 gives 20 ppm adjustment. Table 3. Digital Trimming Registers vided to adjust the on-chip loading capacitance range. from 3.25pF to 18.75pF in 0.25pF steps. tance in addition to the ATR value. ceeded by a start and ended with a stop).
0 Single Time Event Set By Alarm
1 Repetitive / Recurring Time Event Set By Alarm
write. The contents of the array are not affected. write operation, the RWEL bit will be set to 0. Address Read, Random Read, and Sequential Read. acknowledge, and data transfer sequence. the ninth clock cycle and then issue a stop condition. must first perform a “dummy” write operation. address, acknowledge, and data transfer sequence. needs to read, but is not ready for the data. with an acknowledge and then issuing a stop condition. address n followed by the data from address n + 1. Figure 9. Current Address Read Sequence
summarizes these parameters. Table 4. Crystal Parameters Required for Intersil RTC’s Table 5. Crystal Manufacturers Manufacturer Part Number Temp Range +25°C Freq Toler.
note AN154 on Intersil’s website at www.intersil.com. a suggested layout for the X1205 SOIC device. Figure 12. Suggested Layout for Intersil RTC in SO-8 circuit will begin to oscillate. the proper crystal and layout). functions as an indication of proper oscillation. may disappear intermittently for short periods of time.
charge a battery (especially lithium batteries!). Figure 13. Supercapactor charging circuit or the battery will be drained. Table 6. Battery Backup Operation
- Example Application, Vcc=5V, Vback=3.0V
- Example Application, Vcc=3.3V,Vback=3.0V
down, the serial interface will most likely be inactive. which may be needed to get safety agency approval. non-volatile writes will require higher supplier current. Figure 14. I
21 FN8097.2 September 23, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic, SOIC, Package Code S8 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical
8 PlacesFOOTPRINT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8097.2 September 23, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Code V8 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical X1205