DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Recommended Operating Conditions
- 2.3 Thermal Information
- 2.4 Electrical Specifications
- 5.1 Default Start-up
- 5.2 Logic Control
- 5.3 Power Supplies
- 5.4 Control Pin Interface
- 6.1 Board Images
- 6.2 Setup and Configuration
- 6.3 Application Circuit
- 6.4 Bill of Materials
Features
■ High Isolation:
- 74dB at 1GHz
- 73dB at 2GHz
- 70dB at 3GHz
- 66dB at 4GHz ■ High Linearity:
- IIP3 of 61dBm at 2GHz ■ Wide single 2.75V to 5.25V supply voltage range ■ 3.3V and 1.8V compatible control logic ■ Operating temperature -40°C to +105°C ■ 3 × 3 mm 16-VFQFPN package
Applications
■ Base Station 2G, 3G, 4G, 5G ■ Portable Wireless ■ Repeaters and E911 systems ■ Digital Pre-Distortion ■ Point to Point Infrastructure ■ Public Safety Infrastructure ■ WIMAX Receivers and Transmitters ■ Military Systems and JTRS radios ■ RFID handheld and portable readers ■ Test / ATE Equipment
1.1 Pin Assignments
1.2 Pin Descriptions
Table 1. Pin Descriptions is not 0V DC then an external coupling capacitor must be used. high puts the part in all paths off state and disables the control of VCTL (Table 2). as close as possible to pin.
X0010823 Rev.1.1 Apr 28, 2021 Page 5 2. Specifications
2.1 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the F2934 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Parameter Symbol Minimum Maximum Unit VDD to GND VDD -0.3 +5.5 V VCTL, EN to GND Vlogic -0.3 3.6 V RF1, RF2, RFC to GND VRF -0.3 +0.3 V RF Input Power [1] RF1 or RF2 as an input (Connected to RFC) PRF12 36 [2] dBm RFC as an input (Connected to RF1 or RF2) PRFC 36 RFC as an input (All off state) PRFC_OFF 30 RF1 or RF2 as input (Terminated states) PRF12_TERM 30 [2] RF1 and RF2 as inputs (All off state) PRF12_OFF 30 [2] Maximum Junction Temperature TJmax +125 °C Storage Temperature Range TST -65 +150 °C Lead Temperature (soldering, 10s) TLEAD +260 °C ESD Voltage – HBM (Per JESD22-A114) VESDHBM 1000 V ESD Voltage – CDM (Per JESD22-C101) VESDCDM 500 V 1. VDD = 2.7V to 5.25V, 250MHz ≤ FRF ≤ 6000MHz, Tc = 105°C, ZS = ZL = 50Ω. 2. Each port.
X0010823 Rev.1.1 Apr 28, 2021 Page 6
2.2 Recommended Operating Conditions
Parameter Symbol Conditions Minimum Typical Maximum Unit Supply Voltage VDD 2.7 5.25 V Operating Temperature Range TCASE Exposed Paddle Temperature -40 +105 ºC RF Frequency Range FRF 50 6000 MHz RF Continuous Input CW Power (Non-Switched) PRF RFC connected to RF1 or RF2 [2] TC = 85ºC 34 dBm TC = 105ºC 34 RF1/ RF2 Input, Terminated State [3][4] TC = 85ºC 27 TC = 105ºC 27 RFC Input, All off State TC = 85ºC 27 TC = 105ºC 27 RF Continuous Input Power (RF Hot Switching CW) [1] PRFSW RFC Input, switching between RF1 and RF2. TC = 85ºC 30 dBm TC = 105ºC 30 RFC Input, switching into or out of, All off State. TC = 85ºC 27 TC = 105ºC 27 RF1 or RF2 as input, switched between RFC and Term. TC = 85ºC 27 TC = 105ºC 27 RF1 and RF2 as inputs, switching into or out of All off State. [4] TC = 85ºC 27 TC = 105ºC 27 RF1/2 Port Impedance ZRFx 50 Ω RFC Port Impedance ZRFC 50 Ω RF frequency. 2. Input could be: RFC, RF1, or RF2 (applied to only one input). 3. Any RF1 / RF2 termination state. Power level specified is for each port. 4. Power level specified is for each port.
Figure 2. Maximum RF Input Operating Power vs. Frequency
2.3 Thermal Information
X0010823 Rev.1.1 Apr 28, 2021 Page 8
2.4 Electrical Specifications
Typical Application Circuit, VDD = 5.0V, TC = +25°C, FRF = 2000MHz, Driven Port = RF1, RF2, input power = 10dBm, ZS = ZL = 50Ω, PCB board trace and connector losses are de-embedded unless otherwise noted. Parameter Symbol Test Conditions Min Typ Max Unit Logic Input High Threshold VIH 1.1 3.6 V Logic Input Low Threshold VIL -0.3 0.6 V Logic Current IIH, IIL For each control pin -1 +1 µA DC Current IDD VDD = 3.3 V 205 400 [1] µA VDD = 5.0 V 250 450 Insertion Loss RFC to RF1 / RF2 IL 50MHz 0.7 dB 1GHz 0.8 2GHz 0.8 1 3GHz 0.9 4GHz 0.9 6GHz 1.1 Isolation RFC to RF1 / RF2 ISOCS 50MHz 74 [2] 79 dB 1GHz 71 74 2GHz 69 73 3GHz 65 70 4GHz 60 66 6GHz 50 53 Isolation RF1 to RF2 ISOX 50MHz 86 dB 1GHz 62 2GHz 57 3GHz 53 4GHz 50 6GHz 46 Return Loss RFC, RF1, RF2 RFRL 50MHz 25 dB 1GHz 28 2GHz 26 3GHz 22 4GHz 18
X0010823 Rev.1.1 Apr 28, 2021 Page 9 Parameter Symbol Test Conditions Min Typ Max Unit 6GHz 21 Return Loss RF1, RF2 terminated RFTRL 50MHz 25 dB 1GHz 26 2GHz 28 3GHz 22 4GHz 18 6GHz 19 Input 1dB Compression ICP1dB 50MHz 33 dBm 1GHz 35 2GHz 36 3GHz 36 4GHz 35 Input 0.1dB Compression [3] ICP0.1dB VDD = 5.0 V 50MHz 34 dBm 2GHz 33.5 3GHz 33.5 4GHz 33.5 VDD = 3.1 V 50MHz 33.5 2GHz 34 3GHz 34 4GHz 33 Input IP3 IIP3 RF Input = RF1 or RF2 PIN = +15 dBm/tone Δ F = 1MHz 50MHz 62 dBm 1GHz 61 2GHz 62 2.5GHz 62.5 4GHz 61.5 Non-RF Driven Spurious [4] SpurMAX At any RF port when externally terminated to 50Ω (RBW = 100Hz) -114 dBm Switching Time [5] TSW 50% control to 90% RF 325 ns 50% control to 10% RF 255 Maximum Switching Rate [6] 25 kHz 1. Items in minimum/maximum columns in bold italics are confirmed by Test. 2. Items in minimum/maximum columns that are not bold/italics are confirmed by Design Characterization.
- The input 0.1dB compression point is a linearity figure of merit. For the maximum operating power levels, see Recommended
- Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 5.2MHz.
- Minimum time required between switching of states = 1 / Maximum Switching Rate.
Table 2. Switch Control Truth Table
- Typical Performance Graphs
■ PIN = 0 dBm for all small signal tests. ■ PIN = +15 dBm/tone applied to RF1 or RF2 port for two tone linearity tests. ■ Two-tone frequency spacing = 1MHz. ■ RF1 or RF2 is the driven RF port and RFC is the output port. ■ All unused RF ports terminated into 50Ω. ■ For Insertion Loss and Isolation plots, RF trace and connector losses are de-embedded. specific path, refer to the online S-Parameter file.
5.1 Default Start-up
There are no internal pull-up or pull-down resistors on the VCTL or EN pins.
5.2 Logic Control
Control pins VCTL and EN are used to set the state of the SP2T switch (see Table 2).
5.3 Power Supplies
voltage ramps or while it returns to zero.
5.4 Control Pin Interface
(VCTL) and pin 5 (EN) as shown below. Figure 18. Typical Application Circuit
6.1 Board Images
Figure 19. Evaluation Board – Top View Figure 20. Evaluation Board – Bottom View
X0010823 Rev.1.1 Apr 28, 2021 Page 16
6.2 Setup and Configuration
6.2.1. External Supply Setup Set up a VCC power supply in the voltage range of 2.7V to 5.25V and disable the power supply output. 6.2.2. Logic Control Setup Using the evaluation board to manually set the control logic: On connector J6 connect a 2-pin shunt from pin 3 (VCC) to pin 4 (VLOGIC). This connection provides the VCC voltage supply to the Eval Board logic control pull up network. Resistors R5 and R6 form a voltage divider to set the Vhigh level over the 2.7V to 5.25V VCC range for manual logic control. Connector J6 has 2 logic input pins: EN (pin 5) and VCTL (pin 7). See Table 2 for Logic Truth Table. With the pull- up network enabled (as noted above) these pins can be left open to provide a logic high through pull-up resistors R3 and R4. To set a logic low for EN and VCTL connect 2-pin shunts on J6 from pin 5 (EN) to pin 6 (GND) and from pin 7 (VCTL) to pin 8 (GND). Note that when using the on board R5 / R6 voltage divider the current draw from the VCC supply will be higher by approximately VCC / 37kΩ. Using external control logic: External logic controls are applied to J6 pin 5 (EN) and pin 7 (VCTL). See Table 2 for Logic Truth Table. 6.2.3. Turn On Procedure Setup the supplies and Evaluation Board as noted in the External Supply Setup and Logic Control Setup sections above. Connect the preset disabled VCC power supply to the red VCC loop and ground to GND1 or GND2. Enable the VCC supply. Set the desired logic setting using J6 pin 5 (EN) and pin 7 (VCTL) to achieve the desired Table 2 setting. Note that external control logic should not be applied without VCC being present. 6.2.4. Turn Off Procedure If using external control logic for EN and VCTL then set them to a logic low. Disable the VCC supply.
6.3 Application Circuit
6.4 Bill of Materials
Table 3. Bill of Materials (BOM) Qty Ref. Designator Description Mfr. Part # Mfr.
0 C1 Not Installed (0402)
0 C3, C4, C6 Not Installed (0402)
1 C5 100pF ±5%, 50V, C0G, Ceramic Capacitor (0402) GRM1555C1H101J Murata
2 R1, R2 100Ω ±1%, 1/10W, Resistor (0402) ERJ-2RKF1000X Panasonic
2 R3, R4 100kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1003X Panasonic
1 R5 15kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1502X Panasonic
1 R6 22kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF2202X Panasonic
1 F2934 SP2T Switch 3 mm x 3 mm QFN16-EP F2934NTGI8 Renesas
1 Printed Circuit Board F2934 EVKIT REVA Renesas
X0010823 Rev.1.1 Apr 28, 2021 Page 18 7. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 8. Ordering Information Part Number Package Description Carrier Type Temperature Range F2934NTGI8 3 × 3 mm, 16-VFQFPN Tape and Reel -40 to +85°C 9. Revision History Revision Date Description
1.1 Apr 28, 2021 Updated Figure 9 and Figure 10
1.0 Mar 9, 2021 Initial release.
© Integrated Device Technology, Inc.
© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionRev 02Add "K" Value 0.20 MinimumSept 5, 2018Rev 03Correct Typo Error MinimumJuly 8, 2019
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2020 Renesas Electronics Corporation. All rights reserved.