WP1602B-Y-JCS

WP1602B-Y-JCS DBLECTRO | Alldatasheet

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第 4 頁，共 19 頁 1.Module Classification Information W P 1 6 0 2 B －Y－ J C S c d e f g ○ ,6 c Brand：DB LECTRO Inc. d Display Type：H→ Character Type, G→ Graphic Type , P→ PLED e Display Font：Character 16 words, 2Lines. f Model serials no. g Backlight Type： Y → Yellow Green ErrSpecial Code JCS: English and Japanese standard font 2.Precautions in use of PLED Modules (1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don’t make extra holes on the printed circuit board, modify its shape or change the components of PLED module. (3)Don’t disassemble the PLEDM. (4)Don’t operate it above the absolute maximum rating. (5)Don’t drop, bend or twist PLEDM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment. 3.General Specification Item Dimension Unit Number of Characters 16 characters x 2 Lines － Module dimension 80.0 x 36.0 x 9.7(MAX) mm View area 66.0 x 16.0 mm Active area 50.67 x 10.36 mm Dot size 0.51 x 0.60 mm Dot pitch 0.54 x 0.63 mm Character size 2.67 x 5.01 mm Character pitch 3.20 x 5.35 mm LCD type PLED , Green

第 5 頁，共 19 頁 Duty 1/16 4.Absolute Maximum Ratings Item Symbol Min Typ Max Unit Operating Temperature T OP -20 25 +50 ℃ Storage Temperature T ST -30 － +70 ℃ Input V oltage V I -0.3 － VDD V Supply V oltage For Logic V DD-VSS -0.3 － 7 V Supply V oltage For LCD V BT- VSS -0.3 － 5.0 V 5.Electrical Characteristics Item Symbol Condition Min Typ Max Unit Supply V oltage For Logic V DD-VSS － 4.5 5.0 5.5 V Supply V oltage For LCD V BT Ta=25℃ 2.0 2.5 5.0 V Input High V olt. V IH － 0.7 VDD － VDD V Input Low V olt. V IL － -0.3 － 0.55 V Output High V olt. V OH － 2.4 － － V Output Low V olt. V OL － － － 0.4 V Supply Current I DD V DD=5V － 0.35 0.6 mA 6.Optical Characteristics Item Symbol Condition Min Typ Max Unit

第 6 頁，共 19 頁 (V)θ 80 deg View Angle (H)φ 80 deg Contrast Ratio CR 100 lux － 100 － － T rise － 10 us Response Time T fall － 10 us Brightness With polarizer 40 nits 7.Interface Pin Function Pin No. Symbol Level Description

1 V SS 0V Ground

2 V DD 5.0V Supply V oltage for logic 3 ※VBT (Variable) Operating voltage for PLED Brightness adjhstment

4 RS H/L H: DATA, L: Instruction code

5 R/W H/L H: Read(MPU→ Module) L: Write(MPU→ Module)

6 E H,H→ L Chip enable signal

7 DB0 H/L Data bit 0

8 DB1 H/L Data bit 1

9 DB2 H/L Data bit 2

10 DB3 H/L Data bit 3

11 DB4 H/L Data bit 4

12 DB5 H/L Data bit 5

13 DB6 H/L Data bit 6

14 DB7 H/L Data bit 7

15 NC －

16 NC －

第 7 頁，共 19 頁 ※Brightness Control VBT Brightness(nits) Power consump tion(measured with random texts) 2.5V 20(typical) 50mW 3.0V 45(typical) 63mW Note:1.When random texts pattern is running,averagely,at any instance,about 1/4 of pixels will be on. 2.If VBT is not operated within 2V and 3V ,non-uniformity display may occur. 3.You have to use the saving mode by VBT 2.5V in order to make long life. 8.Contour Drawing &Block Diagram

第 8 頁，共 19 頁 312 456789 1 0 1 4 1211 13 16 15Character located DDRAM address DDRAM address MPU 80 series RS R/W E DB0~DB7 or 68 series Controller/Com Driver 16X2 LCD Com1~16 Seg1~40 D Seg Driver M CL1 CL2 Seg41~80 Vdd,Vss,Vbt Bias and Power Circuit Vdd Vbt Vss 4.6 75.02.5 40.55 80.0 0.5 36.0 0.5 5.7 10.3 13.12 31.0 2.5 18.3 4.95 7.55 15.21 8.0 P2.54*15=38.1 1.8 16- 1.0PTH 9.7Max 4.9 1.6 4- 2.5 PTH 4- 5.0 PAD 25.2 16.0(VA) 10.36(AA) 71.2 64.0(VA) 50.67(AA) Vss RS R/W Vo DB2 DB0 DB1 E Vdd DB6 DB4 DB5 NC NC DB7

10 DB3

0.34 0.53 0.51 0.54 2.67 0.60.635.01 DOT SIZES 1 16

第 9 頁，共 19 頁 9.Function Description The LCD display Module is built in a LSI contro ller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores da ta to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (R S) signal, these two registers can be selected. RS R/W Operation 0 0 IR write as an internal op eration (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB7) 1 0 Write data to DDRAM or CG RAM (DR to DDRAM or CGRAM) 1 1 Read data from DDRAM or CG RAM (DDRAM or CGRAM to DR) Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 a nd R/W=1, the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80×8 bits or 80 characters. Below figur e is the relationships between DDRAM addresses and positions on the liquid crystal display. AC (hexadecimal) High bits Low bits AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0 Example: DDRAM addresses 4E

第 10 頁，共 19 頁 Character Generator ROM (CGROM) The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewr ite character by program. For 5 ×8 dots, eight character patterns can be written, and for 5×10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM. Display position DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 2 - L i n e b y 1 6 - C h a r a c t e r D i s p l a y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

第 11 頁，共 19 頁 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1. For 5 * 8 dot character patterns Char act er Codes ( DDRAM dat a ) CGRAM Addr ess Character Patterns ( CGRAM dat a ) 543210675 4 3 2 0 17 6 5 4 3 2 1 0 000 001 100 101 010 011 110 111 000 001 100 101 010 011 110 111 000 001 010 011 110 111 * * * * * * * * 00000 * * * * * * * * 00000 00 00 00 00 00 00 000 000 000 00 0 00 0 000 000 000 001 * * 1110000 *111 0000 * 000 0000 * 001 H igh L ow H igh L ow H igh L ow For 5 * 10 dot character patterns Char act er Codes ( DDRAM dat a ) CGRAM Addr ess Character Patterns ( CGRAM dat a ) H igh L ow 4563 2 1 0 H igh L ow 543210 H igh L ow 7654 1 230 * 00000 00000* * * * * * * * * *** 0000 0001 0010 0011 0100 0101 0110 0111 1000 100 1 1010 1111 00000 0000 * 000 00 000 000 0000 0000 0000 Character pattern( 1 ) Cursor pattern Character pattern( 2 ) Cursor pattern Character pattern Cursor pattern : " H igh "

第 12 頁，共 19 頁 10.Character Generator ROM Pattern Table.2 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL Upper 4 bit Lower 4 bit LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH HHHH CG RAM ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 )

第 13 頁，共 19 頁 11.Instruction Table Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution time (fosc=270Khz) Clear Display 0 0 0 0 0 0 0 0 0 1 Write “00H” to DDRAM and set DDRAM address to “00H” from AC 1.52ms Return Home 0 0 0 0 0 0 0 0 1 － Set DDRAM address to “00H” from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. 1.52ms Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH Assign cursor moving direction and enable the shift of entire display. I/D=1:Increment；0: Decrement SH=1:Display shift on 37μ s Display ON/OFF Control 0 0 0 0 0 0 1 D C B Set display (D), cursor (C), and blinking of cursor (B) on/off control bit. D=1:Display on C=1:Cursor display on B=1:Cursor blink on 37μ s Cursor or Display Shift 0 0 0 0 0 1 S/C R/L － － Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. S/C=1:Shift display ；0:Move cursor R/L=1:Shift right；0:Shift leftf 37μ s Function Set 0 0 0 0 1 DL N F － － Set interface data length (DL) DL=1:8-bit；0:4-bit Set numbers of display lines(N) N=1:Dual line；0:Single line Set display font type (F) F=1:5x10 dots；0:5x8dots 37μ s Set CGRAM Address 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 37μ s Set DDRAM Address 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 37μ s Read Busy Flag and Address 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether during internal operation or not can be known by reading BF. The contents of address counter can also be read. BF=1:Internal operation BF=0:Ready for instruction 0μ s Write Data to RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). 37μ s Read Data from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM (DDRAM/CGRAM). 37μ s

第 14 頁，共 19 頁 12.Timing Characteristics

12.1 Write Operation

Item Symbol Min Typ Max Unit Enable cycle time t cycE 500 － － ns Enable pulse width (high level) PW EH 230 － － ns Enable rise/fall time t Er,tEf － － 20 ns Address set-up time (RS, R/W to E) t AS 40 － － ns Address hold time t AH 10 － － ns Data set-up time t DSW 80 － － ns Data hold time t H 10 － － ns VIH1 VIL1 VIH1 VIL1 VIL1 tcycE VIH1 VIL1 VIH1 VIL1 VIL1 tAS tAH tAH tEf tHtDSW PWEH tEr VIL1 VIH1 VIL1 VIH1 VIL1 RS R/W E DB0 to DB7 Valid data

第 15 頁，共 19 頁

12.2 Read Operation

Item Symbol Min Typ Max Unit Enable cycle time t cycE 500 － － ns Enable pulse width (high level) PW EH 230 － － ns Enable rise/fall time t Er,tEf － － 20 ns Address set-up time (RS, R/W to E) t AS 40 － － ns Address hold time t AH 10 － － ns Data delay time t DDR － － 160 ns Data hold time t DHR 5 － － ns VIH1 VIL1 VIH1 VIL1 tcycE VOH1 VOL1* tAS tAH tAH tEf tDHR PWEH tEr VIL1 VIH1 VIL1 VIH1 VIL1 RS R/W E DB0 to DB7 VIH1 VIH1 VOH1 *VOL1Valid data tDDR NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation.

第 16 頁，共 19 頁 13.Initializing of LCM Power on RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 000011** Wait for more than 15 ms after VCC rises to 4.5 V Wait for more than 4.1 ms DB4DB7 RS R/W DB6 DB5 DB1DB2DB3 DB0 Wait for more than 100 µs DB4 DB7R/WRS DB5DB6 001 DB1DB3 DB2 * DB0 DB4DB7 RS R/W 100 DB6 DB5 DB1 F*N DB2DB3 DB0 0000001000 0000000001

00000001 I/D S

BF can not be checked before this instruction. Function set ( Interface is 8 bits long. ) Function set ( Interface is 8 bits long. ) BF can not be checked before this instruction. BF can not be checked before this instruction. Function set ( Interface is 8 bits long. ) BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. Function set ( Interface is 8 bits long. Specify the number of display lines and font. ) The number of display lines and character font can not be changed after this point. 8-Bit Ineterface Display off Display clear Entry mode set

第 17 頁，共 19 頁 Power on RS R/W DB7 DB6 DB5 DB4 000011 Wait for more than 15 ms after VCC rises to 4.5 V Wait for more than 4.1 ms Wait for more than 100 µs DB4DB7 RS R/W 100 DB6 DB5 000010 00N F** 000000 Initialization ends BF can not be checked before this instruction. Function set ( Interface is 8 bits long. ) Function set ( Interface is 8 bits long. ) BF can not be checked before this instruction. BF can not be checked before this instruction. Function set ( Interface is 8 bits long. ) BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. Function set ( Set interface to be 4 bits long. ) Interface is 8 bits in length. Function set ( Interface is 4 bits long. Specify the number of display lines and character font. ) The number of display lines and character font can not be changed after this point. Display off Display clear Entry mode set 4-Bit Ineterface DB6RS R/W DB7 DB4DB5 DB6 RS R/W DB7 DB4DB5 001000 000000 000001 000000

000 I/D S1

第 18 頁，共 19 頁 14.Quality Assurance Screen Cosmetic Criteria Item Defect Judgment Criterion Partition

1 Spots

A)Clear Size: d mm Acceptable Qty in active area d ≦ 0 . 1 D i s r e g a r d 0.1<d ≦ 0 . 2 6 0.2<d ≦ 0 . 3 2 0 . 3 < d 0 Note: Including pin holes and defective dots which must be within one pixel size. B)Unclear S i z e : d m m Acceptable Qty in active area d ≦ 0 . 2 D i s r e g a r d 0 . 2 < d ≦ 0 . 5 6 0 . 5 < d ≦ 0 . 7 2 0 . 7 < d 0 Minor

2 Bubbles in Polarize

Size: d mm Acceptable Qty in active area d ≦ 0 . 3 D i s r e g a r d 0 . 3 < d≦ 1 . 0 3 1 . 0 < d≦ 1 . 5 1 1 . 5 < d 0 Minor

3 Scratch

In accordance with spots cosmetic criteria. When the light reflects on the panel surface, the scratches are not to be remarkable. Minor

4 Allowable Density Above defects should be separated more than 30mm each

other. Minor

5 Coloration

Not to be noticeable coloration in the viewing area of the LCD panels. Back-light type should be judged with back-light on state only. Minor

第 19 頁，共 19 頁 15.Reliability Content of Reliability Test Environmental Test Test Item Content of Test Test Condition Applicable Standard High Temperature storage Endurance test applying the high storage temperature for a long time. 70℃ 200hrs Low Temperature storage Endurance test applying the high storage temperature for a long time. -30℃ 200hrs High Temperature Operation Endurance test applying the electric stress (V oltage & Current) and the thermal stress to the element for a long time. 50℃ 200hrs Low Temperature Operation Endurance test applying the electric stress under low temperature for a long time. -20℃ 200hrs High Temperature/ Humidity Storage Endurance test applying the high temperature and high humidity storage for a long time. 70℃,90%RH 96hrs High Temperature/ Humidity Operation Endurance test applying the electric stress (V oltage & Current) and temperature / humidity stress to the element for a long time. 50℃,90%RH 96hrs Temperature Cycle Endurance test applying the low and high temperature cycle. - 2 0 ℃ 2 5 ℃ 5 0 ℃ 3 0 m i n 5 m i n 3 0 m i n 1 c y c l e -20℃/50℃ 10 cycles Mechanical Test Vibration test Endurance test applying the vibration during transportation and using. 10~22Hz→ 1.5mmp-p 22~500Hz→ 1.5G Total 0.5hrs Shock test Constructional and mechanical endurance test applying the shock during transportation. 50G Half sign wave 11 msedc 3 times of each direction Atmospheric pressure test Endurance test applying the atmospheric pressure during transportation by air. 115mbar 40hrs —— Others Static electricity test Endurance test applying the electric stress to the terminal. VS=800V ,RS=1.5kΩ CS=100pF 1 time ***Supply voltage for logic system=5V . Supply voltage for LCD system =Operating voltage at 25℃