WMF512K8-60DEC5

WMF512K8-XXX5 WEDC | Alldatasheet

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White Electronic Designs WMF512K8-XXX5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.comNovember 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 512Kx8 MONOLITHIC FLASH, SMD 5962-96692

FEATURES

/square6 Access Times of 60, 70, 90, 120, 150ns /square6 Packaging

• 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ (Package 101)
• 32 pin, Rectangular Ceramic Leadless Chip Carrier (Package 601)
• 32 lead Flatpack (Package 220) /square6 1,000,000 Erase/Program Cycles Minimum /square6 Sector Erase Architecture
• 8 equal size sectors of 64K bytes each
• Any combination of sectors can be concurrently erased. Also supports full chip erase /square6 Organized as 512Kx8 /square6 Commercial, Industrial and Military Temperature Ranges /square6 5 Volt Programming. 5V ± 10% Supply. /square6 Low Power CMOS /square6 Embedded Erase and Program Algorithms /square6 TTL Compatible Inputs and CMOS Outputs /square6 Page Program Operation and Internal Program Control Time. Note: For programming information refer to Flash Programming 4M5 Application Note. This product is subject to change without notice. Pin Confi guration For WMF512K8-XXX5 Pin Description A0-18 Address Inputs I/O0-7 Data Input/Output CS# Chip Select OE# Output Enable WE# Write Enable VCC +5.0V Power VSS Ground A18 A16 A15 A12 I/O0 I/O1 I/O2 V SS VCC WE# A17 A14 A13 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 Top View

32 DIP

32 CSOJ

32 Flatpack

OE# A10 CS# I/O7 A12 A15 A16 A18 V CC WE# A17 Pin Confi guration For WMF512K8-XCLX5 Top View

32 CLCC

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS (1) Parameter Unit Operating Temperature -55 to +125 °C Supply Voltage (V Signal Voltage Range(any pin except A9) (2) -2.0 to +7.0 V Storage Temperature Range -65 to +150 °C Lead Temperature (soldering, 10 seconds) +300 °C Data Retention Mil Temp 20 years Endurance - erase/program cycles (Mil Temp) 100,000 min cycles A9 Voltage for sector protect (V NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot V SS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns. DC CHARACTERISTICS — CMOS COMPATIBLE VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Conditions Min Max Unit Input Leakage Current I LI VCC = 5.5, VIN = GND to VCC 10 µA Output Leakage Current I LOx32 VCC = 5.5, VIN = GND to VCC 10 µA VCC Active Current for Read (1) I CC1 CS# = VIL, OE# = VIH, f = 5MHz 50 mA VCC Active Current for Program or Erase (2) I CC2 CS# = VIL, OE# = VIH 60 mA VCC Standby Current I CC4 VCC = 5.5, CS# = VIH, f = 5MHz 1.6 mA Output Low Voltage V OL IOL = 8.0 mA, VCC = 4.5 0.45 V Output High Voltage V OH1 IOH = -2.5 mA, VCC = 4.5 0.85 x V CC V Low VCC Lock-Out Voltage V LKO 3.2 4.2 V NOTES: 1. The I CC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. I CC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: V IL = 0.3V, VIH = VCC - 0.3V RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.0 V CC + 0.5 V Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) T A -55 +125 °C Operating Temp. (Ind.) T A -40 +85 °C A9 Voltage for Sector Protect V ID 11.5 12.5 V CAPACITANCE TA = +25°C Parameter Symbol Conditions Max Unit Address Input capacitance CAD VI/O = 0 V, f = 1.0 MHz 15 pF Output Enable capacitance COE VIN = 0 V, f = 1.0 MHz 15 pF Write Enable capacitance CWE VIN = 0 V, f = 1.0 MHz 15 pF Chip Select capacitance CCS VIN = 0 V, f = 1.0 MHz 15 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 15 pF This parameter is guaranteed by design but not tested.

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Write Cycle Time t AVAV tWC 60 70 90 120 150 ns Write Enable Setup Time t WLEL tWS 00000 n s Chip Select Pulse Width t ELEH tCP 40 45 45 50 50 ns Address Setup Time t AVEL tAS 00000 n s Data Setup Time t DVEH tDS 40 45 45 50 50 ns Data Hold Time t EHDX tDH 00000 n s Address Hold Time t ELAX tAH 40 45 45 50 50 ns Chip Select Pulse Width High t EHEL tCPH 20 20 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 300 300 µs Sector Erase Time (2) t WHWH2 15 15 15 15 15 sec Read Recovery Time t GHEL 00000 n s Chip Programming Time 11 11 11 11 11 sec Chip Erase Time (3) 64 64 64 64 64 sec NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase time is 8sec. AC TEST CIRCUIT AC Test Conditions Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. I Current Source D.U.T. C = 50 pfeff IOL V 1.5V (Bipolar Supply) Z Current Source OH

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. AC CHARACTERISTICS – READ ONLY OPERATIONS VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Read Cycle Time t AVAV tRC 60 70 90 120 150 ns Address Access Time t AVQV tACC 60 70 90 120 150 ns Chip Select Access Time t ELQV tCE 60 70 90 120 150 ns Output Enable to Output Valid t GLQV tOE 35 35 35 50 55 ns Chip Select to Output High Z (1) t EHQZ tDF 20 20 20 30 35 ns Output Enable High to Output High Z (1) t GHQZ tDF 20 20 20 30 35 ns Output Hold from Address, CS# or OE# Change, whichever is First tAXQX tOH 00000n s NOTES: 1. Guaranteed by design, but not tested AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE# CONTROLLED VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Write Cycle Time t AVAV tWC 60 70 90 120 150 ns Chip Select Setup Time t ELWL tCS 00000n s Write Enable Pulse Width t WLWH tWP 40 45 45 50 50 ns Address Setup Time t AVWH tAS 00000n s Data Setup Time t DVWH tDS 40 45 45 50 50 ns Data Hold Time t WHDX tDH 00000n s Address Hold Time t WHAX tAH 40 45 45 50 50 ns Write Enable Pulse Width High t WHWL tWPH 20 20 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 300 300 µs Sector Erase Time (2) t WHWH2 15 15 15 15 15 sec Read Recovery Time before Write t GHWL 00000m s VCC Set-up Time t VCS 50 50 50 50 50 µs Chip Programming Time 11 11 11 11 11 sec Output Enable Setup Time t OES 00000n s Output Enable Hold Time (4) t OEH 10 10 10 10 10 ns Chip Erase Time (3) 64 64 64 64 64 sec NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase time is 8sec. 4. For Toggle and Data# Polling.

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. AC WAVEFORMS FOR READ OPERATIONS Addresses CS# OE# WE# Outputs High Z Addresses Stable tOE tRC Output Valid tCE tACC tOH High Z tDF NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. I/O 7# is the output of the complement of the data written to the device. 4. I/O OUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED Addresses CS# OE# WE# Data 5.0 V 5555H PA PA tWC tCS PD I/O7# I/OOUT tAH tWPH tDH tDS Data# Polling tAS tRC tWP A0H tOE tDF tOH tCE tGHWL tWHWH1

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. CS# OE# WE# tOE tOE tCE tCH tOH I/O7# I/O7 = Valid Data High Z I/O0-6 = Invalid I/O0-7 Valid Data tDF I/O7 I/O0-6 tOEH tWHWH 1 or 2Data AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS Addresses CS# OE# WE# Data VCC 5555H 2AAAH 2AAAH SA 5555H 5555H tWP tCS tVCS 10H/30H55H80H55H AAHAAH tAH tAS tGHWL tWPH tDH tDS NOTES: 1. SA is the Sector Address for Sector Erase.

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. I/O 7# is the output of the complement of the data written to the device. 4. I/O OUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. Addresses WE# OE# CS# Data 5.0 V 5555H PA PA tWC tWS PD I/O7# I/OOUT tAH tCPH tCP tDH tDS Data# Polling tAS tGHEL A0H tWHWH1 ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 101: 32 LEAD, CERAMIC SOJ 1.27 (0.050) TYP 19.1 (0.750) TYP 11.3 (0.442) ± 0.30 (0.012) 3.96 (0.156) MAX 0.2 (0.008) ± 0.05 (0.002) 0.89 (0.035) Radius TYP PIN 1 IDENTIFIER PACKAGE 220: 32 LEAD, CERAMIC FLATPACK ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 10.41 (0.410) ± 0.13 (0.005) 2.60 (0.102) MAX 0.127 (0.005) + 0.05 (0.002) 0.025 (0.001) PIN 1 IDENTIFIER 1.27 (0.050) TYP 19.05 (0.750) TYP 10.16 (0.400) ± 0.51 (0.020) 0.43 (0.017) ± 0.05 (0.002) 20.83 (0.820) ± 0.25 (0.010)

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED 2.5 (0.100) TYP 1.27 (0.050) ± 0.1 (0.005) 0.46 (0.018) ± 0.05 (0.002) 0.84 (0.033) ± 0.4 (0.014) 3.2 (0.125) MIN 15.04 (0.592) ± 0.3 (0.012) 0.25 (0.010) ± 0.05 (0.002) 15.25 (0.600) ± 0.25 (0.010) PIN 1 IDENTIFIER ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 601: 32 PIN, RECTANGULAR CERAMIC LEADLESS CHIP CARRIER 7.62 (0.300) TYP 5.08 (0.200) TYP 3.81 (0.150) TYP 10.16 (0.400) TYP 0.38 (0.015) x 45° PIN 1 IDENTIFIER 0.56 (0.022) 0.71 (0.028) 11.25 (0.443) 14.15 (0.557) 13.79 (0.543) 14.15 (0.557) 1.63 (0.064) 2.54 (0.100) PIN 1 1.02 (0.040) x 45°

3 PLACES

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

ORDERING INFORMATION

WHITE ELECTRONIC DESIGNS CORP. MONOLITHIC Flash ORGANIZATION, 512K x 8 ACCESS TIME (ns) PACKAGE TYPE: C = 32 Pin Ceramic DIP (Package 300) CL = 32 Pin Rectangular Ceramic Leadless Chip Carrier (Package 601) DE = 32 Lead Ceramic SOJ (Package 101) FE = 32 Lead Flatpack (Package 220) DEVICE GRADE: M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C V PP PROGRAMMING VOLTAGE 5 = 5V LEAD FINISH: Blank = Gold plated leads A = Solder dip leads W M F 512K 8 - XXX X X 5 X

12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO. 512K x 8 Flash Monolithic 64KByte 150ns 32 pin DIP (C) 5962-96692 01HXX 512K x 8 Flash Monolithic 64KByte 120ns 32 pin DIP (C) 5962-96692 02HXX 512K x 8 Flash Monolithic 64KByte 90ns 32 pin DIP (C) 5962-96692 03HXX 512K x 8 Flash Monolithic 64KByte 70ns 32 pin DIP (C) 5962-96692 04HXX 512K x 8 Flash Monolithic 64KByte 150ns 32 lead SOJ (DE) 5962-96692 01HYX 512K x 8 Flash Monolithic 64KByte 120ns 32 lead SOJ (DE) 5962-96692 02HYX 512K x 8 Flash Monolithic 64KByte 90ns 32 lead SOJ (DE) 5962-96692 03HYX 512K x 8 Flash Monolithic 64KByte 70ns 32 lead SOJ (DE) 5962-96692 04HYX 512K x 8 Flash Monolithic 64KByte 150ns 32 lead Flatpack (FE) 5962-96692 01HUX 512K x 8 Flash Monolithic 64KByte 120ns 32 lead Flatpack (FE) 5962-96692 02HUX 512K x 8 Flash Monolithic 64KByte 90ns 32 lead Flatpack (FE) 5962-96692 03HUX 512K x 8 Flash Monolithic 64KByte 70ns 32 lead Flatpack (FE) 5962-96692 04HUX 512K x 8 Flash Monolithic 64KByte 150ns 32 lead Flatpack (FF) 5962-96692 01HTX 512K x 8 Flash Monolithic 64KByte 120ns 32 lead Flatpack (FF) 5962-96692 02HTX 512K x 8 Flash Monolithic 64KByte 90ns 32 lead Flatpack (FF) 5962-96692 03HTX 512K x 8 Flash Monolithic 64KByte 70ns 32 lead Flatpack (FF) 5962-96692 04HTX

13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF512K8-XXX5 November 2005 Rev. 6 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. Document Title 512K x 8 Flash Monolithic

Revision History

Rev # History Release Date Status Rev 1 Initial Release Changes (Pg. 1)

1.1 Change status to Final

Changes (Pg. 1)

1.1 Correct typo of Ceramic

Changes (Pg. 10)

1.1 Remove pedestal from Flatpack package drawing

Changes (Pg. 1)

1.1 Change name from ‘FP’ to Flatpack

Rev 2 Changes (Pg. 1, 2, 3, 4, 13)

2.1 Change number of max program/erases to 1,000,000

2.2 Change temperature of max program/erases to 25C

2.3 Absolute Maximum Ratings Table:

2.3.1 Change Data Retention to 20years

2.3.2 Change Endurance to 100,000 cycles minimum

2.4 Write/Erase/Program Operations Tables:

2.4.1 Change t

WHWH1 to 300µs

2.4.2 Add Note (1) Typical tWHWH1 = 7µs

2.4.3 Change t WHWH2 to 15sec

2.4.4 Add Note (2) Typical tWHWH2 = 1 sec

2.4.5 Change Chip Programming Time to 11 sec

2.4.6 Change Chip Erase Time too 64 sec

2.4.7 Add Note (3) Chip Erase Time = 8 sec

2.5 Ordering Information

2.5.1 Change Company Name to White EDC

2.6 Change Title Style to new WEDC look

Rev 3 Changes (Pg. 1, 2, 10, 12, 13) 3.1 Change package 206 to package 220

3.2 Remove temperature range notice for Endurance

3.3 Change width spec to 0.457" minimum for package 601 May 1999 Final Rev 4 Changes (Pg. 1, 3, 4)

4.1 Add 60ns speed grade option

Rev 5 Changes (Pg. 1, 11, 13)

5.1 Add 'T' case outline for 'FF' package

Rev 6 Changes (Pg. 1, 13) 6.1 Change revision history Rev 2.4.1 to 300 µs 6.2 Change revision history Rev 2.4.2 to 7µs November 2005 Final