WMF2M8-120DAC5

WMF2M8-XXX5 WEDC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Fig. 1 – Pin Confi guration for WMF2M8-XXX5 2Mx8 MONOLITHIC FLASH, SMD 5962-97609 /square6 Low Power CMOS /square6 Data# Polling and Toggle Bit feature for de tec tion of program or erase cycle completion. /square6 Supports reading or programming data to a sector not being erased. /square6 RESET# pin resets internal state machine to the read mode. /square6 Multiple Ground Pins for Low Noise Operation * This data sheet describes a product that is subject to change without notice. ** Package to be developed. Note: For programming information refer to Flash Pro gram ming 16M5 Ap pli ca tion Note.

FEATURES

/square6 Access Times of 90, 120, 150ns /square6 Packaging:

• 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP foot print.
• 44 pin Ceramic LCC** /square6 Sector Architecture
• 32 equal size sectors of 64KBytes each
• Any combination of sectors can be erased. Also supports full chip erase. /square6 100,000 Write/Erase Cycles Minimum /square6 Organized as 2Mx8 /square6 Commercial, Industrial, and Military Tem per a ture Ranges /square6 5V Read and Write. 5V ± 10% Sup ply.

56 CSOP

I/O0-7 Data Inputs/Out puts A0-20 Address Inputs WE# Write Enable CS# Chip Select OE# Output Enable VCC Power Supply GND Ground RY/BY# Ready/Busy RESET# Reset CS# A12 A13 A14 A15 NC NC NC A20 A19 A18 A17 A16 V CC GND I/O6 NC I/O7 NC RY/BY# OE# WE# NC NC I/O5 NC I/O4 V CC NC RESET# A11 A10 GND V CC NC I/O1 NC I/O0 NC NC NC I/O2 NC I/O3 NC GND ** Package to be developed.

44 CLCC**

18 19 20 21 22 23 24 25 26 27 28 A NC NC NC A I/O0 I/O1 I/O2 I/O3 GND GND VCC I/O4 I/O5 I/O6 I/O7 A16 A17 A18 A19 NC NC NC A WE# OE# RY/BY# A10 A11 RESET# VCC CS# A A13 A14 A15

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Ground V SS 00 0 V Input High Voltage V IH 2.0 - V CC + 0.5 V Input Low Voltage V IL -0.5 - +0.8 V Operating Temperature (Mil.) T A -55 - +125 °C Operating Temperature (Ind.) T A -40 - +85 °C DC CHARACTERISTICS — CMOS COMPATIBLE VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at V IH. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions V IL = 0.3V, VIH = VCC - 0.3V CAPACITANCE TA = +25°C Parameter Symbol Con di tions Max Unit Address Input capacitance CAD V I/O = 0 V, f = 1.0MHz 12 pF Output Enable capacitance COE V IN = 0 V, f = 1.0MHz 12 pF Write Enable capacitance CWE V IN = 0 V, f = 1.0MHz 12 pF Chip Select capacitance CCS V IN = 0 V, f = 1.0MHz 12 pF Data I/O capacitance CI/O V I/O = 0 V, f = 1.0MHz 12 pF Parameter Symbol Conditions Min Max Unit Input Leakage Current I LI VCC = 5.5, VIN = GND to VCC 10 µA Output Leakage Current I LO VCC = 5.5, VIN = GND to VCC 10 µA VCC Active Current for Read (1) I CC1 CS# = VIL, OE# = VIH, f = 5MHz 40 mA VCC Active Current for Program or Erase (2) I CC2 CS# = VIL, OE# = VIH 60 mA VCC Standby Current I CC3 VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = Vcc ± 0.3V 2.0 mA Output Low Voltage V OL IOL = 12.0 mA, VCC = 4.5 0.45 V Output High Voltage V OH IOH = -2.5 mA, VCC = 4.5 0.85xV CC V Low VCC Lock-Out Voltage V LKO 3.2 4.2 V Parameter Symbol Ratings Unit Voltage on Any Pin Relative to VSS V T -2.0 to +7.0 V Power Dissipation P T 8W Storage Temperature T STG -65 to +125 °C Short Circuit Output Current I OS 100 mA Endurance - Write/Erase Cycles (Mil Temp) 100,000 min cycles Data Retention (Mil Temp) 20 years This parameter is guaranteed by design but not tested.

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -90 -120 -150 Unit Min Max Min Max Min Max Write Cycle Time t AVAV tWC 90 120 150 ns Chip Select Setup Time t ELWL tCS 000 n s Write Enable Pulse Width t WLWH tWP 45 50 50 ns Address Setup Time t AVWL tAS 000 n s Data Setup Time t DVWH tDS 45 50 50 ns Data Hold Time t WHDX tDH 000 n s Address Hold Time t WLAX tAH 45 50 50 ns Write Enable Pulse Width High t WHWL tWPH 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase (2) t WHWH2 15 15 15 sec Read Recovery Time before Write t GHWL 000 µ s VCC Setup Time t VCS 50 50 50 µs Chip Programming Time 44 44 44 sec Chip Erase Time (3) 256 256 256 sec Output Enable Hold Time (4) t OEH 10 10 10 ns RESET# Pulse Width t RP 500 500 500 ns NOTES: 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. AC CHARACTERISTICS – READ-ONLY OPERATIONS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -90 -120 -150 Unit Min Max Min Max Min Max Read Cycle Time t AVAV tRC 90 120 150 ns Address Access Time t AVQV tACC 90 120 150 ns Chip Select Access Time t ELQV tCE 90 120 150 ns Output Enable to Output Valid t GLQV tOE 40 50 55 ns Output Enable Hold Time Read Toggle & tOEH 000 n s 10 10 10 nsData Polling Chip Select High to Output High Z (1) t EHQZ tDF 20 30 35 ns Output Enable High to Output High Z (1) t GHQZ tDF 20 30 35 ns Output Hold from Addresses, CS# or OE# Change, whichever is First tAXQX tOH 000 n s RESET# Low to Read Mode (1) t Ready 20 20 20 µs 1. Guaranteed by design, not tested.

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Current Source Current Source D.U.T. Ceff = 50 pf IOL IOL VZ = 1.5V (Bipolar Supply) AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED VCC = 5.0V, VSS = 0V, VSS = 0V, -55°C ≤ TA ≤ +125°C AC Test Conditions FIGURE 2 – AC TEST CIRCUIT Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load cir cuit. ATE tester includes jig capacitance. Parameter Typ Unit Input Pulse Levels V IL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V Parameter Symbol -90 -120 -150 Unit Min Max Min Max Min Max Write Cycle Time t AVAV tWC 90 120 150 ns Write Enable Setup Time t WLEL tWS 000 n s Chip Select Pulse Width t ELEH tCP 45 50 50 ns Address Setup Time t AVEL tAS 000 n s Data Setup Time t DVEH tDS 45 50 50 ns Data Hold Time t EHDX tDH 000 n s Address Hold Time t ELAX tAH 45 50 50 ns Chip Select Pulse Width High t EHEL tCPH 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase Time (2) t WHWH2 15 15 15 sec Read Recovery Time t GHEL 000 µ s Chip Programming Time 44 44 44 sec Chip Erase Time (3) 256 256 256 sec Output Enable Hold Time (4) t OEH 10 10 10 ns NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. HARDWARE RESET (RESET#) Parameter Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET Pulse Width Min 500 ns tRH RESET High Time Before Read (See Note) Min 50 ns tRB RY/BY Recovery Time Min 0 ns

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 tRH tRP tRP tRB tReady tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms RY/BY# CS#, OE# RESET# RY/BY# CS#, OE# RESET# FIGURE 3 – RESET# TIMING

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Addresses CS# OE# WE# Outputs RESET# RY/BY# HIGH Z Addresses Stable Output Valid HIGH Z 0 V tRC tACC tDFtOE tOEH tCE tOH FIGURE 4 – AC WAVEFORMS FOR READ OPERATIONS

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 555h PA PA PA A0h PD Status DOUT Addresses CS# OE# WE# Data RY/BY# VCC tBUSY tRB tAH tCH tWHWH1 tVCS tDS tDH tWPH tWP tAStWC tCS Program Command Sequence (last two cycles) Read Status Data (last two cycles) FIGURE 5 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of a four bus cycle sequence.

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Addresses CS# OE# WE# Data RY/BY# VCC tC tWC tAS 2AAh SA VA VA 555h for chip erase tAH tWHWH2 tRBtBUSY 10 for CHip Erase tVCS tDH tCS tDS tWPH tWP tCH 30h55h In Progress Complete FIGURE 6 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS Notes: SA is the sector address for Sector Erase.

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Addresses CS# OE# WE# DQ7 DQ0-DQ6 RY/BY# tRC tACC tCE tCH tOE tOEH tDF tOH tBUSY Complement Status Data Complement True Status Data True Valid Data Valid Data High Z High Z VA VA VA FIG. 7 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALIGORITHM OPERATIONS Notes: VA = Valid Address. Illustration shows fi rst status cycle after command sequence, last status read cycle and array data read cycle.

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Addresses WE# OE# CS# Data RESET# RY/BY# XXX for program XXX for erase PA for program SA for sector erase XXX for chip erase tWC tAS tAH Data Polling PA tWH tGHEL tCP tWS tCPH tDS tDH tWHWH1 or 2 tBUSY DQ7 DOUT AO for program 55 for erase PD for program 30 for sector erase 10 for chip erase tRH FIGURE 8 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of a four bus cycle sequence.

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 Addresses CS# OE# WE# DQ6-DQ2 RY/BY# tRC VA VA VA VA tACC tCE tCH tOE tOEH tDF High Z tOH tBUSY Valid Status (first read) Valid Status Valid Status (second read) (stops toggling) Valid Data FIGURE 9 – TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS) Notes: VA = Valid address; not required for DQ6. Illustration shows fi rst two status cycle after command sequence, last status read cycle and array data read cycle.

13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 12.96 (0.510) ± 0.15 (0.006) 0.18 (0.007) 16.13 (0.635) ± 0.13 (0.005) 0.25 (0.010) ± 0.05 (0.002) 0.80 (0.031) TYP 4.06 (0.160) MAX PIN 1 IDENTIFIER 0 / -4 0.51 (0.020) TYP DETAIL "A" SEE DETAIL "A" 1.02 (0.040) ± 0.18 (0.007) 1.60 (0.063) TYP 2.87 (0.113) MAX R = 0.18 (0.007) TYP PACKAGE 207: 56 LEAD, CERAMIC SOP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 12.70 (0.500) TYP 1.27 (0.050) TYP 12.70 (0.500) TYP PIN 1 IDENTIFIER 0.53 (0.021) 0.74 (0.029) 16.26 (0.640) 16.67 (0.660) 16.26 (0.640) 16.67 (0.660) 3.05 (0.120) MAX PIN 1 1.14 (0.045) 1.40 (0.055) PACKAGE DIMENSION: 44 LEAD, CERAMIC LCC ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Package to be developed.

14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WMF2M8-XXX5 May 2004 Rev. 6 W M F 2M 8 - XXX X X 5 X Device Type Sector Size Speed Package SMD No. 2M x 8 Flash Monolithic 64KByte 150ns 56 lead CSOP (DA) 5962-97609 01HXX 2M x 8 Flash Monolithic 64KByte 120ns 56 lead CSOP (DA) 5962-97609 02HXX 2M x 8 Flash Monolithic 64KByte 90ns 56 lead CSOP (DA) 5962-97609 03HXX

ORDERING INFORMATION

LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: M = Military, 883 Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: DA = 56 Lead CSOP (Package 207) fi ts standard 56 SSOP footprint L = 44 Lead Ceramic LCC* ACCESS TIME (ns) ORGANIZATION, 2M x 8 Flash MONOLITHIC WHITE ELECTRONIC DESIGNS CORP. * Package to be developed.