WME128K8-200CC

WME128K8-XXX WEDC | Alldatasheet

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Technical content

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. January 2004 Rev. 5

FEATURES

/square6 Read Access Times of 120, 140, 150, 200, 250, 300ns /square6 JEDEC Approved Packages

• 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ (Package 101) /square6 Commercial, Industrial and Military Temperature Ranges /square6 MIL-STD-883 Compliant Devices Available /square6 Write Endurance 10,000 Cycles /square6 Data Retention at 25°C, 10 Years /square6 Low Power CMOS Operation FIGURE 1 – Pin Confi guration

32 DIP

32 CSOJ

V SS VCC WE# NC A14 A13 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796 Pin Description A0-16 Address Inputs I/O0-7 Data Input/Output CS# Chip Selects OE# Output Enable WE# Write Enable V CC +5.0v Power VSS Ground /square6 Automatic Page Write Operation

• Internal Address and Data Latches for 128 Bytes
• Internal Control Timer /square6 Page Write Cycle Time 10ms Max. /square6 Data Polling for End of Write Detection /square6 Hardware and Software Data Protection /square6 TTL Compatible Inputs and Outputs This product is subject to change without notice.

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. FIGURE 2 – AC Test Circuit DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Conditions Min Max Unit Input Leakage Current I LI VCC = 5.5, VIN = GND to VCC 10 µA Output Leakage Current I LO CS# = VIH, OE# = VIH, VOUT = GND to VCC 10 µA Operating Supply Current I CC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 80 mA Standby Current I SB CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 0.625 mA Output Low Voltage V OL IOL = 2.1mA, VCC = 4.5V 0.45 V Output High Voltage V OH IOH = -400µA, VCC = 4.5V 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V TRUTH TABLE CS# OE# WE# Mode Data I/O H X X Standby High Z L L H Read Data Out L H L Write Data In X H X Out Disable High Z/Data Out X X H Write X L X Inhibit CAPACITANCE TA = +25°C Parameter Symbol Conditions Max Unit Input Capacitance C IN VIN = 0 V, f = 1MHz 20 pF Output Capacitance C OUT VI/O = 0 V, f = 1MHz 20 pF This parameter is guaranteed by design but not tested. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Operating Temperature T A -55 to +125 °C Storage Temperature T STG -65 to +150 °C Signal Voltage Relative to GND V G -0.6 to + 6.25 V Voltage on OE# and A9 -0.6 to +13.5 V NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.0 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) T A -55 +125 °C Operating Temp. (Ind.) T A -40 +85 °C AC TEST CONDITIONS Parameter Typ Unit Input Pulse Levels V IL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. Current Source IOH IOL Current Source Vz ~ 1.5V Bipolar Supply ~D.U.T Ceff = 50 pf

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. WRITE CYCLE TIMING Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE# line low. The write cycle begins when the last of either CS# or WE# goes low. The WE# line transition from high to low also initiates an internal 150µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. WRITE Write operations are initiated when both CS# and WE# are low and OE# is high. The EEPROM devices support both a CS# and WE# controlled write cycle. The address is latched by the falling edge of either CS# or WE#, whichever occurs last. The data is latched internally by the rising edge of either CS# or WE#, whichever occurs fi rst. A byte write operation will automatically continue to completion. AC WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol 128Kx8 Unit Min Max Write Cycle Time, TYP = 6ms t WC 10 ms Address Set-up Time t AS 10 ns Write Pulse Width (WE# or CS#) t WP 100 ns Chip Select Set-up Time t CS 0n s Address Hold Time t AH 100 ns Data Hold Time t DH 10 ns Chip Select Hold Time t CH 0n s Data Set-up Time t DS 50 ns Output Enable Set-up Time t OES 0n s Output Enable Hold Time t OEH 0n s Write Pulse Width High t WPH 50 ns

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DATA POLLING The WME128K8-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on I/O7. Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. FIGURE 6 – DATA POLLING WAVEFORMS DATA POLLING CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Min Max Unit Data Hold Time tdh 10 ns OE# Hold Time toeh 10 ns OE# To Output Valid toe 55 ns Write Recovery Time twr 0 ns WE# tOEH tDH tOE tWR HIGH Z CS# OE# I/O7 ADDRESS TOGGLE BUT CHARACTERISTICS(1) Symbol Parameter Min Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns TOGGLE BIT: In addition to DATA# Polling another method for determining the end of a write cycle is provided . During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. NOTE: 1. Toggling either OE# or CS# or both OE# and CS# will operate toggle bit. 2. Beginning and ending state of I/O6 will vary 3. Any address location may be used but the address should not vary. tWR HIGH ZtDH tOE tOEH WE# CS# OE# I/O6 (2)

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. PAGE WRITE OPERATION The WME128K8-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the fi rst data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. The usual procedure is to increment the least signifi cant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. FIGURE 7 – PAGE MODE WRITE WAVEFORMS PAGE WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Page Mode Write Characteristics Symbol Unit Parameter Min Max Write Cycle Time, TYP = 6ms t wc 10 ms Address Set-up Time t as 10 ns Address Hold Time (1) t ah 100 ns Data Set-up Time t ds 50 ns Data Hold Time t dh 10 ns Write Pulse Width t wp 100 ns Byte Load Cycle Time t blc 150 µs Write Pulse Width High t wph 50 ns 1. Page address must remain valid for duration of write cycle. OE# BYTE 0 BYTE 1 BYTE 2 BYTE 3VALID DATA VALID ADDRESS tWC tBLCtWPHtWP ADDRESS DATA CS# WE# BYTE 127 tDS tDH tAS tAH

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. FIGURE 8 – SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1) NOTES: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A 16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data to be loaded. WRITES ENABLED (2) ENTER DATA PROTECT STATE LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS NOTES: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1) EXIT DATA PROTECT STATE(3) SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WME128K8-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software Data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No Data will be written to the device; however, for the duration of t WC. The write protection feature can be disabled by a six byte write sequence of specifi c data to specifi c locations. Power transitions will not reset the software write protection. The software write protection guards against inadvertent writes during power transitions or unauthorized modifi cation using a PROM programmer. HARDWARE DATA PROTECTION These features protect against inadvertent writes to the WME128K8-XXX. These are included to improve reliability during normal operation: a) V CC power on delay As V CC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) V CC sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise fi lter Pulses of <15ns (typ) on WE# or CS# will not initiate a write cycle.

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 101: 32 LEAD, CERAMIC SOJ 1.27 (0.050) TYP PIN 1 IDENTIFIER 19.1 (0.750) TYP 11.3 (0.446) ± 0.2 (0.009) 3.96 (0.156) MAX 0.2 (0.008) ± 0.05 (0.002) 0.89 (0.035) Radius TYP PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED PIN 1 IDENTIFIER 0.84 (0.033) ± 0.4 (0.014) 15.04 (0.592) ± 0.3 (0.012) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

ORDERING INFORMATION

DEVICE TYPE SPEED PACKAGE SMD NO. 128K x 8 EEPROM Monolithic 300ns 32 pin DIP (C) 5962-96796 01HYX 128K x 8 EEPROM Monolithic 250ns 32 pin DIP (C) 5962-96796 02HYX 128K x 8 EEPROM Monolithic 200ns 32 pin DIP (C) 5962-96796 03HYX 128K x 8 EEPROM Monolithic 150ns 32 pin DIP (C) 5962-96796 04HYX 128K x 8 EEPROM Monolithic 140ns 32 pin DIP (C) 5962-96796 05HYX 128K x 8 EEPROM Monolithic 120ns 32 pin DIP (C) 5962-96796 06HYX 128K x 8 EEPROM Monolithic 300ns 32 lead SOJ (DE) 5962-96796 01HXX 128K x 8 EEPROM Monolithic 250ns 32 lead SOJ (DE) 5962-96796 02HXX 128K x 8 EEPROM Monolithic 200ns 32 lead SOJ (DE) 5962-96796 03HXX 128K x 8 EEPROM Monolithic 150ns 32 lead SOJ (DE) 5962-96796 04HXX 128K x 8 EEPROM Monolithic 140ns 32 lead SOJ (DE) 5962-96796 05HXX 128K x 8 EEPROM Monolithic 120ns 32 lead SOJ (DE) 5962-96796 06HXX LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: C = 32 Pin Ceramic DIP (Package 300) DE = 32 Lead CSOJ (Package 101) ACCESS TIME (ns) ORGANIZATION 128K x 8 EEPROM MONOLITHIC WHITE ELECTRONIC DESIGNS CORP. W M E 128K8 - XXX X X X