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WLA49VVA

National Semiconductor ...

Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

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Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

1.0 General Description

The LM4935 is an integrated audio subsystem that supports both analog and digital audio functions. The LM4935 in- cludes a high quality stereo DAC, a mono ADC, a multi- purpose SAR ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE)modes of operation, a mono earpiece amplifier and a mono high effi- ciency loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM4935 features a bi-directional I 2S serial interface for full range audio and an I 2C or SPI compatible interface for control. The stereo DAC path features an SNR of 88 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33 mW RMS t oa3 2 Ω single-ended stereo load with less than 1% distortion (THD+N) when A_V DD = 3.3V. The mono earpiece amplifier delivers at least 115 mW RMS t oa3 2Ω bridged-tied load with less than 1% distor- tion (THD+N) when A_V DD = 3.3V. The mono speaker am- plifier delivers up to 600 mW into an 8 Ω load with less than 1% distortion when LS_V DD = 3.3V and up to 1.3W when LS_VDD = 5.0V. The LM4935 also contains a general pur- pose SAR ADC for housekeeping duties such as battery and temperature monitoring. This can also be used for analog volume control of the output stages and can trigger interrupt events. The LM4935 employs advanced techniques to reduce power consumption, to reduce controller overhead to speed devel- opment time and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external com- ponents. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power con- sumption, PCB area and cost are primary requirements.

2.0 Applications

n Mobile Phones and Multimedia Terminals n PDAs, Internet Appliances and Portable Gaming n Portable DVD/CD/AAC/MP3 Players n Digital Cameras/Camcorders

3.0 Key Specifications

n PHP (AC-COUP) @ A_VDD = 3.3V, 32Ω, 1% THD 33 mW n PHP (OCL) @ A_VDD = 3.3V, 32Ω, 1% THD 31 mW n PLS @ LS_VDD =5 V ,8Ω, 1% THD 1.3 W n PLS @ LS_VDD = 4.2V, 8Ω, 1% THD 900 mW n PLS @ LS_VDD = 3.3V, 8Ω, 1% THD 600 mW j Supply Voltage Range BB_VDD = 1.8V to 4.5V, D_VDD & PLL_VDD = 2.7V to 4.5V LS_VDD & A_VDD = 2.7V to 5.5V n Shutdown Current 1.1 µA n PSRR @ 217 Hz, A_VDD = 3.3V, (Headphone) 60 dB n SNR (Stereo DAC to AUXOUT) 88 dB (typ) n SNR (Mono ADC from Cell Phone In) 90 dB (typ) n SNR (Aux In to Headphones) 98 dB (typ)

4.0 Features

n 12-bit 4 input multipurpose SAR ADC n 8 kHz to 48 kHz stereo audio playback n 8 kHz to 48 kHz mono recording n 1 Hz to 13.888 kHz sample rate on all 4 SAR channels n Bidirectional PCM/I2S compatible audio interface n Sigma-Delta PLL for operation from any clock at any sample rate n Low power clock network operation if 12 MHz system clock is available n Read/write I2C or SPI compatible control interface n 33mW stereo headphone amplifier at 3.3V n OCL or AC-coupled headphone operation n Automatic headphone & microphone detection n Support for internal and external microphones n Automatic gain control for microphone input n High efficiency BTL 8Ω amplifier, 600 mW @ 3.3V n 115 mW earpiece amplifier at 3.3V n Differential audio I/O for external cellphone module n Mono differential auxiliary output n Stereo auxiliary inputs n Differential microphone input for internal microphone n Flexible audio routing from input to output n 32 Step volume control for mixers with 1.5 dB steps n 16 Step volume control for microphone in 2 dB steps n Programmable sidetone attenuation in 3 dB steps n DC Volume Control n Two configurable GPIO ports n Programmable voltage triggers on SAR channels n Multi-function IRQ output n Micro-power shutdown mode n Available in the4x4m m4 9 bump microfil package Boomer® is a registered trademark of National Semiconductor Corporation. October 2005 LM4935 Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC © 2005 National Semiconductor Corporation DS201341 www.national.com

5.0 LM4935 Overview

FIGURE 1. Conceptual Schematic

6.0 Typical Application

FIGURE 2. Example Application in Multimedia Mobile Phone

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Table of Contents(Continued) LM4935 www.national.com5

7.0 Connection Diagrams

49 Bump Microfil 49 Bump Microfil Marking

Top View (Bump Side Down) Order Number LM4935 See NS Package Number WLA49VVA 201341P5 Top View XY — Date Code TT — Die Traceability G — Boomer F4 — LM4935WL/WLX Pin Descriptions Pin Pin Name Type Direction Description A1 EP_NEG Analog Output Earpiece negative output A2 A_V DD Supply Input Headphone and mixer V DD A3 INT_MIC_POS Analog Input Internal microphone positive input A4 EXT_MIC Analog Input External microphone input A5 VSAR2 Analog Input Input to SAR channel 2 A6 VSAR1 Analog Input Input to SAR channel 1 A7 PLL_V SS Supply Input PLL V SS B1 A_V SS Supply Input Headphone and mixer V SS B2 EP_POS Analog Output Earpiece positive output B3 INT_MIC_NEG Analog Input Internal microphone negative input B4 BYPASS Analog Inout A_V DD/2 filter point B5 TEST_MODE/CS Digital Input If SPI_MODE = 1, then this pin becomes CS. If SPI_MODE = 0, and TEST_MODE/CS = 1, then this places the LM4935 into test mode. B6 PLL_FILT Analog Inout Filter point for PLL VCO input B7 PLL_V DD Supply Input PLL V DD C1 HP_R Analog Output Headphone Right Output C2 EXT_BIAS Analog Output External microphone supply (2.0/2.5/2.8/3.3V) C3 INT_BIAS Analog Output 2.0V/2.5V ultra-clean supply for internal microphone C4 AUX_R Analog Input Right Analog Input C5 GPIO_2 Digital Inout General Purpose I/O 2 C6 SDA Digital Inout Control Data, I2C_SDA or SPI_SDI C7 SCL Digital Input Control Clock, I2C_SCL or SPI_SCK D1 HP_L Analog Output Headphone Left Output D2 VREF_FLT Analog Inout Filter point for the microphone power supply D3 AUX_L Analog Input Left Analog Input D4 SPI_MODE Digital Input Control mode selec t 1 = SPI, 0 = I2C (or test) D5 GPIO_1 Digital Inout General Purpose I/O 1 D6 BB_V DD Supply Input Baseband V DD for the digital I/Os D7 D_V DD Supply Input Digital V DD E1 HP_VMID Analog Inout Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input LM4935 www.national.com 6

7.0 Connection Diagrams (Continued)

Pin Descriptions (Continued) Pin Pin Name Type Direction Description E2 HP_VMID_FB Analog Inout VMID Feedback in OCL mode, otherwise a 2nd headset detection input E3 MIC_DET Analog Input Headset insertion/removal and Microphone presence detection input E4 CPI_NEG Analog Input Cell Phone analog input negative E5 IRQ Digital Output Interrupt request signal (NOT open drain) E6 I2S_SDO Digital Output I2S Serial Data Out E7 I2S_SDI Digital Input I2S Serial Data Input F1 LS_V DD Supply Input Loudspeaker V DD F2 LS_V DD Supply Input Loudspeaker V DD F3 CPI_POS Analog Input Cell Phone analog input positive F4 CPO_NEG Analog Output Cell Phone analog output negative F5 AUX_OUT_NEG Analog Output Auxiliary analog output negative F6 I2S_WS Digital Inout I2S Word Select Signal (can be master or slave) F7 I2S_CLK Digital Inout I2S Clock Signal (can be master or slave) G1 LS_POS Analog Output Loudspeaker positive output G2 LS_V SS Supply Input Loudspeaker V SS G3 LS_NEG Analog Output Loudspeaker negative output G4 CPO_POS Analog Output Cell Phone analog output positive G5 AUX_OUT_POS Analog Output Auxiliary analog output positive G6 D_V SS Supply Input Digital V SS G7 MCLK Digital Input Input clock from 0.5 MHz to 30 MHz

7.1 PIN TYPE DEFINITIONS

Analog Input — A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Analog Output — A pin that is driven by the device and should not be driven by external sources. Analog Inout — A pin that is typically used for filtering a DC signal within the device, Passive com- ponents can be connected to these pins. Digital Input — A pin that is used by the digital but is never driven. Digital Output — A pin that is driven by the device and should not be driven by another device to avoid contention. Digital Inout — A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the direction is selected by a control register within the LM4935. LM4935 www.national.com7

8.0 Absolute Maximum Ratings

(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_V DD & LS_VDD) 6.0V Digital Supply Voltage (BB_VDD & D_VDD & PLL_VDD) 6.0V Storage Temperature −65˚C to +150˚C Power Dissipation (Note 3) Internally Limited ESD Susceptibility Human Body Model (Note 4) Machine Model (Note 5) 2500V 200V Junction Temperature 150˚C Thermal Resistance θ JA – WLA49 (soldered down to PCB with 2in 2 1oz. copper plane) 60˚C/W Soldering Information See AN-1279 for Microfil TM package information. Peak reflow temperature should not exceed 235˚C.

9.0 Operating Ratings

Temperature Range −40˚C to +85˚C Supply Voltage D_VDD/PLL_VDD BB_VDD LS_VDD/A_VDD 2.7V to 4.5V 1.8V to 4.5V 2.7V to 5.5V 10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. Symbol Parameter Conditions LM4935 UnitsTypical (Note 6) Limit (Note 7) DC CURRENT CONSUMPTION DISD Digital Shutdown Current Chip Mode ’00’, fMCLK = 13MHz 0.7 µA Chip Mode ’00’, fMCLK = 19.2MHz 0.7 5 µA (max) DIST Digital Standby Current Chip Mode ’01’, fMCLK = 13MHz 1.5 mA Chip Mode ’01’, fMCLK = 19.2MHz 2.2 3 mA (max) DIDD Digital Active Current Chip Mode ’10’, fMCLK = 13MHz, DAC, ADC, SAR OFF 1.5 mA Chip Mode ’10’, fMCLK = 19.2MHz, DAC, ADC, SAR OFF 2.2 mA Chip Mode ’10’, fMCLK = 13MHz DAC, ADC, SAR ON 11.2 mA Chip Mode ’10’, fMCLK = 19.2MHz, DAC, ADC, SAR ON 16.2 20 mA (max) AISD Analog Shutdown Current Chip Mode ’00’ 0.2 3 µA (max) AIST Analog Standby Current Chip Mode ’01’, No headset inserted 0.2 3 µA (max) AIDD Analog Active Current All Outputs OFF, SE MODE 6.1 mA All Outputs OFF, OCL MODE 5.7 mA All Outputs ON, SE MODE 18.3 mA All Outputs ON, OCL MODE 18.7 28 mA (max) PLLI DD PLL Active Current fMCLK =1 3M H z fPLLOUT = 12 MHz, PLL ON only 4.2 mA fMCLK = 19.2 MHz fPLLOUT = 12 MHz, PLL ON only 6.2 mA ADCIDD ADC Active Current fMCLK = 13MHz, ADC ON only 2.5 mA fMCLK = 19.2MHz, ADC ON only 3.6 mA LM4935 www.national.com 8

10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. (Continued) Symbol Parameter Conditions LM4935 UnitsTypical (Note 6) Limit (Note 7) DC CURRENT CONSUMPTION DACIDD DAC Active Current fMCLK = 13MHz, DAC ON only; PLL OFF, fS = 48kHz 7.4 mA fMCLK = 19.2MHz, DAC ON only PLL OFF; fS = 48kHz 10.7 mA SARIDD SAR Active Current fMCLK = 13MHz, SAR ON only 1.6 mA fMCLK = 19.2MHz, SAR ON only 2.3 mA LSIDD Loudspeaker Quiescent Current LS ON only 8.8 mA HPIDD Headphone Quiescent Current HP ON only, SE MODE 3.5 mA HP ON only, OCL MODE 3.9 mA EPIDD Earpiece Quiescent Current EP ON only 4.4 mA AUXIDD AUXOUT Quiescent Current AUXOUT ON only 4.8 mA CPOUTIDD CPOUT Quiescent Current CPOUT ON only 4.8 mA LOUDSPEAKER AMPLIFIER P LS Max Loudspeaker Power 8 Ω load, LS_VDD = 5V 1.3 W 8Ω load, LS_VDD = 4.2V 0.9 W 8Ω load, LS_VDD = 3.3V 0.6 0.44 W (min) LSTHD+N Loudspeaker Harmonic Distortion 8 Ω load, LS_VDD = 3.3V, PO = 400mW 0.4 % LSEFF Efficiency 0 dB Input MCLK = 12.000 MHz 84 % PSRRLS Power Supply Rejection Ration (Loudspeaker) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz 54 dB SNRLS Signal to Noise Ratio From 0 dB Analog AUX input at 1 kHz, A-weighted 76 dB eN Output Noise A-weighted 350 µV VOS Offset Voltage 7 mV HEADPHONE AMPLIFIER P HP Headphone Power 32 Ω load, 3.3V, SE 33 20 mW (min) 16Ω load, 3.3V, SE 52 mW 32Ω load, 3.3V, OCL, VCM = 1.5V 31 mW 32Ω load, 3.3V, OCL, VCM = 1.2V 20 mW 16Ω load, 3.3V, OCL, VCM = 1.5V 50 mW 16Ω load, 3.3V, OCL, VCM = 1.2V 32 mW PSRRHP Power Supply Rejection Ratio (Headphones) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz SE Mode 60 dB OCL Mode VCM = 1.2V 68 dB OCL Mode VCM = 1.5V 65 dB LM4935 www.national.com9

10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. (Continued) Symbol Parameter Conditions LM4935 UnitsTypical (Note 6) Limit (Note 7) HEADPHONE AMPLIFIER SNRHP Signal to Noise Ratio From 0dB Analog AUX input A-weighted SE Mode 98 dB OCL Mode VCM = 1.2V 97 dB OCL Mode VCM = 1.5V 96 dB HP THD+N Headphone Harmonic Distortion 32 Ω load, 3.3V, PO = 7.5mW 0.05 % eN Output Noise A-weighted 12 µV ∆ACH-CH Stereo Channel-to-Channel Gain Mismatch 0.3 dB XTALK Stereo Crosstalk SE Mode 61 dB OCL Mode 63 dB EARPIECE AMPLIFIER P EP Earpiece Power 32 Ω load, 3.3V 115 100 mW (min) 16Ω load, 3.3V 150 mW PSRREP Power Supply Rejection Ratio (Earpiece) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P FRIPPLE = 217 Hz 65 dB SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted 98 dB EPTHD+N Earpiece Harmonic Distortion 32 Ω load, 3.3V, PO = 50mW 0.04 % eN Output Noise A-weighted 24 µV VOS Offset Voltage 15 mV AUXOUT AMPLIFIER THD+N Total Harmonic Distortion + Noise V O =1 VRMS,5 kΩ load 0.02 % PSRR Power Supply Rejection Ratio AUX inputs terminated CBYPASS = 1.0µF VRIPPLE = 200mVPP fRIPPLE = 217Hz 70 dB CP_OUT AMPLIFIER THD+N Total Harmonic Distortion + Noise V O =1 VRMS,5 kΩ load 0.02 % PSRR Power SUpply Rejection Ratio C BYPASS = 1.0µF VRIPPLE = 200mVPP fRIPPLE = 217Hz 68 dB MONO ADC RADC ADC Ripple ±0.25 dB PBADC ADC Passband Lower (HPF Mode 1), f S = 8 kHz 300 Hz Upper 3470 Hz SBAADC ADC Stopband Attenuation Above Passband 60 dB HPF Notch, 50 Hz/60 Hz (worst case) 58 dB SNRADC ADC Signal to Noise Ratio From CPI, A-weighted 90 dB ADCLEVEL ADC Full Scale Input Level 1 V RMS LM4935 www.national.com 10

10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. (Continued) Symbol Parameter Conditions LM4935 UnitsTypical (Note 6) Limit (Note 7) STEREO DAC R DAC DAC Ripple 0.1 dB PBDAC DAC Passband 20 kHz SBADAC DAC Stopband Attenuation 70 dB SNRDAC DAC Signal to Noise Ratio A-weighted, AUXOUT 88 dB DRDAC DAC Dynamic Range 96 dB DACLEVEL DAC Full Scale Output Level 1 V RMS PLL F IN Input Frequency Range Min 0.5 MHz Max 30 MHz I2S/PCM fI2SCLK I2S CLK Frequency fS = 48kHz; 16 bit mode 1.536 MHz fS = 48kHz; 25 bit mode 2.4 MHz fS = 8kHz; 16 bit mode 0.256 MHz fS = 8kHz; 25 bit mode 0.4 MHz fPCMCLK PCM CLK Frequency fS = 48kHz; 16 bit mode 0.768 MHz fS = 48kHz; 25 bit mode 1.2 MHz fS = 8kHz; 16 bit mode 0.128 MHz fS = 8kHz; 25 bit mode 0.2 MHz DCI2S_CLK I2S_CLK Duty Cycle Min 40 % (min) Max 60 % (max) DCI2S_WS I2S_WS Duty Cycle 50 % I2C T I2CSET I2C Data Setup Time Refer to Pg. 18 for more details 100 ns (min) TI2CHOLD I2C Data Hold Time Refer to Pg. 18 for more details 300 ns (min) SPI T SPISETENB Enable Setup Time 100 ns (min) TSPIHOLD-ENB Enable Hold Time 100 ns (min) TSPISETD Data Setup Time 100 ns (min) TSPIHOLDD Data Hold Time 100 ns (min) TSPICL Clock Low Time 500 ns (min) TSPICH Clock High Time 500 ns (min) VOLUME CONTROL VCRAUX AUX Volume Control Range Minimum Gain w/ AUX_BOOST OFF –46.5 dB Maximum Gain w/ AUX_BOOST OFF 0d B Minimum Gain w/ AUX_BOOST ON –34.5 dB Maximum Gain w/ AUX_BOOST ON 12 dB VCRDAC DAC Volume Control Range Minimum Gain w/ DAC_BOOST OFF –46.5 dB Maximum Gain w/ DAC_BOOST OFF 0d B Minimum Gain w/ DAC_BOOST ON –34.5 dB Maximum Gain w/ DAC_BOOST ON 12 dB VCRCPIN CPIN Volume Control Range Minimum Gain –34.5 dB Maximum Gain 12 dB LM4935 www.national.com11

10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. (Continued) Symbol Parameter Conditions LM4935 UnitsTypical (Note 6) Limit (Note 7) AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer) Loudspeaker Audio Path Gain Minimum Gain from AUX input, BOOST OFF –34.5 dB Maximum Gain from AUX input, BOOST OFF 12 dB Minimum Gain from CPI input –22.5 dB Maximum Gain from CPI input 24 dB Headphone Audio Path Gain Minimum Gain from AUX input, BOOST OFF –52.5 dB Maximum Gain from AUX input, BOOST OFF –6 dB Minimum Gain from CPI input –40.5 dB Maximum Gain from CPI input 6 dB Minimum Gain from MIC input using SIDETONE path w/ VCR MIC gain = 6dB –30 dB Maximum Gain from MIC input using SIDETONE path w/ VCR MIC gain = 6dB 0d B Earpiece Audio Path Gain Minimum Gain from AUX input, BOOST OFF –40.5 dB Maximum Gain from AUX input, BOOST OFF 6d B Minimum Gain from CPI input –28.5 dB Maximum Gain from CPI input 18 dB Minimum Gain from MIC input using SIDETONE path w/ VCR MIC gain = 6dB –18 dB Maximum Gain from MIC input using SIDETONE path w/ VCR MIC gain = 6dB 12 dB AUXOUT Audio Path Gain Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0d B Minimum Gain from CPI input –34.5 dB Maximum Gain from CPI input 12 dB CPOUT Audio Path Gain Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0d B Minimum Gain from MIC input 6 dB Maximum Gain from MIC input 36 dB LM4935 www.national.com13

10.0 Electrical Characteristics(Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V.The following specifications apply for the circuit shown in Figure 2unless otherwise stated. Limits apply for 25˚C. (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indica tion of device performance. Note 2: All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is P DMAX =( TJMAX –T A)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model: 100pF discharged through a 1.5k Ω resistor. Note 5: Machine model: 220pF – 240pF discharged through all pins. Note 6: Typical values are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level). Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled. Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements. LM4935 www.national.com15

11.0 System Control

Method 1. I2C Compatible Interface

11.1 I2C SIGNALS

In I2C mode the LM4935 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I 2C specification. The I 2C slave address for LM4935 is 00110102.

11.2 I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. 201341Q1 I2C Signals: Data Validity

11.3 I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I 2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I 2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I 2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 201341Q2

11.4 TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9 th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I 2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM4935 address is 00110102. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. 201341Q3 I2C Chip Address Register changes take an effect at the SCL rising edge during the last ACK from slave. LM4935 www.national.com 16

11.0 System Control (Continued)

w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Example I2C Write Cycle LM4935 www.national.com17

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 201341Q6 Example I2C Read Cycle 201341P9 I2C Timing Diagram

11.5 I2C TIMING PARAMETERS

Symbol Parameter Limit Units Min Max 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs

3 Clock High Time 600 ns

4 Setup Time for a Repeated START Condition 600 ns

5 Data Hold Time (Output direction, delay generated by LM4935) 300 900 ns

5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns

6 Data Setup Time 100 ns

7 Rise Time of SDA and SCL 20+0.1C b 300 ns 8 Fall Time of SDA and SCL 15+0.1C b 300 ns

9 Set-up Time for STOP condition 600 ns

10 Bus Free Time between a STOP and a START Condition 1.3 µs Cb Capacitive Load for Each Bus Line 10 200 pF NOTE: Data guaranteed by design LM4935 www.national.com 18

FIGURE 3. SPI Write Transaction FIGURE 4. SPI Read Transaction FIGURE 5. SPI Timing

12.0 Status & Control Registers

TABLE 1. Register Map For all registers, the default setting of data bits 7 through 0 are all set to zero. RESERVED bits should always be set to zero.

12.0 Status & Control Registers(Continued)

12.1 BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip. TABLE 2. BASIC (0x00h)

2 Off Off Power-down Mode

012 Off On Stand-by mode with headset event

102 On Off Active without headset event detection

112 On On Active with headset event detection

2 PLL_ENABLE If set the PLL can be used. functions such as click and pop. to both headphone outputs and their levels are reduced by 6dB to allow enough headroom. 7 OCL If set the part is placed in OCL (Output Capacitor Less) mode. while the audio sub-system is active.

12.2 CLOCKS CONFIGURATION REGISTER

This register is used to control the clocks throughout the chip. TABLE 3. CLOCKS (0x01h) 0 DAC_CLK Selects the clock to be used by the audio DAC system.

0 PLL Input (MCLK or I2S_CLK)

1 PLL Output

1 ADC_CLK Selects the clock to be used by the audio ADC system.

0 MCLK

7:2 R_DIV Programs the R divider (divides from an expected 12.000 MHz input).

0 Bypass

1 Bypass

12.3 LM4935 CLOCK NETWORK

then the DAC and power stage may become unsynchronized and SNR performance may be reduced. FIGURE 6. LM4935 Clock Network

12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC

TABLE 4. Common DAC Clock Frequencies The ADC has an over sampling ratio of 125 so the table below shows the required clock frequency at point C. TABLE 5. Common ADC Clock Frequencies Methods for producing these clock frequencies are described in the PLL Section.

12.5 PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input section of the PLL. TABLE 6. PLL_M (0x02h)

0 RSVD RESERVED

7 PLL_INPUT Programs the PLL input multiplexer to select between:

1 I2S_CLK

The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. Note 11: See Further Notes on PLL Programmingfor more detail.

12.6 PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control the feedback divider of the PLL. TABLE 7. PLL_N (0x03h) (comparison frequency) or F ref (reference frequency), in this document F comp is used. Note 12: See Further Notes on PLL Programmingfor further details.

12.7 PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the output divider of the PLL. TABLE 8. PLL_P (0x04h) 6:4 Q_DIV Programs the Q Divider (divides from an expected 12.000 MHz input).

7 RSVD RESERVED

Note 13: See Further Notes on PLL Programmingfor more details.

12.8 PLL N MODULUS CONFIGURATION REGISTER

This register is used to control the modulation applied to the feedback divider of the PLL. TABLE 9. PLL_N_MOD (0x05h)

2 Medium

012 Small

102 Large

112 Off

Note 14: See Further Notes on PLL Programmingfor more details.

12.9 FURTHER NOTES ON PLL PROGRAMMING

highly unlikely to be a problem. TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates FIGURE 7. PLL Overview

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams). Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M inputs from 1 to 3. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that settin gM=1 ,N= 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR. The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers. LM4935 www.national.com 30

12.10 ADC_1 CONFIGURATION REGISTER

This register is used to control the LM4935’s audio ADC. TABLE 11. ADC_1 (0x06h) 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. 1 CPI_SELECT If set the cell phone input is added to the ADC input signal. 2 LEFT_SELECT If set the left stereo bus is added to the ADC input signal. 3 RIGHT_SELECT If set the right stereo bus is added to the ADC input signal. AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC.

002 No HPF

112 No HPF

12.11 ADC_2 CONFIGURATION REGISTER

This register is used to control the LM4935’s audio ADC. TABLE 12. ADC_2 (0x07h)

0 ULAW/ALAW If COMPAND is set then the data across the PCM interface to the DAC and from the ADC is

1 A-law

1 COMPAND If set the 16 bit PCM data from the ADC is companded before the PCM interface and the PCM

data to the DAC is treated as companded data. 2 ADC_MUTE If set the analog inputs to the ADC are muted. mode to read SAR information whenever both the audio ADC and DAC are inactive. word are 25% shorter to allow generation. Note 15: Refer to the AGC overviewfor further detail.

12.12 AGC_1 CONFIGURATION REGISTER

TABLE 13. AGC_1 (0x08h) input must be passed to the ADC. headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail. gate is not in use as it is required by the AGC algorithm. Note 16: See the AGC overview.

12.13 AGC_2 CONFIGURATION REGISTER

This register is used to control the LM4935’s Automatic Gain Control. TABLE 14. AGC_2 (0x09h) 3:0 AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. Note 17: The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC. mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC overview.

12.14 AGC_3 CONFIGURATION REGISTER

TABLE 15. AGC_3 (0x0Ah) 7:5 AGC_ATTACK Programs the speed at which the AGC will reduce gains if it detects the input level is too large. Note 18: See the AGC overview.

12.15 AGC OVERVIEW

The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation. The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to the target level. To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased at a programmable rate(AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below: 20134112 AGC Operation Example The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain ((1) → (2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the gain at a faster rate ((2) → (3)) to allow the elimination of typical popping noises. Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm. The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC’s HPF should always be enabled. LM4935 www.national.com 36

12.16 MIC_1 CONFIGURATION REGISTER

This register is used to control the microphone configuration. TABLE 16. MIC_1 (0x0Bh) 3:0 PREAMP_GAIN Programs the gain applied to the microphone preamplifier if the AGC is not in use. 4 MIC_MUTE If set the microphone preamplifier is muted. between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to stabilize. This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize. 1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected. To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize.

12.17 MIC_2 CONFIGURATION REGISTER

This register is used to control the microphone configuration. TABLE 17. MIC_2 (0x0Ch)

0 OCL_

available supply and the power output requirements of the headphone amplifiers. driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. supply for a cellular headset external microphone. Please refer to Table 18 for more detail. (parallel push button), shorting out the microphone when pressed. TABLE 18. External MIC Supply Voltages in OCL Mode

12.18 SIDETONE ATTENUATION REGISTER

TABLE 19. SIDETONE (0x0Dh) Programs the attenuation applied to the microphone preamp output to produce a sidetone signal. 1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected. To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to ’0000’ until DC points have stabilized whenever the SIDETONE path is used.

12.19 CP_INPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone input. TABLE 20. CP_INPUT (0x0Eh) 4:0 CPI_LEVEL Programs the gain/attenuation applied to the cell phone input. 5 CPI_MUTE If set the CPI input is muted at source.

12.20 AUX_LEFT CONFIGURATION REGISTER

This register is used to control the left aux analog input. TABLE 21. AUX_LEFT (0x0Fh)

5 AUX_

If set the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above). 6 AUX_L_MUTE If set the AUX LEFT input is muted. the analog power supply is insufficient to cater for the required gain.

12.21 AUX_RIGHT CONFIGURATION REGISTER

This register is used to control the right aux analog input. TABLE 22. AUX_RIGHT (0x10h) If set the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above). 6 AUX_R_MUTE If set the AUX RIGHT input is muted. the analog power supply is insufficient to cater for the required gain.

12.22 DAC CONFIGURATION REGISTER

This register is used to control the DAC levels to the mixer. TABLE 23. DAC (0x11h)

5 USE_AUX_

a stereo balance to be applied. 6 BOOST If set the gain of the DAC inputs to the mixer is increased by 12 dB (see above). 7 DAC_MUTE If set the stereo DAC input is muted on the next zero crossing. analog power supply is insufficient to cater for the required gain.

12.23 CP_OUTPUT CONFIGURATION REGISTER

TABLE 24. CP_OUTPUT (0x12h) 0 MIC_SELECT If set the microphone channel of the mixer is added to the cellphone output signal. 1 RIGHT_SELECT If set the right channel of the mixer is added to the cellphone output signal. 2 LEFT_SELECT If set the left channel of the mixer is added to the cellphone output signal. 3 CPO_MUTE If set the CPOUT output is muted. Note 24: The gain of cell phone output amplifier is 0 dB.

12.24 AUX_OUTPUT CONFIGURATION REGISTER

TABLE 25. AUX_OUTPUT (0x13h) 0 CPI_SELECT If set the cell phone input channel of the mixer is added to the aux output signal. 1 RIGHT_SELECT If set the right channel of the mixer is added to the aux output signal. 2 LEFT_SELECT If set the left channel of the mixer is added to the aux output signal. 3 AUX_MUTE If set the aux output is muted. onboard loudspeaker amplifier gain.

12.25 LS_OUTPUT CONFIGURATION REGISTER

TABLE 26. LS_OUTPUT (0x14h) 0 CPI_SELECT If set the cell phone input channel of the mixer is added to the loudspeaker output signal. 1 RIGHT_SELECT If set the right channel of the mixer is added to the loudspeaker output signal. 2 LEFT_SELECT If set the left channel of the mixer is added to the loudspeaker output signal. 3 LS_MUTE If set the loudspeaker output is muted. Note 26: The gain of the loudspeaker output amplifier is 12 dB.

12.26 HP_OUTPUT CONFIGURATION REGISTER

TABLE 27. HP_OUTPUT (0x15h) 0 SIDETONE_SELECT If set the sidetone channel of the mixer is added to both of the headphone output signals.

1 CPI_SELECT If set the cell phone input channel of the mixer is added to both of the headphone output

4 HP_MUTE If set the headphone output is muted. dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers).

12.27 EP_OUTPUT CONFIGURATION REGISTER

TABLE 28. EP_OUTPUT (0x16h) 0 SIDETONE_SELECT If set the sidetone channel of the mixer is added to the earpiece output signal. 1 CPI_SELECT If set the cell phone input channel of the mixer is added to the earpiece output signal. 2 RIGHT_SELECT If set the right channel of the mixer is added to the earpiece output signal. 3 LEFT_SELECT If set the left channel of the mixer is added to the earpiece output signal. 4 EP_MUTE If set the earpiece output is muted. Note 28: The gain of the earpiece output amplifier is 6 dB.

12.28 DETECT CONFIGURATION REGISTER

This register is used to control the headset detection system. TABLE 29. DETECT (0x17h) an IRQ that has been triggered by the headset detect. has been triggered by a button event. triggered by a temperature event. insertion/removal of a headset.

12.29 HEADSET DETECT OVERVIEW

The LM4935 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM4935 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no analog supply current when the headset is absent. The LM4935 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of control register settings. The LM4935 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset micro- phone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in stand-by mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push button. Upon button press, the LM4935 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN (bit 3 of STATUS (0x18h)) can be read. The LM4935 can also be programmed to raise an interrupt on the IRQ pin when button press is sensed by setting bit 1 of DETECT. The LM4935 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button. Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch). Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the debounce time for series button press in defined by HS_DBNC_TIME. Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push button detection all following bits should be defined before enabling the headset detection system: 1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 7 of BASIC (0x00h)) 2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h)) 3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch)) 4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch)) Figure 8 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from the MIC_DET pin to ground when a headset is not inserted. LM4935 www.national.com 50

FIGURE 8. Headset Configurations Supported by the LM4935

FIGURE 9. Connection of Headset Jack to LM4935 Depends on the Mode of the Headphone Amplifier.

12.30 STATUS REGISTER

This register is used to report the status of the device. TABLE 30. STATUS (0x18h)

0 HEADSET This field is high when headset presence is detected (only valid if the detection system is

1 STEREO_

whenever the loudspeaker amplifier is turned off.

7 GPIN When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back

Note 29: The detection IRQ is cleared when this register has been written to.

12.31 AUDIO INTERFACE CONFIGURATION REGISTER

This register is used to control the configuration of the audio data interfaces. TABLE 31. AUDIO_IF (0x19h) 1:0 AUDIO_IF_MODE Selects the function of the 6 audio interface IOs.

002 I2S

012 PCM

102 PCM

112 I2S

2 I2S_WS_MS If set the I 2S_WS is produced by the LM4935 and the I 2S_WS pin will be an output. 3 I2S_CLK_MS If set the I 2S_CLK is produced by the LM4935 and the I 2S_CLK pin will be an output. 4 PCM_SYNC_MS If set the PCM_SYNC is produced by the LM4935 and the relevant pin will be an output. 5 PCM_CLK_MS If set the PCM_CLK is produced by the LM4935 and the relevant pin will be an output.

2 AUDIO ADC SAR_CH_SEL

012 SAR VSAR 1 SAR_CH_SEL

102 SAR VSAR 2 SAR_CH_SEL

112 A_VDD/2 SAR_CH_SEL

12.32 DIGITAL AUDIO DATA FORMATS

the risk of sample rate mismatch between the data converters and the audio interfaces. When SAR SDO data is passed to the I2S, it is left aligned (MSB aligned) to allow lower I2S resolutions to be used. If the DAC is driven from the PCM interface then the left channel of the DAC is used and the right channel is inactive. FIGURE 10. I2S Serial Data Format (Default Mode) FIGURE 11. PCM Serial Data Format (16 bit Slave Example)

12.33 GPIO CONFIGURATION REGISTER

This register is used to control the GPIO system. TABLE 32. GPIO (0x1Ah) 2:0 GPIO_SEL This sets the function of the GPIOs when the Audio Interface is not using them.

0012 READABLE SPI_SDO

0102 LS_AMP_ENABLE SPI_SDO

0112 GPIO_DATA SPI_SDO

1012 READABLE SAR_SDO

1102 LS_AMP_ENABLE SAR_SDO

1112 GPIO_DATA SAR_SDO

amplifier for stereo loudspeaker applications.

002 VSAR_1

012 VSAR_2

102 D_VDD/2 or BB_VDD

112 A_VDD/2

6 PCM_LONG If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync. 7 GPIO_DATA If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output. FIGURE 12. I2S Serial Data Format (Left Justified Mode)

12.34 SAR CHANNELS0&1 CONFIGURATION REGISTER

TABLE 33. SAR_SLOT01 (0x1Bh)

3 SLOT_0_ENB If set then VSAR 1 is sampled into SAR slot 0 which also activates the

7 SLOT_1_ENB If set then VSAR 2 is sampled into SAR slot 1 which also activates the

Note 31: See the section SAR Overviewfor more details on this register.

12.35 SAR CHANNELS2&3 CONFIGURATION REGISTER

TABLE 34. SAR_SLOT23 (0x1Ch)

3 SLOT_2_ENB If set then D_V DD / 2 or BB_V DD (depending on SLOT2_VBB) is sampled

into SAR slot 2 which also activates the SAR ADC.

4 SLOT_3_ENB If set then A_V DD / 2 is sampled into SAR slot 3 which also activates the

5 SLOT_2_VBB If set then BB_V DD input is used as input to SAR slot 2 rather than the

12.36 SAR DATA 0 TO 3 REGISTERS

These registers are used to read the 8 MSBs from the 4 SAR channels. TABLE 35. SAR_DATA_0 Register (0x1Dh) 7:0 SLOT_0_DATA Latest slot 0 sample bits 11:4. TABLE 36. SAR_DATA_1 Register (0x1Eh) 7:0 SLOT_1_DATA Latest slot 1 sample bits 11:4. TABLE 37. SAR_DATA_2 Register (0x1Fh) 7:0 SLOT_2_DATA Latest slot 2 sample bits 11:4. TABLE 38. SAR_DATA_3 Register (0x20h) 7:0 SLOT_3_DATA Latest slot 3 sample bits 11:4.

12.37 SAR OVERVIEW

the ADC is settling to reduce power consumption. software overhead and IO bandwidth, further reducing system power. perform housekeeping duties such as voltage monitoring with minimal power consumption. *Depending on SLOT_2_VBB in SAR_SLOT23 (0x1Ch). FIGURE 13. Internal SAR Control Signals to SAR Module

Only the 8 MSBS [11:4] from the 12 bits of SAR output data can be read back using the I 2C interface. is stable during the read operation. interface. This is accomplished by setting I2S_SDO_DATA (bit [7:6] of (0x19h)) to the desired SAR channel(s). MSB is aligned with the MSB of I2S_SDO. FIGURE 14. SPI SAR Read Transaction (GPIO2 set to SAR_SDO) FIGURE 15. SPI SAR Read Transaction (GPIO2 set to SPI_SDO)

12.38 DC VOLUME CONFIGURATION REGISTER

This register is used to control the DC volume control system. TABLE 39. DC_VOLUME (0x21h)

0 DC_VOL_ENB Enables the DC volume control system to use the voltage applied on the

1 DC_VOL_EFFECT Selects which volume is altered:

0 AUX/DAC

1 CPI

FIGURE 16. DC Volume Transfer Function For AUX/DAC

12.39 SAR TRIGGER 1 CONFIGURATION REGISTER

This register is used to setup a voltage trigger on one of the SAR outputs. TABLE 40. TRIG_1 (0x22h) 0 TRIG_1_ENB Enables the 1st SAR trigger interrupt, if cleared will clear the IRQ.

1 TRIG_1_DIR Selects the direction the voltage should be moving:

0 Above Threshold

1 Below Threshold

3:2 TRIG_1_SOURCE Programs the channel used by the trigger.

2 VSAR_1

7:4 TRIG_1_LSB Sets bits 3:0 of the threshold used by the trigger.

12.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER

This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. TABLE 41. TRIG_1_MSB (0x23h) 7:0 TRIG_1_MSB Sets bits 11:4 of the threshold used by the trigger.

12.41 SAR TRIGGER 2 CONFIGURATION REGISTER

This register is used to setup a voltage trigger on one of the SAR outputs. TABLE 42. TRIG_2 (0x24h) 0 TRIG_2_ENB Enables the 2nd SAR trigger interrupt, if cleared will clear the IRQ.

1 TRIG_2_DIR Selects the direction the voltage should be moving:

7:4 TRIG_2_LSB Sets bits 3:0 of the threshold used by the trigger.

12.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER

This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. TABLE 43. TRIG_2_MSB (0x25h) 7:0 TRIG_2_MSB Sets bits 11:4 of the threshold used by the trigger.

12.43 DEBUG REGISTER

This register is used to set test modes within the device. TABLE 44. DEBUG (0x26h)

1 RSVD Reserved

2 RSVD Reserved

3 SOFT_RESET This field can be used to reset the chip without a power cycle.

4 RSVD Reserved

5 RSVD Reserved

6 RSVD Reserved

digital microphone as long as AUDIO_IF_MODE (0x19h) is not set to ’11’.

2 RSVD RSVD

0012 RSVD RSVD

0102 VADC_CLOCK_OUT DIG_MIC_IN

0112 RSVD RSVD

1002 RSVD RSVD

1012 RSVD RSVD

1102 RSVD RSVD

1112 RSVD RSVD

13.0 Typical Performance Characteristics

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DV DD = 3.3V unless otherwise specified. Stereo DAC Frequency Response fS = 8kHz Stereo DAC Frequency Response Zoom fS = 8kHz 20134136 20134137 Stereo DAC Frequency Response fS = 16kHz Stereo DAC Frequency Response Zoom fS = 16kHz 20134138 20134139 Stereo DAC Frequency Response fS = 24kHz Stereo DAC Frequency Response Zoom fS = 24kHz 20134140 20134141 LM4935 www.national.com 68

13.0 Typical Performance Characteristics(Continued)

Stereo DAC Frequency Response fS = 32kHz Stereo DAC Frequency Response Zoom fS = 32kHz 20134142 20134143 Stereo DAC Frequency Response fS = 48kHz Stereo DAC Frequency Response Zoom fS = 48kHz 20134144 20134145 THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) Stereo DAC Crosstalk (0dB DAC, HP SE) 20134146 20134147 LM4935 www.national.com69

MONO ADC Frequency Response fS = 8kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC 20134148 20134149 MONO ADC Frequency Response fS = 8kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 36dB MIC 20134150 20134151 MONO ADC Frequency Response fS = 16kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 6dB MIC 20134152 20134153 LM4935 www.national.com 70

MONO ADC Frequency Response fS = 16kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC 20134154 20134155 MONO ADC Frequency Response fS = 24kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 6dB MIC 20134156 20134157 MONO ADC Frequency Response fS = 24kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 36dB MIC 20134158 20134169 LM4935 www.national.com71

MONO ADC Frequency Response fS = 32kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC 20134159 20134160 MONO ADC Frequency Response fS = 32kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 36dB MIC 20134161 20134162 MONO ADC HPF Frequency Response fS = 8kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) MONO ADC HPF Frequency Response fS = 16kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) 20134163 20134164 LM4935 www.national.com 72

MONO ADC HPF Frequency Response fS = 24kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) MONO ADC HPF Frequency Response fS = 32kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) 20134165 20134166 MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 6dB MIC) MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 36dB MIC) 20134167 20134168 MONO ADC PSRR vs Frequency AVDD = 3.3V, 6dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 6dB MIC 20134170 20134171 LM4935 www.national.com73

MONO ADC PSRR vs Frequency AVDD = 3.3V, 36dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 36dB MIC 20134172 20134173 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20134174 20134175 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI inputs terminated) 20134176 20134177 LM4935 www.national.com 74

AVDD = 3.3V, 0dB DAC (DAC inputs selected) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 20134178 20134179 CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) CPOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 20134180 20134181 CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) CPOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 20134182 20134183 LM4935 www.national.com75

AVDD = 3.3V, 36dB MIC (EXTMIC inputs terminated, AGC on) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (EXTMIC inputs terminated, AGC on) 20134185 20134187 CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 20134188 20134189 CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 20134190 20134191 LM4935 www.national.com 76

AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 20134192 20134193 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 20134196 20134197 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 20134198 20134199 LM4935 www.national.com77

AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 201341A0 201341A1 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC on) 201341A2 201341A3 CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC (INTMIC SE input terminated, AGC on) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (INTMIC SE input terminated, AGC on) 201341A5 201341A7 LM4935 www.national.com 78

Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 201341A8 201341A9 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 201341B0 201341B1 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Earpiece PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 201341B2 201341B3 LM4935 www.national.com79

Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 201341B4 201341B5 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.2V (CPI input terminated) 201341B6 201341B7 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB ADC, OCL 1.2V (DAC input selected) 201341B8 201341B9 LM4935 www.national.com 80

Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.5V (AUX inputs terminated) 201341C0 201341C1 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.5V (CPI input terminated) 201341C2 201341C3 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, OCL 1.5V (DAC input selected) 201341C4 201341C5 LM4935 www.national.com81

Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, SE (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, SE (AUX inputs terminated) 201341C6 201341C7 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, SE (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, SE (CPI input terminated) 201341C8 201341C9 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, SE (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, SE (DAC input selected) 201341D0 201341D1 LM4935 www.national.com 82

Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 201341N6 201341N7 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 201341N8 201341N9 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 201341O0 201341O1 LM4935 www.national.com83

INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.0V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.0V 201341D2 201341D3 INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.5V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.5V 201341D4 201341D5 INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.8V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.8V 201341D6 201341D7 LM4935 www.national.com 84

INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT =1 VRMS,5 kΩ 201341D8 201341D9 AUXOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT =1 VRMS,5 kΩ CPOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT =1 VRMS,5 kΩ 201341E0 201341E1 CPOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT =1 VRMS,5 kΩ Earpiece THD+N vs Frequency AVDD = 3.3V, 0dB, POUT = 500mW, 32Ω 201341E2 201341E3 LM4935 www.national.com85

Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.5mW, 32Ω 201341E4 201341E5 Headphone THD+N vs Frequency AVDD = 5V, OCL 1.5V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.2V, 0dB POUT = 7.5mW, 32Ω 201341E6 201341N1 Headphone THD+N vs Frequency AVDD = 5V, OCL 1.2V, 0dB POUT = 10mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, SE, 0dB POUT = 7.5mW, 32Ω 201341E7 201341E8 LM4935 www.national.com 86

Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32Ω Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15µH+8Ω+15µH 201341E9 201341O2 Loudspeaker THD+N vs Frequency AVDD = 5V, POUT = 400mW 15µH+8Ω+15µH Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 16Ω 201341O3 201341F0 Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 32Ω 201341F1 201341F2 LM4935 www.national.com87

Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16Ω 201341F3 201341F4 Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 32Ω 201341F5 201341F6 Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω 201341F7 201341F8 LM4935 www.national.com 88

Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω 201341F9 201341G0 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω 201341G1 201341G2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω 201341G3 201341G4 LM4935 www.national.com89

Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω 201341G5 201341G6 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω 201341G7 201341G8 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω 201341G9 201341H0 LM4935 www.national.com 90

Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω 201341H1 201341H2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 16Ω 201341H3 201341H4 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 32Ω 201341H5 201341H6 LM4935 www.national.com91

Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16Ω 201341H7 201341H8 Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 32Ω 201341H9 201341I0 Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 201341I1 201341I2 LM4935 www.national.com 92

Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 201341I3 201341I4 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 201341I5 201341I6 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω 201341I7 201341I8 LM4935 www.national.com93

Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω 201341I9 201341J0 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω 201341J1 201341J2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 201341J3 201341J4 LM4935 www.national.com 94

Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 201341J5 201341J6 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 201341J7 201341J8 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω 201341J9 201341K0 LM4935 www.national.com95

Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω 201341K1 201341K2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω 201341K3 201341N2 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 16Ω 201341N3 201341N4 LM4935 www.national.com 96

Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32Ω 201341N5 201341K4 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 16Ω 201341K5 201341K6 Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 32Ω 201341K7 201341K8 LM4935 www.national.com97

Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32Ω Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH 201341K9 201341O4 Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH 201341O5 201341O6 Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH 201341O7 201341O8 LM4935 www.national.com 98

Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH 201341O9 201341P0 Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH 201341P1 201341P2 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 201341L0 201341L1 LM4935 www.national.com99

AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5kΩ 201341L2 201341L3 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 201341L4 201341L5 AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 201341L6 201341L7 LM4935 www.national.com 100

CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 201341L8 201341L9 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ 201341M0 201341M1 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 6dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 6dB MIC fOUT = 1kHz, 5kΩ 201341M2 201341M3 LM4935 www.national.com101

CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 201341M4 201341M5 CPOUT THD+N vs Output Voltage AVDD = 3.3V, 36dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 36dB MIC fOUT = 1kHz, 5kΩ 201341M6 201341M7 Headphone Crosstalk vs Frequency OCL 1.2V, 0dB AUX, 32Ω Headphone Crosstalk vs Frequency OCL 1.5V, 0dB AUX, 32Ω 201341M8 201341M9 LM4935 www.national.com 102

Headphone Crosstalk vs Frequency SE, 0dB AUX, 32Ω 201341N0 LM4935 www.national.com103

14.0 LM4935 Demonstration Board Schematic Diagram

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15.0 Demoboard PCB Layout

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15.0 Demoboard PCB Layout(Continued)

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16.0 Product Status Definitions

Datasheet Status Product Status Definition Advance Information Formative or in Design This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This data sheet contains preliminary data. Supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Obsolete Not in Production This data sheet contains specifications on a product that has been discontinued by National Semiconductor Corporation. The datasheet is printed for reference information only. National Semiconductor B.V reserves the right to make changes without notice to any products herein to improve reliability, function or design. Nati onal does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the right of others. LM4935 www.national.com 110

17.0 Revision History

1.0 5/11/05 Filled in the actual limits (for TBDs) under Limit and edited few Typical values, all under the EC table. Edits from Alvin F. 1.1 7/29/05 Input more edits. Replaced the correct boards. Replaced the Schematic Diagram (pg 60). 1.2 9/8/05 Added the 1st set of Typ Perf curves. 1.3 9/21/05 Added a couple of tables. 1.4 9/30/05 Input text edits. 1.5 10/5/05 Input more edits. 1.6 10/11/05 More edits. 1.7 10/12/05 First D/S WEB release. 1.8 10/14/5 Input more text edits after the 1st released. 1.9 10/17/05 Input some text edits, then re-released D/S to the WEB. 2.0 10/18/05 More text edits. Also used graphic 20134107 back. LM4935 www.national.com111

18.0 Physical Dimensionsinches (millimeters) unless otherwise noted

49 Bump Microfil Package

Dimensions: X1 = 3.925 mm, X2 = 3.925 mm, X3 = 0.6 mm National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LM4935 Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

Product Information

WLA49VVA specifications and overview.

Summary

Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

Description

Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

Source title WLA49VVA Datasheet(PDF) - National Semiconductor (TI)

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