WF4M32-150G2TM5

WF4M32-XXX5 WEDC | Alldatasheet

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/c49 White Electronic Designs Corporation • (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 I/O8 I/O9 I/O10 A14 A16 A11 A18 I/O0 I/O1 I/O2 RESET CS2 GND I/O11 A10 A15 VCC CS1 A19 I/O3 I/O15 I/O14 I/O13 I/O12 OE A WE I/O I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A12 A21 A13 I/O16 I/O17 I/O18 VCC CS4 NC I/O27 A20 CS3 GND I/O19 I/O31 I/O30 I/O29 I/O28 I/O23 I/O22 I/O21 I/O20 11 22 33 44 55 66 1 12 23 34 45 56 /G65/G117/G103/G117/G115/G116/G32 /G50/G48/G48/G50/G32 /G32 /G82/G101/G118/G46._/G32 /G52 I/O0-31 Data Inputs/Outputs A0-21 Address Inputs WE Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground RESET Reset /G84/G79/G80/G32/G86/G73/G69/G87 /G52/G77/G88/G51/G50/G32/G53/G86/G32/G70/G76/G65/G83/G72/G32/G77/G79/G68/G85/G76/G69/G44/G32/G83/G77/G68/G32/G53/G57/G54/G50/G45/G57/G55/G54/G49/G50/G32/G40/G112/G101/G110/G100/G105/G110/G103/G41 /G70/G69/G65/G84/G85/G82/G69/G83 /G110Access Times of 100, 120, 150ns /G110Packaging:  66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402).  68 lead, 40mm Low Profile CQFP ( Package 502 ), 3.5mm (0.140") height.  68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990CQFJ footprint (Fig. 3) /G110Sector Architecture  32 equal size sectors of 64KBytes per each 2Mx8 chip  Any combination of sectors can be erased. Also supports full chip erase. /G110Minimum 100,000 Write/Erase Cycles Minimum /G66/G76/G79/G67/G75/G32/G68/G73/G65/G71/G82/G65/G77 /G110Organized as 4Mx32 /G110User configurable as 8Mx16 or 16Mx8 in HIP and G4T packages. /G110Commercial, Industrial, and Military Temperature Ranges /G1105 Volt Read and Write. 5V ± 10% Supply. /G110Low Power CMOS /G110Data Polling and Toggle Bit feature for detection of program or erase cycle completion. /G110Supports reading or programming data to a sector not being erased. /G110RESET pin resets internal state machine to the read mode. /G110Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity PRELIMINARY* *This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: For programming information refer to Flash Programming 16M5 Application Note. I/O 0-7 CS1 I/O 8-15 CS2 I/O 16-23 CS3 I/O 24-31 CS OE A0-20 A21 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8 2Mx 8 2M x 8 2M x 8 WE RESET

/c50White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 VCC A11 A12 A13 A14 A15 A16 CS2 OE CS4 A17 A18 A19 A20 A21 RESET NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 NC A CS1 GND CS WE A A10 VCC I/O 0-31 Data Inputs/Outputs A0-21 Address Inputs WE Write Enable CS1-4 Chip Selects OE Output Enable VCC Power Supply RESET Reset GND Ground NC Not Connected /G84/G79/G80/G32/G86/G73/G69/G87 /G80/G73/G78/G32/G68/G69/G83/G67/G82/G73/G80/G84/G73/G79/G78 /G84/G79/G80/G32/G86/G73/G69/G87 The White 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. I/O 0-31 Data Inputs/Outputs A0-20 Address Inputs WE Write Enables CS1-2 Banks Selects OE Output Enable VCC Power Supply GND Ground RESET Reset /G66/G76/G79/G67/G75/G32/G68/G73/G65/G71/G82/G65/G77 /G66/G76/G79/G67/G75/G32/G68/G73/G65/G71/G82/G65/G77 Note: CS1& CS2 are used as bank select I/O 0-7 CS1 I/O 8-15 CS2 I/O 16-23 CS3 I/O 24-31 CS OE A0-20 A21 2M x 8 2M x 8 WE RESET 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8 BUFFER 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 VCC A11 A12 A13 A14 A15 A16 CS1 OE CS2 A17 NC NC NC A A19 A20 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 RESET A NC GND NC WE A A10 VCC 2M x 8 I/O 0-7 CS 1 I/O 8-15 CS 2 I/O 16-23 I/O 24-31 A0-20 OE WE RESET 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8 2M x 8

/c51 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G80/G97/G114/G97/G109/G101/G116/G101/G114/G83/G121/G109/G98/G111/G108 /G67/G111/G110/G100/G105/G116/G105/G111/G110/G115 /G72/G73/G80 /G71/G50/G84 /G71/G52/G84 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Input Leakage Current I LI VCC = 5.5, VIN = GND to VCC 10 10 10 µA Output Leakage Current I LOx32 VCC = 5.5, VIN = GND to VCC 10 10 10 µA VCC Active Current for Read (1) I CC1 CS = VIL, OE = VIH, f = 5MHz 320 215 345 mA VCC Active Current for Program I CC2 CS = VIL, OE = VIH 420 295 445 mA or Erase (2) VCC Standby Current I CC3 VCC = 5.5, CS = VIH, f = 5MHz, RESET = VIH 20 2.0 95 mA Vcc Vcc Vcc /G80/G97/G114/G97/G109/G101/G116/G101/G114/G83/G121/G109/G98/G111/G108/G72/G73/G80/G32/G40/G72/G50/G41/G32/G67/G81/G70/G80/G32/G40/G71/G50/G84/G41 /G67/G81/G70/G80/G40/G32/G71/G52/G84/G41 OE capacitance C OE 75 75 20 WE capacitance C WE 75 75 20 CS capacitance C CS 20 50 20 Data I/O capacitance C I/O 30 30 30 Address input capacitance C AD 75 75 20 This parameter is guaranteed by design but not tested. /G65/G66/G83/G79/G76/G85/G84/G69/G32/G77/G65/G88/G73/G77/G85/G77/G32/G82/G65/G84/G73/G78/G71/G83 /G80/G97/G114/G97/G109/G101/G116/G101/G114/G83/G121/G109/G98/G111/G108 /G82/G97/G116/G105/G110/G103/G115 /G85/G110/G105/G116 Voltage on Any Pin Relative to VSS VT -2.0 to +7.0 V Power Dissipation P T 8W Storage Temperature Tstg -65 to +125 °C Short Circuit Output Current I OS 100 mA Endurance - Write/Erase Cycles 100,000 min cycles (Mil Temp) Data Retention (Mil Temp) 20 years /G82/G69/G67/G79/G77/G77/G69/G78/G68/G69/G68/G32/G68/G67/G32/G79/G80/G69/G82/G65/G84/G73/G78/G71/G32/G67/G79/G78/G68/G73/G84/G73/G79/G78/G83 /G80/G97/G114/G97/G109/G101/G116/G101/G114/G83/G121/G109/G98/G111/G108 /G77/G105/G110 /G84/G121/G112 /G77/G97/G120 /G85/G110/G105/G116 Supply Voltage V CC 4.5 5.0 5.5 V Ground V SS 00 0V Input High Voltage V IH 2.0 - V CC + 0.5 V Input Low Voltage V IL -0.5 - +0.8 V Operating Temperature (Mil.) T A -55 - +125 °C Operating Temperature (Ind.) T A -40 - +85 °C /G68/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G45/G32/G67/G77/G79/G83/G32/G67/G79/G77/G80/G65/G84/G73/G66/G76/G69 NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at V IH. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions V IL = 0.3V, V IH = V CC - 0.3V /G67/G65/G80/G65/G67/G73/G84/G65/G78/G67/G69/G32/G40/G80/G70/G41 HIP = 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402). G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3) (Package 509) G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140") (Package 502 )

/c52White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G50/G84/G32/G80/G65/G67/G75/G65/G71/G69/G32/G150/G32/G87/G82/G73/G84/G69/G47/G69/G82/G65/G83/G69/G47/G80/G82/G79/G71/G82/G65/G77/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83/G32/G45/G32/G87/G69/G32/G67/G79/G78/G84/G82/G79/G76/G76/G69/G68 /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108/G45/G49/G48/G48/G45/G49/G50/G48 /G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Write Cycle Time t AVAV tWC 100 120 150 ns Chip Select Setup Time t ELWL tCS 00 0 n s Write Enable Pulse Width t WLWH tWP 45 50 50 ns Address Setup Time t AVWL tAS 00 0 n s Data Setup Time t DVWH tDS 45 50 50 ns Data Hold Time t WHDX tDH 00 0 n s Address Hold Time t WLAX tAH 45 50 50 ns Write Enable Pulse Width High t WHWL tWPH 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase (2) t WHWH2 15 15 15 sec Read Recovery Time before Write t GHWL 00 0 µ s VCC Setup Time t VCS 50 50 50 µ s Chip Programming Time 44 44 44 sec Chip Erase Time (3) 256 256 256 sec Output Enable Hold Time (4) t OEH 10 10 10 ns RESET Pulse Width t RP 500 500 500 ns NOTES: 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G50/G84/G32/G80/G65/G67/G75/G65/G71/G69/G32/G150/G32/G82/G69/G65/G68/G45/G79/G78/G76/G89/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83 /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108/G45/G49/G48/G48/G45/G49/G50/G48/G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Read Cycle Time t AVAV tRC 100 120 150 ns Address Access Time t AVQV tACC 100 120 150 ns Chip Select Access Time t ELQV tCE 100 120 150 ns Output Enable to Output Valid t GLQV tOE 40 50 55 n s Chip Select High to Output High Z (1) t EHQZ tDF 20 30 35 ns Output Enable High to Output High Z (1) t GHQZ tDF 20 30 35 ns Output Hold from Addresses, CS or OE Change, t AXQX tOH 000n s whichever is First RST Low to Read Mode (1) t Ready 20 20 20 µs 1. Guaranteed by design, not tested.

/c53 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G50/G84/G32/G80/G65/G67/G75/G65/G71/G69/G32/G150/G32/G87/G82/G73/G84/G69/G47/G69/G82/G65/G83/G69/G47/G80/G82/G79/G71/G82/G65/G77/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83/G44/G67/G83/G32/G67/G79/G78/G84/G82/G79/G76/G76/G69/G68 /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108/G45/G49/G48/G48/G45/G49/G50/G48/G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Write Cycle Time t AVAV tWC 100 120 150 ns Write Enable Setup Time t WLEL tWS 000 n s Chip Select Pulse Width t ELEH tCP 45 50 50 ns Address Setup Time t AVEL tAS 000 n s Data Setup Time t DVEH tDS 45 50 50 ns Data Hold Time t EHDX tDH 000 n s Address Hold Time t ELAX tAH 45 50 50 ns Chip Select Pulse Width High t EHEL tCPH 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase Time (2) t WHWH2 15 15 15 sec Read Recovery Time t GHEL 000 µ s Chip Programming Time 44 44 44 sec Chip Erase Time (3) 256 256 256 sec Output Enable Hold Time (4) t OEH 10 10 10 ns NOTES: 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling.

/c54White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G52/G84/G32/G65/G78/G68/G32/G72/G50/G32/G80/G65/G67/G75/G65/G71/G69/G83/G32/G150/G32/G87/G82/G73/G84/G69/G47/G69/G82/G65/G83/G69/G47/G80/G82/G79/G71/G82/G65/G77/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83/G32/G45/G32/G87/G69/G32/G67/G79/G78/G84/G82/G79/G76/G76/G69/G68 /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108/G45/G49/G48/G48/G45/G49/G50/G48 /G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Write Cycle Time t AVAV tWC 100 120 150 ns Chip Select Setup Time t ELWL tCS 00 0 n s Write Enable Pulse Width t WLWH tWP 45 50 50 ns Address Setup Time t AVWL tAS 00 0 n s Data Setup Time t DVWH tDS 45 50 50 ns Data Hold Time t WHDX tDH 15 15 15 ns Address Hold Time (1) t WLAX tAH 45 50 50 ns Write Enable Pulse Width High (2) t WHWL tWPH 20 20 20 ns Duration of Byte Programming Operation (3) t WHWH1 300 300 300 µs Sector Erase (4) t WHWH2 15 15 15 sec Read Recovery Time before Write t GH WL 00 0 µ s VCC Setup Time t VCS 50 50 50 µ s Chip Programming Time 44 44 44 sec Chip Erase Time (5) 256 256 256 sec Output Enable Hold Time (6) t OEH 10 10 10 ns RESET Pulse Width t RP 500 500 500 ns NOTES: 1. A21 must be held constant until WE or CS go high, whichever occurs first. 2. Guaranteed by design, but not tested. 3. Typical value for tWHWH1 is 7µs. 4. Typical value for tWHWH2 is 1sec. 5. Typical value for Chip Erase Time is 32sec. 6. For Toggle and Data Polling. /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G52/G84/G32/G65/G78/G68/G32/G72/G50/G32/G80/G65/G67/G75/G65/G71/G69/G83/G32/G150/G32/G82/G69/G65/G68/G45/G79/G78/G76/G89/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83 /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108/G45/G49/G48/G48/G45/G49/G50/G48/G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Read Cycle Time t AVAV tRC 100 120 150 ns Address Access Time t AVQV tACC 100 120 150 ns Chip Select Access Time t ELQV tCE 100 120 150 ns Output Enable to Output Valid t GLQV tOE 50 50 55 ns Chip Select High to Output High Z t EHQZ tDF 40 45 45 ns Output Enable High to Output High Z t GHQZ tDF 40 45 45 ns Output Hold from Addresses, CS or OE Change, t AXQX tOH 000n s whichever is First RST Low to Read Mode t Ready 20 20 20 µs

/c55 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G65/G67/G32/G67/G72/G65/G82/G65/G67/G84/G69/G82/G73/G83/G84/G73/G67/G83/G32/G70/G79/G82/G32/G71/G52/G84/G32/G65/G78/G68/G32/G72/G50/G32/G80/G65/G67/G75/G65/G71/G69/G83/G32/G150/G32/G87/G82/G73/G84/G69/G47/G69/G82/G65/G83/G69/G47/G80/G82/G79/G71/G82/G65/G77/G32/G79/G80/G69/G82/G65/G84/G73/G79/G78/G83/G44/G67/G83/G32/G67/G79/G78/G84/G82/G79/G76/G76/G69/G68 Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75/G87. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. /c80/c97/c114/c97/c109/c101/c116/c101/c114 /c32 /c32 /c84 /c121 /c112 /c85 /c110 /c105 /c116 Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V /G80/G97/G114/G97/G109/G101/G116/G101/G114 /G83/G121/G109/G98/G111/G108 /G45/G49/G48/G48/G45/G49/G50/G48/G45/G49/G53/G48 /G85/G110/G105/G116 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 /G77/G105/G110 /G77/G97/G120 Write Cycle Time t AVAV tWC 100 120 150 ns Write Enable Setup Time t WLEL tWS 000 n s Chip Select Pulse Width t ELEH tCP 45 50 50 ns Address Setup Time t AVEL tAS 000 n s Data Setup Time t DVEH tDS 45 50 50 ns Data Hold Time t EHDX tDH 15 15 15 ns Address Hold Time (1) t ELAX tAH 45 50 50 ns Chip Select Pulse Width High t EHEL tCPH 20 20 20 ns Duration of Byte Programming Operation (2) t WHWH1 300 300 300 µs Sector Erase Time (3) t WHWH2 15 15 15 sec Read Recovery Time t GHEL 000 µ s Chip Programming Time 44 44 44 sec Chip Erase Time (4) 256 256 256 sec Output Enable Hold Time (5) t OEH 10 10 10 ns NOTES: 1. A21 must be held constant until WE or CS go high, whichever occurs first. 2. Typical value for tWHWH1 is 7µs. 3. Typical value for tWHWH2 is 1sec. 4. Typical value for Chip Erase Time is 32sec. 5. For Toggle and Data Polling. RESET tRP tReady

/c56White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53

/c57 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D 7 is the output of the complement of the data written to each chip. 4. D OUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.

/c49/c48White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 NOTE: 1. SA is the sector address for Sector Erase.

/c49/c49 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 CS OE WE tOE tCE tCH tOH D7 D7 = Valid Data High Z D0-D6 = Invalid D0-D7 Valid Data tDF D0-D6 tOEH tWHWH 1 or 2 Data

/c49/c50White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D 7 is the output of the complement of the data written to each chip. 4. D OUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.

/c49/c51 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G80/G65/G67/G75/G65/G71/G69/G32/G52/G48/G50/G58/G32/G32/G32/G54/G54/G32/G80/G73/G78/G44/G32/G80/G71/G65/G32/G84/G89/G80/G69/G44/G32/G67/G69/G82/G65/G77/G73/G67/G32/G72/G69/G88/G45/G73/G78/G45/G76/G73/G78/G69/G32/G80/G65/G67/G75/G65/G71/G69/G44/G32/G72/G73/G80/G32/G40/G72/G50/G41 ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES /G80/G65/G67/G75/G65/G71/G69/G32/G53/G48/G50/G58/G32/G32/G32/G54/G56/G32/G76/G69/G65/G68/G44/G32/G67/G69/G82/G65/G77/G73/G67/G32/G81/G85/G65/G68/G32/G70/G76/G65/G84/G32/G80/G65/G67/G75/G44/G32/G76/G79/G87/G32/G80/G82/G79/G70/G73/G76/G69/G32/G67/G81/G70/G80/G32/G40/G71/G52/G84/G41

/c49/c52White Electronic Designs Corporation  Phoenix AZ  (602) 437-1520 White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 /G80/G65/G67/G75/G65/G71/G69/G32/G53/G48/G57/G58/G32/G32/G32/G54/G56/G32/G76/G69/G65/G68/G44/G32/G67/G69/G82/G65/G77/G73/G67/G32/G81/G85/G65/G68/G32/G70/G76/G65/G84/G32/G80/G65/G67/G75/G44/G32/G67/G81/G70/G80/G32/G40/G71/G50/G84/G41 ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES The White 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.

/c49/c53 White Electronic Designs Corporation  (602) 437-1520  www.whiteedc.com White Electronic Designs /G87/G70/G52/G77/G51/G50/G45/G88/G88/G88/G53 DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO. 4M x 32 5V Flash Module 64KByte 150ns 66 pin HIP (H2) 5962-97612 01HXX* 4M x 32 5V Flash Module 64KByte 120ns 66 pin HIP (H2) 5962-97612 02HXX* 4M x 32 5V Flash Module 64KByte 100ns 66 pin HIP (H2) 5962-97612 03HXX* 4M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP Low Profile (G4T) 5962-97612 01HXX* 4M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP Low Profile (G4T) 5962-97612 02HXX* 4M x 32 5V Flash Module 64KByte 100ns 68 lead CQFP Low Profile (G4T) 5962-97612 03HXX* 4M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP Low Profile (G2T) 5962-97612 01HXX* 4M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP Low Profile (G2T) 5962-97612 02HXX* 4M x 32 5V Flash Module 64KByte 100ns 68 lead CQFP Low Profile (G2T) 5962-97612 03HXX* /G79/G82/G68/G69/G82/G73/G78/G71/G32/G73/G78/G70/G79/G82/G77/G65/G84/G73/G79/G78 /c76/c69/c65/c68/c32 /c70/c73/c78/c73/c83/c72/c58 Blank = Gold plated leads A = Solder dip leads /c86 /c80/c80 /c32 /c80/c82/c79/c71/c82/c65/c77/c77/c73/c78/c71/c32 /c86/c79/c76/c84/c65/c71/c69 5 = 5 V /c68/c69/c86/c73/c67/c69/c32 /c71/c82/c65/c68/c69/c58 M =Military Screened -55°C to +125°C I =Industrial -40°C to +85°C C =Commercial 0°C to +70°C /c80/c65/c67/c75/c65/c71/c69/c32 /c84/c89/c80/c69/c58 H2 =Ceramic Hex In line Package, HIP (Package 402) G4T = 40mm Low Profile CQFP (Package 502) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) /c65/c67/c67/c69/c83/c83/c32 /c84/c73/c77/c69/c32 /c40/c110/c115/c41 /c79/c82/c71/c65/c78/c73/c90/c65/c84/c73/c79/c78/c44/c32 /c52/c77/c32 /c120/c32 /c51/c50 User configurable as 8M x 16 or 16M x 8 in HIP and G4T packages /c70/c76/c65/c83/c72 /c87/c72/c73/c84/c69/c32 /c69/c76/c69/c67/c84/c82/c79/c78/c73/c67/c32 /c68/c69/c83/c73/c71/c78/c83/c32 /c67/c79/c82/c80/c46 /c87/c32 /c32 /c70/c32 /c32 /c52/c77/c51/c50/c32 /c45/c32 /c88/c88/c88 /c32 /c88 /c32 /c88/c32/c53/c32 /c88 *Pending