WF2M16-XXX5 WEDC | Alldatasheet

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1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY* 2Mx16 Flash MODULE, SMD 5962-97610

FEATURES

/square6 Access Times of 90, 120, 150ns /square6 Packaging:

  • 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP footprint.
  • 44 pin Ceramic SOJ (Package 102)**
  • 44 lead Ceramic Flatpack (Package 208)** /square6 Sector Architecture
  • 32 equal size sectors of 64KBytes each
  • Any combination of sectors can be erased. Also supports full chip erase. /square6 Minimum 100,000 Write/Erase Cycles Minimum /square6 Organized as 2Mx16; User Confi gurable as 2 x 2Mx8 /square6 Commercial, Industrial, and Military Temperature Ranges /square6 5 Volt Read and Write. 5V ± 10% Supply. /square6 Low Power CMOS /square6 Data# Polling and Toggle Bit feature for detection of program or erase cycle completion. /square6 Supports reading or programming data to a sector not being erased. /square6 Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation. /square6 RESET# pin resets internal state machine to the read mode. /square6 Ready/Busy (RY#/BY#) output for detection of program or erase cycle completion. /square6 Multiple Ground Pins for Low Noise Operation * This product is under development, is not qualifi ed or characterized and is subject to change without notice. ** Package to be developed. Note: For programming information refer to Flash Programming 16M5 Application Notes. FIGURE 1 – PIN CONFIGURATIONS PIN DESCRIPTION I/O0-15 Data Inputs/Outputs A0-20 Address Inputs WE# Write Enable CS1-2# Chip Select OE# Output Enable VCC Power Supply VSS Ground RY/BY# Ready/Busy RESET# Reset BLOCK DIAGRAM NOTE: 1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor. 2. Address compatible with Intel 2M8 56 SSOP. TOP VIEW WF2M16-XDAX5

56 CSOP

CS1# A12 A13 A14 A15 NC CS2# NC A20 A19 A18 A17 A16 V CC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC NC #RESET A11 A10 GND V CC I/O9 I/O1 I/O8 I/O0 NC NC NC I/O2 I/O10 I/O3 I/O11 GND 2M x 8 2M x 8 A0-20 OE# WE# CS 1# CS 2# I/O 0-7 I/O 8-1 RESET# RY/BY# TOP VIEW CS1# A12 A13 A14 A15 NC CS2# NC A20 A19 A18 A17 A16 V CC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC NC #RESET A11 A10 GND V CC I/O9 I/O1 I/O8 I/O0 NC NC NC I/O2 I/O10 I/O3 I/O11 GND WF2M16-XXX5

44 CSOJ (DL)**

44 FLATPACK (FL)**

** Package to be developed.

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Ratings Unit Voltage on Any Pin Relative to VSS V T -2.0 to +7.0 V Power Dissipation P T 8W Storage Temperature T STG -65 to +125 °C Short Circuit Output Current I OS 100 mA Data Retention (Mil Temp) 20 years Endurance — write/erase cycles (Mil Temp) 100,000 min. cycles RECOMMENDED DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Ground V SS 000V Input High Voltage V IH 2.0 – V CC + 0.5 V Input Low Voltage V IL -0.5 – +0.8 V Operating Temperature (Mil.) T A -55 – +125°C °C Operating Temperature (Ind.) T A -40 – +85 °C DC CHARACTERISTICS - CMOS COMPATIBLE VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Conditions Min Max Unit Input Leakage Current I LI VCC = 5.5, VIN = GND to VCC 10 µA Output Leakage Current I LO VCC = 5.5, VIN = GND to VCC 10 µA VCC Active Current for Read (1) I CC1 CS# = VIL, OE# = VIH, f = 5MHz 80 mA VCC Active Current for Program or Erase (2) I CC2 CS# = VIL, OE# = VIH 120 mA VCC Standby Current I CC3 VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC ± 0.3V 4.0 mA Output Low Voltage V OL IOL = 12.0 mA, VCC = 4.5 0.45 V Output High Voltage V OH IOH = -2.5 mA, VCC = 4.5 0.85xV CC V Low VCC Lock-Out Voltage V LKO 3.2 4.2 V CAPACITANCE (TA = +25°C) Parameter Symbol Conditions Max Unit OE# capacitance C OE VIN = 0V, f = 1.0 MHz 25 pF WE# capacitance C WE VIN = 0V, f = 1.0 MHz 25 pF CS# capacitance C CS VIN = 0V, f = 1.0 MHz 15 pF Data I/O capacitance C I/O VI/O = 0V, f = 1.0 MHz 15 pF Address input capacitance C AD VIN = 0V, f = 1.0 MHz 25 pF This parameter is guaranteed by design but not tested. NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at V IH. 2. I CC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions V IL = 0.3V, VIH = VCC - 0.3V

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY AC Characteristics – Write/Erase/Program Operations - WE# Controlled VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -90 -120 -150 Unit Min Max Min Max Min Max Write Cycle Time t AVAV tWC 90 120 150 ns Chip Select Setup Time t ELWL tCS 000 n s Write Enable Pulse Width t WLWH tWP 45 50 50 ns Address Setup Time t AVWL tAS 000 n s Data Setup Time t DVWH tDS 45 50 50 ns Data Hold Time t WHDX tDH 000 n s Address Hold Time t WLAX tAH 45 50 50 ns Write Enable Pulse Width High t WHWL tWPH 20 20 20 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 µs Sector Erase (2) t WHWH2 15 15 15 sec Read Recovery Time before Write t GHWL 000 µ s VCC Setup Time t VCS 50 50 50 µs Chip Programming Time 44 44 44 sec Chip Erase Time (3) 256 256 256 sec Output Enable Hold Time (4) t OEH 10 10 10 ns RESET# Pulse Width t RP 500 500 500 ns NOTES: 1. Typical value for t WHWH1 is 7µs. 2. Typical value for t WHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. AC CHARACTERISTICS – READ-ONLY OPERATIONS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -90 -120 -150 Unit Min Max Min Max Min Max Read Cycle Time T AVAV TRC 90 120 150 ns Address Access Time T AVQV TACC 90 120 150 ns Chip Select Access Time T ELQV TCE 90 120 150 ns Output Enable to Output Valid T GLQV TOE 40 50 55 ns Chip Select High to Output High Z (1) T EHQZ TDF 20 30 35 ns Output Enable High to Output High Z (1) T GHQZ TDF 20 30 35 ns Output Hold from Addresses, CS# or OE# Change, whichever is First TAXQX TOH 000 n s RESET# Low to Read Mode (1) T READY 20 20 20 µs 1. Guaranteed by design, not tested.

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY FIGURE 3 – AC WAVEFORMS FOR READ OPERATIONS Addresses FCS1#/FCS2# FDx FDx FOE# FWE# Outputs High Z Addresses Stable tOE tRC Output Valid tCE tACC tOH High Z tDF

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D 7# is the output of the complement of the data written to the device. 4. D OUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. FIGURE 4 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED Data# Polling CS# OE# WE# I/O7# I/O OUT

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY FIGURE 5 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS NOTE: 1. SA is the sector address for Sector Erase. Addresses FCS1#/FCS2# FAx FDx FOE# FWE# Data VCC 5555H 2AAAH 2AAAH SA 5555H 5555H tWP tCS tVCS 10H/30H55H80H55H AAHAAH tAH tGHWL tWPH tDH tDS tAS

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY FIG. 6 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FCS# OE# FWE# tOE tCE tCH tOH D7 D7 = Valid Data High Z D0-D6 = Invalid D0-D7 Valid Data tDF D0-D6 tOEH tWHWH 1 or 2

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D 7# is the output of the complement of the data written to the device. 4. D OUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. WE# OE# CS# Data# Polling FIGURE 7 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY PACKAGE 208: 44 LEAD, CERAMIC FLAT PACK ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 28.45 (1.120) ± 0.26 (0.010) 32.64 (1.285) TYP 12.95 (0.510) ± 0.13 (0.005) 3.81 (0.150) TYP 3.18 (0.125) MAX 0.13 (0.005) ± 0.05 (0.002) PIN 1 IDENTIFIER 1.27 (0.050) TYP 9.90 (0.390) ± 0.13 (0.005) 26.67 (1.050) TYP 12.70 (0.500) ± 0.51 (0.020) 5.08 (0.200) ± 0.25 (0.010) 0.43 (0.017) ± 0.05 (0.002) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 102: 44 LEAD, CERAMIC SOJ 1.27 (0.050) TYP 26.7 (1.050) TYP 11.3 (0.446) ± 0.2 (0.009) 3.96 (0.156) MAX 0.2 (0.008) ± 0.05 (0.002) 0.89 (0.035) Radius TYP Package to be developed. Package to be developed.

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY FIGURE 8 – ALTERNATE PIN CONFIGURATION FOR WF2M16W-XDAX5 PACKAGE 207: 56 LEAD, CERAMIC SOP* ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES * Package Dimensions subject to change 12.96 (0.510) ± 0.15 (0.006) 0.18 (0.007) 16.13 (0.635) ± 0.13 (0.005) 0.25 (0.010) ± 0.05 (0.002) 0.80 (0.031) TYP a 3.57 (0.140) ± 0.51 (0.020) PIN 1 IDENTIFIER 0 / -4 1.60 (0.063) TYP 0.51 (0.020) TYP DETAIL "A" SEE DETAIL "A" 0.51 (0.020) ± 0.13 (0.005) 3.43 (0.120) ± 0.38 (0.015) 0.51 (0.020) ± 0.13 (0.005) BLOCK DIAGRAM NOTE: 1. RY/BY# is an open drain output and should be pulled up toVcc with an external resistor. 2. Address compatible with Intel 1M16 56 SSOP. CS1# A12 A13 A14 A15 NC CS2# A21 A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC NC RESET# A11 A10 GND VCC I/O9 I/O1 I/O8 I/O0 NC NC NC NC I/O2 I/O10 I/O3 I/O11 GND 2M x 8 2M x 8 A1-21 OE# WE# CS 1# CS 2# I/O 0-7 I/O 8-15 RESET# RY/BY# PIN DESCRIPTION I/O0-15 Data Inputs/Outputs A0-21 Address Inputs WE# Write Enable CS1-2# Chip Select OE# Output Enable VCC Power Supply VSS Ground RY/BY# Ready/Busy RESET# Reset

12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WF2M16-XXX5 April 2004 Rev. 5 PRELIMINARY W F 2M16 X - XXX X X 5 X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads V PP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: Q = Compliant -55°C to +125°C M = Military, 883 Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: DA = 56 Lead CSOP (Package 207) fi ts standard 56 SSOP footprint DL = 44 Lead Ceramic SOJ (Package 102)* FL = 44 Lead Ceramic Flatpack (Package 208)* ACCESS TIME (ns) IMPROVEMENT MARK:

  • Address Pinout for 56 CSOP Package W = Word Wide Applications ORGANIZATION of 2M x 16 User confi gurable as 2 x 2M x 8 Flash WHITE ELECTRONIC DESIGNS CORP.

ORDERING INFORMATION

  • Package to be developed. DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO. 2M x 16 Flash MCP 150ns 5962-97610 04HXX 2M x 16 Flash MCP 120ns 5962-97610 05HXX 2M x 16 Flash MCP 90ns 5962-97610 06HXX