WF128K16 ETC1 | Alldatasheet

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White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5

FEATURES

n Access Times of 50, 60, 70, 90, 120 and 150ns n 40 pin Ceramic DIP (Package 303) n Organized as 128Kx16 and 256Kx16 n Sector Architecture

  • 8 equal size sectors of 16KBytes each per chip
  • Any combination of sectors can be concurrently erased. Also supports full chip erase n 100,000 Erase/Program Cycles Minimum (0 °C to 70 °C) n Data Retention, 10 Years at 125 °C n Commercial, Industrial and Military Temperature Ranges 5V FLASH MODULE PRELIMINARY * n 5 Volt Programming; 5V –10% Supply n Low Power CMOS n Embedded Erase and Program Algorithms n TTL Compatible Inputs and CMOS Outputs n Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation n Page Program Operation and Internal Program Control Time * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM A0-16 Address Inputs I/O0-15 Data Input/Output CS1-2 Chip Selects OE Output Enable WE Write Enable VCC +5.0V Power GND Ground PIN DESCRIPTION 128K x 8 128K x 8 A 0-16 OE WE CS 1 CS 2 128K x 8 128K x 8 I/O8-15I/O0-7 (1) (1) NOTE: 1. CS 1 and CS2 are used to select the lower and upper 128Kx16 of the device. CS 1 and CS2 must not be enabled at the same time. BLOCK DIAGRAM FOR WF256K16-XCX5 BLOCK DIAGRAM FOR WF128K16-XCX5 TOP VIEW CS2*/NC CS1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE V CC WE A16 A15 A14 A13 A12 A11 A10 GND 128K x 8 A 0-16 OE WE CS 1 128K x 8 I/O8-15I/O0-7 * CS2 for 256Kx16 and NC for 128Kx16 October 1998

2White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5 ABSOLUTE MAXIMUM RATINGS (1) NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot V SS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is V CC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A 9 pin is -0.5V. During voltage transitions, A 9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A 9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns. CAPACITANCE (TA = 25°C) DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, V SS = 0V, TA = -55°C to +125 °C) Parameter Unit Operating Temperature -55 to +125 °C Supply Voltage Range (VCC) -2.0 to +7.0 V Signal voltage range (any pin except A9) (2) -2.0 to +7.0 V Storage Temperature Range -65 to +150 °C Lead Temperature (soldering, 10 seconds) +300 °C Data Retention Mil Temp 10 years Endurance (write/erase cycles) Mil Temp 10,000 cycles min. A9 Voltage for sector protect (VID) (3) -2.0 to +14.0 V NOTES: 1. The I CC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at V IH. 2. I CC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: V IL = 0.3V, VIH = VCC - 0.3V Parameter Symbol Conditions 128K x 16 256K x 16 Unit Min Max Min Max Input Leakage Current I LI VCC = 5.5, V IN = GND to V CC 10 10 mA Output Leakage Current I LO VCC = 5.5, V IN = GND to V CC 10 10 mA VCC Active Current for Read (1) I CC1 CS = VIL, OE = VIH 70 80 mA VCC Active Current for Program I CC2 CS = V IL, OE = V IH 100 110 mA or Erase (2) VCC Standby Current I CC3 VCC = 5.5, CS = V IH, f = 5MHz 6 8 mA Output Low Voltage V OL IOL = 12.0 mA, V CC = 4.5 0.45 0.45 V Output High Voltage V OH1 IOH = -2.5 mA, V CC = 4.5 0.85xVcc 0.85xVcc V Output High Voltage V OH2 IOH = -100 mA, V CC = 4.5 V CC -0.4 V CC -0.4 V Low V CC Lock Out Voltage V LKO 3.2 3.2 V Test Symbol Conditions Max Unit OE capacitance C OE VIN = 0 V, f = 1.0 MHz 50 pF WE capacitance C WE VIN = 0 V, f = 1.0 MHz 50 pF CS capacitance C CS VIN = 0 V, f = 1.0 MHz 30 pF I/O0-7 capacitance C I/O VI/O = 0 V, f = 1.0 MHz 30 pF Address capacitance C AD VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.0 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) T A -55 +125 °C Operating Temp. (Ind.) T A -40 +85 °C A9 Voltage for Sector Protect V ID 11.5 12.5 V

White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5 PRINCIPLES OF OPERATION WRITE Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the commands, along with address and data information needed to execute the command. The command register is written by bringing Write-Enable to a logic-low level (V IL), while Chip-Select is low and OE is at VIH. Addresses are latched on the falling edge of the Write-Enable while data is latched on the rising edge of the WE pulse. Standard microprocessor write timings are used. Refer to AC Program characteristics, Figures 4 and 7. TABLE 1 - BUS OPERATIONS Operation CS OE WE A 0 A1 A9 I/O Read L L H A 0 A1 A9 DOUT Standby H X X X X X HIGH Z Output Disable L H H X X X HIGH Z Write L H L A 0 A1 A9 DIN Enable Sector Protect L V ID L XXV ID X Verify Sector Protect L L H L H V ID Code The following principles of operation of the WF128K16-XCX5 and WF256K16-XCX5 are applicable to each 128K x 8 memory chip inside the MCM. Programming of the device is accom- plished by executing the program command sequence. The program algorithm, which is an internal algorithm, automati- cally times the program pulse widths and verifies proper cell margin. Sectors can be programmed and verified in less than 0.3 seconds. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire memory is typically erased and verified in three seconds (including pre-program- ming). BUS OPERATIONS READ The device has two control functions, both of which must be logically active, to obtain data at the outputs. Chip-Select (CS) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins. Figure 3 illustrates read timing waveforms. OUTPUT DISABLE With Output-Enable at a logic-high level (V IH), output from the device is disabled. Output pins are placed in a high impedance state. STANDBY MODE The device has two standby modes, a CMOS standby mode (CS input held at V CC + 0.5V), and a TTL standby mode (CS is held VIH). In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed.

4White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED (VCC = 5.0V, V SS = 0V, TA = -55°C to +125 °C) Parameter Symbol -50 -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Min Max Write Cycle Time t AVAV tWC 50 60 70 90 120 150 ns Chip Select Setup Time t ELWL tCS 00 00 00 n s Write Enable Pulse Width t WLWH tWP 25 30 35 45 50 50 ns Address Setup Time t AVWL tAS 00 00 00 n s Data Setup Time t DVWH tDS 25 30 30 45 50 50 ns Data Hold Time t WHDX tDH 00 00 00 n s Address Hold Time t WLAX tAH 40 45 45 45 50 50 ns Chip Select Hold Time t WHEH tCH 00 00 00 n s Write Enable Pulse Width High t WHWL tWPH 20 20 20 20 20 20 ns Duration of Byte Programming Operation (min) tWHWH1 14 14 14 14 14 14 ms Read Recovery Time Before Write t GHWL 00 00 00 n s VCC Setup Time t VCS 50 50 50 50 50 50 ms Output Enable Setup Time t OES 00 00 00 n s Output Enable Hold Time (1) t OEH 10 10 10 10 10 10 ns 1. For Toggle and Data Polling. AC CHARACTERISTICS – READ ONLY OPERATIONS (VCC = 5.0V, V SS = 0V, TA = -55°C to +125 °C) Parameter Symbol -50 -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Min Max Read Cycle Time t AVAV tRC 50 60 70 90 120 150 ns Address Access Time t AVQV tACC 50 60 70 90 120 150 ns Chip Select Access Time t ELQV tCE 50 60 70 90 120 150 ns OE to Output Valid t GLQV tOE 25 30 35 40 50 55 ns Chip Select to Output High Z (1) t EHQZ tDF 20 20 20 25 30 35 ns OE High to Output High Z (1) t GHQZ tDF 20 20 20 25 30 35 ns Output Hold from Address, CS or OE Change, t AXQX tOH 00 0 0 0 0 n s whichever is first 1. Guaranteed by design, not tested.

White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED (VCC = 5.0V, V SS = 0V, TA = -55°C to +125 °C) Parameter Symbol -50 -60 -70 -90 -120 -150 Unit Min Max Min Max Min Max Min Max Min Max Min Max Write Cycle Time t AVAV tWC 50 60 70 90 120 150 ns WE Setup Time t WLEL tWS 00 0 000 n s CS Pulse Width t ELEH tCP 25 30 35 45 50 50 ns Address Setup Time t AVEL tAS 00 0 000 n s Data Setup Time t DVEH tDS 25 30 30 45 50 50 ns Data Hold Time t EHDX tDH 00 0 000 n s Address Hold Time t ELAX tAH 40 45 45 45 50 50 ns WE Hold from WE High t EHWH tWH 00 0 000 n s CS Pulse Width High t EHEL tCPH 20 20 20 20 20 20 ns Duration of Programming Operation t WHWH1 14 14 14 14 14 14 ms Read Recovery before Write t GHEL 00 0 000 n s FIG. 2 AC TEST CIRCUIT NOTES: VZ is programmable from -2V to +7V. IOL & I OH programmable from 0 to 16mA. Tester Impedance Z 0 = 75 W . VZ is typically the midpoint of V OH and V OL. IOL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. AC TEST CONDITIONS I Current Source D.U.T. C = 50 pfeff IOL V ≈ 1.5V (Bipolar Supply) Z Current Source OH Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V

6White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES FIG. 3 AC WAVEFORMS FOR READ OPERATIONS Addresses CS OE WE Outputs High Z Addresses Stable tOE tRC Output Valid tCE tACC tOH High Z tDF WF128K16, WF256K16-XCX5

White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES FIG. 4 AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED WF128K16, WF256K16-XCX5 NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed. 3. D 7 is the output of the complement of the data written (for each chip). 4. D OUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Addresses CS OE WE Data 5.0 V 5555H PA PA tWC tCS PD D 7 D OUT tAH tWPH tDH tDS Data Polling tAS tRC tWP A0A0H tOE tDF tOH tCE tGHWL tWHWH1

8White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES FIG. 5 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS NOTES: 1. SA is the sector address for Sector Erase. WF128K16, WF256K16-XCX5 Addresses CS OE WE Data VCC 5555H 2AAAH 2AAAH SA 5555H 5555H tWP tCS tVCS 1010H/3030H5555H8080H5555H AAAAHAAAAH tAH tAS tGHWL tWPH tDH tDS

White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES FIG. 6 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS WF128K16, WF256K16-XCX5 CS OE WE tOE tOE tCE tCH tOH I/O7 and I/O15 I/O7 and I/O15 Valid Data High Z I/O0-6 and I/O8-14 Invalid I/O0-15 Valid Data tDF I/O7 and I/O15 I/O0-6 and I/O8-14 tOEH tWHWH 1 or 2Data

10White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES FIG. 7 AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D 7 is the output of the complement of the data written to the device (for each chip). 4. D OUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. Addresses WE OE CS Data 5.0 V 5555H PA PA tWC tWS PD D 7 D OUT tAH tCPH tCP tDH tDS Data Polling tAS tGHEL A0H tWHWH1 WF128K16, WF256K16-XCX5

White Microelectronics • Phoenix, AZ • (602) 437-1520 7FLASH MODULES WF128K16, WF256K16-XCX5

ORDERING INFORMATION

LEAD FINISH: Blank = Gold plated leads A = Solder dip leads V PP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: Q = Compliant M = Military Screened -55°C to 125°C I = Industrial -40 °C to +85°C C = Commercial 0 to +70 °C PACKAGE TYPE: C = 40 Pin Ceramic 0.600" DIP (Package 303) ACCESS TIME (ns) ORGANIZATION, 128K x 16 or 256K x 16 Flash PROM WHITE MICROELECTRONICS W F XXXK16 - XXX C X 5 X PACKAGE 303: 40 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED 15.1 (0.595) – 0.25 (0.010) 3.2 (0.125) MIN 7.2 (0.285) – 0.8 (0.030) 0.94 (0.037) – 0.25 (0.010) 0.25 (0.010) – 0.05 (0.002) 0.5 (0.018) – 0.05 (0.002) 1.27 (0.050) – 0.1 (0.005) 2.5 (0.100) TYP 15.25 (0.600) – 0.25 (0.010) PIN 1 IDENTIFIER ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES