WARP11 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 19

Technical content

blocks has been implemented. This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1. Logic Diagram

Table 2. Absolute Maximum Ratings Notes: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. device reliability.Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. Figure 2. CPGA100 Pin Configuration

Figure 3. PLCC84 Pin Configuration Table 3. Recomended Operation Conditions (Ta=0 to +70°C unless otherwise specified)

approach rather than on on-line calculation. loaded in the downloading phase. Table 4. Pin Description responsible for all the fuzzy related computing. SON Microelectronics process. the off-linemode theyareused toaddress W.A.R.P.

This resulting word allows to identify the appropri- ate memory [cs2-cs0] and its respective address [add6-add0] where the relative I0-I7 are to be stored. When the CHM pin is high, during the off-line phase, W.A.R.P. generates the addresses for its internalmemories and sendthose addresses to the single external memory support where data (.dat file) are located. These addresses, which are sent by means of the EPA0-EPA2 and A0-A9 (EPA0 MSB, A9 LSB) output pins, allow to identify the data (on the EPROM) that have be loaded in In on-line mode A0-A9 are not used. I0-I7:During the off-line phase these 8 data input pins accept the microcode configuration and data to be written into the internal memories. The ante- cedent memory word size is 64 bits, so it is neces- sary to give each word 8 bits at a time. In the same way are written the words of consequent memory and of program memory. In on-line mode this bus carries the input variables 7 bits in accordance with the configuration setting. possible to restart the work during the computation (on-line phase) or before the writing of internal memories (off-line phase). In both cases it must be putlow at least for a clock period. FIN:During the on-line phase it will start the run- time acquisition cycle. This pin is activated by providing a positive pulse for a time no lower than an entire clock period. When all expected inputs have been processed, a new FIN pulse must be sent to activate a new process. OFL: When this pin ishigh, the chip is enabled to load data in the internal RAMs (off-line phase). It must below when the fuzzy controller is waiting for input values and during the processing phase (on- line phase). CHM: This pin, which is usedonly duringthe off-line phase, determines the charge mode. CHM is not When CHM is low the addresses of the internal memory locations where data have to be stored must be sent to W.A.R.P. from the outside by means of the input pins A0-A9. When CHM is highW.A.R.P. automatically gener- ates the addresses of its internal memories and manages the EPROMs reading by means of the addresses contained in EPA0-EPA2 and A0-A9 output pins (13 bits). TE: For testing purpose only. It must be connected to V SS . MTE: For testing purpose only. It must be con- nected to VSS . MCLK: This is the input master clock whose fre- quency can reach up to 40MHz (MAX). During the off-line phase with CHMhigh, the DCLK signal with a frequency of MCLK/32 is gen- erated in order to drive the downloading phase timing. EPA0-EPA2 : During the off-line phase and in cor- respondencewith CHMhigh, theseoutput pins are joined (as MSB) to A0-A9 to obtaine the complete address of the memory support where to read the EPA0-EPA2 are not used when CHM islow or in O0-O9 : These pins carry out the output values. When the STB (strobe pin) ishigh, one output variable can be read by external devices (in on-line mode). The resolution of output variables is 1024 points (10 bits). If there are more than one output, the output variables are calculated one by one and they are provided in the sequencestabilized during the editing phase (see W.A.R.P.-SDT User Man- ual). OCNT0-OCNT3: This 4 bit outputbus provides the output variables with a progressive number during the on-line phase. As a consequenceit is possible to know to which variable correspond the data that are on the outputdata bus (O0-O9).The dimension of OCNT bus is connected with the maximum number of output variables (16). STB: The strobe pin enables the user to utilize the output. When thispin ishighit indicates that a new output variable has been calculated and it is ready on the output bus (O0-O9). This signal synchro- nizes the external devices and in particular the interfaces with the controlled processes (on-line mode). EP: This signallow indicates that the processing of all the rules has been completed. NP: This output pin indicates that a new process can start. NP is automatically setlow before the lastoutput has beencalculated, so thatit is possible to start a new data acquisition before (with a new FIN) the computation is terminated. cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0 add7 add6 add5 add4 add3 add2 add1 add0

data from an external database in off-line mode. trol rules are loaded inside the program memory. data must be loaded 8 bit a time in the data bus. Table 5. Available Configurations on a Single Antecedent Memory. Figure 4. Block Diagram

configuration and the input number. are used to manipulate the consequent MFs. Inference Unit structure is shown in figure 5. the basis of antecedent MFs and logical operators. formula) are stored during the off-line phase. output variable, a resulting membership function. Ω i=membership degree of the output MFi. THETA must be performed on-line. Figure 6. Inference Unit Structure

Figure 7. Defuzzifier Structure Table 6. DC Characteristics

Table 7. AC Characteristics

  • MCLK [INPUT] must be connected with the external synchronization signal.
  • PRST [INPUT] must be set high to enable the device.

on input buses and restores a new SYNC pulse.

  • MCLK [INPUT] must be connected with the external synchronization signal.
  • PRST [INPUT] must be set high to enable the device.
  • SYNC [OUTPUT] will be provided to synchronize input data (I0-I7) coming from the external database.

half a period of DCLK. DCLK frequency is MCLK/32.

  • MCLK [INPUT] must be connectedwith the external synchronization signal.

[1clock,2clock periods]. FIN pulse mustn’t coincide with NP transitions.

  • NP [OUTPUT] will remain low during the acquisition phase.

in I0-I6 are stored into its internal registers at each next rising edge of the MCLK. phase can start. This information is provided thanks to the configuration stored in the program memory. Figure 10. Input/Output Connection Block Diagram

On-line Phase Timing (Output Generation) Working Frequency 40MHz O0-O9 MCLK NP EP en d o f computation OCNT0-3 ST B start of com putation d ata output storag e da ta o u t p u t storag e la st output data OUT NUM n-1la st output number NEW DA T A ACQUISITION DA T A OUT 1 d ata output storag e Tcomp= 600 ns (first proce ss, pipeline empty), 310 ns (next proces ses) for a configuration with 16 inputs, 8 outputs, 28 rules Elapsed time from the first data acquisition to the first output: 810 ns for the first cycle ,525ns for the other ones. TCOMP OUT NUM 1 OUT NUM 2 DA T A OUT n-1DA T A OUT 2 T COMP TCOMPT COMP Timing Table Description: ON-LINE phase 2nd step:Elaboration - MCLK [INPUT] must be connectedwith the external synchronization signal. - OFL [INPUT] must remain low during this phase. - NP [OUTPUT] remains high during this phase. - EP [OUTPUT] is set high during this phase. - STB [OUTPUT] is set high for a clock period every time an output value has been calculated. It informs that it is possible to utilize the outputwhich is situated in the output bus (O0-O9). The STB pulse starts at the rising edge of the MCLK and stops at the next rising edge of the MCLK. At the falling edge of the STB the data situated on the O0-O9 bus can be stored. - The current output on the O0-O9 [OUTPUT] bus is provided exactly when the STB signal rises and it does not change until a new STB signal occurs. - The output identifier on the OCNT0-OCNT3 [OUTPUT] bus is provided exactly when the STB signal rises and it does not change until a new STB signal occurs. - NP [OUTPUT] is set low when the penultimate STROBE is disabled allowing a new acquisition phase to - When the last output has been provided, EP will be automatically set low.

it generates the code to be loaded in W.A.R.P . Debugger, Exporter and Simulator. by using a list of patterns stored into a file. tions exploiting user-developed models. – functionally simulate W.A.R.P.

It can manage up to 16 inputs and 16 outputs. The clock generatorfrequency on board is 24MHz. of the board is described in figure 12. Figure 12. Board Block Diagram

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. written approval of SGS-THOMSON Microelectronics.  ,M i c r o s o f t and Microsoft Windows are registered trademarks of Microsoft Corporation. MATLAB  is a registered trademark of Mathworks Inc. Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. Table 8. Ordering Information

8 MB RAM

approach rather than on on-line calculation. loaded in the downloading phase. responsible for all the fuzzy related computing.