W3HG2128M72ACER534AD6XG

W3HG2128M72ACER-AD6 WEDC | Alldatasheet

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Technical content

Rev. 5 PRELIMINARY* 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs 2GB – 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP

DESCRIPTION

The W3HG2128M72ACER is a 2x128Mx72 Double Data Rate DDR2 SDRAM high density module based on DDR2 SDRAM components. This memory module consists of eighteen stacks of 256Mx4 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate. * This product is under development, is not qualiﬁ ed or characterized and is subject to change without notice. NOTE: Consult factory for availability of:

Vendor source control options
Industrial temperature option
Parity function

FEATURES

/square6 240-pin, dual in-line very low proﬁ le (VLP) memory module /square6 Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4300 and PC2-3200 /square6 Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM components /square6 V CC = VCCQ = 1.8V /square6 V CCSPD = +1.7V to +3.6V /square6 Differential data strobe (DQS, DQS#) option /square6 Four-bit prefetch architecture /square6 DLL to align DQ and DQS transitions with CK /square6 Multiple internal device banks for concurrent operation /square6 Supports duplicate output strobe (RDQS/RDQS#) /square6 Programmable CAS# latency (CL): 3, 4, 5 and 6 /square6 Adjustable data-output drive strength /square6 On-die termination (ODT) /square6 Posted CAS# additive latency: 0, 1, 2, 3 and 4 /square6 Serial Presence Detect (SPD) with EEPROM /square6 64ms: 8,192 cycle refresh /square6 Gold edge contacts /square6 ECC error detection and correction /square6 Dual Rank /square6 RoHS compliant /square6 Package option

240 Pin VLP: 18.29mm (0.720") TYP OPERATING FREQUENCIES PC2-3200 PC2-4300 PC2-5300* PC2-6400* Clock Speed 200MHz 266MHz 333MHz 400MHz CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 * Consult factory for availability

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 PIN CONFIGURATION Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol 1V REF 61 A4 121 V SS 181 V CCQ 2V SS 62 V CCQ 122 DQ4 182 A3

3 DQ0 63 A2 123 DQ5 183 A1

4 DQ1 64 V

5V SS 65 V SS 125 DQS9 185 CK0

6 DQS0# 66 V SS 126 DQS9# 186 CK0#

7D Q S 0 6 7 V CC 127 V SS 187 V CC 8V SS 68 NC/PAR_IN 128 DQ6 188 A0

9 DQ2 69 V CC 129 DQ7 189 V CC

10 DQ3 70 A10/AP 130 V SS 190 BA1

11 V SS 71 BA0 131 DQ12 191 V CCQ

12 DQ8 72 V CCQ 132 DQ13 192 RAS#

13 DQ9 73 WE# 133 V SS 193 S0#

14 V SS 74 CAS# 134 DQS10 194 V CCQ

15 DQS1# 75 V CCQ 135 DQS10# 195 ODT0

16 DQS1 76 S1# 136 V SS 196 A13

17 V SS 77 ODT1 137 NC 197 V CC

18 RESET# 78 V CCQ 138 NC 198 V SS

19 NC 79 V SS 139 V SS 199 DQ36

20 V SS 80 DQ32 140 DQ14 200 DQ37

21 DQ10 81 DQ33 141 DQ15 201 V SS

22 DQ11 82 V SS 142 V SS 202 DQS13

23 V SS 83 DQS4# 143 DQ20 203 NC/DQS13#

24 DQ16 84 DQS4 144 DQ21 204 V SS

25 DQ17 85 V SS 145 V SS 205 DQ38

26 V SS 86 DQ34 146 DQS11 206 DQ39

27 DQS2# 87 DQ35 147 DQS11# 207 V SS

28 DQS2 88 V SS 148 V SS 208 DQ44

29 V SS 89 DQ40 149 DQ22 209 DQ45

30 DQ18 90 DQ41 150 DQ23 210 V SS

31 DQ19 91 V SS 151 V SS 211 DQS14

32 V SS 92 DQS5# 152 DQ28 212 NC/DQS14#

33 DQ24 93 DQS5 153 DQ29 213 V SS

34 DQ25 94 V SS 154 V SS 214 DQ46

35 V SS 95 DQ42 155 DQS12 215 DQ47

36 DQS3# 96 DQ43 156 DQS12# 216 V SS

37 DQS3 97 V SS 157 V SS 217 DQ52

38 V SS 98 DQ48 158 DQ30 218 DQ53

39 DQ26 99 DQ49 159 DQ31 219 V SS

40 DQ27 100 V SS 160 V SS 220 NC

41 V SS 101 SA2 161 CB4 221 NC

42 CB0 102 NC 162 CB5 222 V SS

43 CB1 103 V SS 163 V SS 223 DQS15

44 V SS 104 DQS6# 164 DQS17 224 NC/DQS15#

45 DQS8# 105 DQS6 165 DQS17# 225 V SS

46 DQS8 106 V SS 166 V SS 226 DQ54

47 V SS 107 DQ50 167 CB6 227 DQ55

48 CB2 108 DQ51 168 CB7 228 V SS

49 CB3 109 V SS 169 V SS 229 DQ60

50 V SS 110 DQ56 170 V CCQ 230 DQ61

51 V CCQ 111 DQ57 171 CKE1 231 V SS

52 CKE0 112 V SS 172 V CC 232 DQS16

53 V CC 113 DQS7# 173 NC 233 NC/DQS16#

54 NC 114 DQS7 174 NC 234 V SS

55 NC/ERR_OUT 115 V SS 175 V CCQ 235 DQ62

56 V CCQ 116 DQ58 176 A12 236 DQ63

57 A11 117 DQ59 177 A9 237 V SS

58 A7 118 V SS 178 V CC 238 V CCSPD

59 V CC 119 SDA 179 A8 239 SA0

60 A5 120 SCL 180 A6 240 SA1

BA0,BA1 SDRAM Bank Address DQ0-DQ63 Data Input/Output CB0-CB7 Check Bits DQS0-DQS8 Data strobes DQS0#-DQS8# Data strobes complement DM0-DM8 Data Masks DQS9#-DQS17# Data Strobe Negative DQS9-DQS17 Data Strobe ODT0, ODT1 On-die termination control CK0,CK0# Clock Inputs, positive line CKE0, CKE1 Clock Enables S0#, S1# Chip Selects RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable RESET# Register Reset Input SA0-SA2 SPD address SDA SPD Data Input/Output SCL Serial Presence Detect(SPD) Clock Input V CC Core Power (1.8V) VCCQ I/O Power (1.8V) VSS Ground VREF Power Supply for Reference VCCSPD SPD Power NC Spare pins, No connect

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 FUNCTIONAL BLOCK DIAGRAM Serial PD A1 A2 SA0 SA1 SA2 SCL SDA WP VCCSPD VCC/VCCQ VREF VSS Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs P L L OE CK0 CK0# RESET# PCK0-PCK6, PCK8, PCK9 /barb2right CK : DDR2 SDRAMs PCK0#-PCK6#, PCK8#, PCK9# /barb2right CK# : DDR2 SDRAMs PCK7 /barb2right CK : Register PCK7# /barb2right CK# : Register VSS RS0# DQS0 DQS0# CS#DM DQS DQS# DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 DQS9 DQS9# DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 I/O 0 I/O 1 I/O 2 I/O 3 DQS10 DQS10# DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 DQS2 DQS2# DQ16 DQ17 DQ18 DQ19 I/O 0 I/O 1 I/O 2 I/O 3 DQS11 DQS11# DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 DQS3 DQS3# DQ24 DQ25 DQ26 DQ27 I/O 0 I/O 1 I/O 2 I/O 3 DQS12 DQS12# DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 DQS5 DQS5# DQ40 DQ41 DQ42 DQ43 I/O 0 I/O 1 I/O 2 I/O 3 DQS14 DQS14# DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 DQS4 DQS4# DQ32 DQ33 DQ34 DQ35 I/O 0 I/O 1 I/O 2 I/O 3 DQS13 DQS13# DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 DQS6 DQS6# DQ48 DQ49 DQ50 DQ51 I/O 0 I/O 1 I/O 2 I/O 3 DQS15 DQS15# DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 DQS8 DQS8# CB0 CB1 CB2 CB3 I/O 0 I/O 1 I/O 2 I/O 3 DQS17 DQS17# CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 DQS#7 DQS7# DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 DQS16 DQS16# DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 RS1# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# CS#DM DQS DQS# CS# DM DQS DQS# 1:2 R E G I S T E R RST# S1# BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 CKE1 RESET# PCK7 PCK7#** RS1# /barb2right CS# : DDR2 SDRAMs RBA0-RBA1 /barb2right BA0-BA1 : DDR2 SDRAMs RA0-RA13 /barb2right A0-A13 : DDR2 SDRAMs RRAS# /barb2right RAS# : DDR2 SDRAMs RCAS# /barb2right CAS# : DDR2 SDRAMs RWE# /barb2right WE# : DDR2 SDRAMs RCKE0 /barb2right CKE : DDR2 SDRAMs RCKE1 /barb2right CKE : DDR2 SDRAMs ODT0 ODT1 RODT0 /barb2right ODT : DDR2 SDRAMs RODT1 /barb2right ODT : DDR2 SDRAMs S0# RS0# /barb2right CS# : DDR2 SDRAMs NOTE: All resistor values are 22 ohms unless otherwise speciﬁ ed.

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 RECOMMENDED DC OPERATING CONDITIONS All Voltages Referenced to VSS Parameter Symbol Rating Units NotesMin. Type Max. Supply Voltage V CC 1.7 1.8 1.9 V 4 Supply Voltage for DLL V CCL 1.7 1.8 1.9 V 4 Supply Voltage for Output V CCQ 1.7 1.8 1.9 V 4 Input Reference Voltage V REF 0.49*VCCQ 0.50*VCCQ 0.51*VCCQ V 1, 2 Termination Voltage V TT VREF-0.04 V REF VREF+0.04 V 3 There is no speciﬁ c device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC. 1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VCCQ of the transmitting device and VREF is expected to track variations in VCCQ. 2. Peak to peak AC noise on V REF may not exceed ±2% VREF(DC). 3. V TT of transmitting device must track VREF of receiving device. 4. V CC, VCCQ and VCCL are tied together on this module. ABSOLUTE MAXIMUM RATINGS SSTL_1.8V Symbol Parameter Rating Units Notes VCC Voltage on VCC pin relative to VSS - 1.0 V - 2.3 V V 5 VCCQ Voltage on VCCQ pin relative to VSS - 0.5 V - 2.3 V V 5 VCCL Voltage on VCCL pin relative to VSS - 0.5 V - 2.3 V V 5 VIN, VOUT Voltage on any pin relative to VSS - 0.5 V - 2.3 V V 5 TSTG Storage Temperature -55 to +100 C 5, 6 5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, plea se refer to JESD51-2 standard. CAPACITANCE TA = 25°C, f = VREF = Gnd, f = 100MHz, VCC = VCCQ = 1.8V Parameter Symbol Max Units Input Capacitance: CK, CK# C CK 5.6 pF Input Capacitance: CKE, CS# CI 1 12.4 pF Input Capacitance: Addr. RAS#, CAS#, WE#, ODT CI 2 12.4 pF Input/Output Capacitance: DQ, DQS, DM, DQS#, CB CI O 15.6 pF

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only Symbol Proposed Conditions 806 665 534 403 Units ICC0 Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,720 1,530 1,530 mA ICC1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 1,980 1,800 1,710 mA ICC2P Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 180 180 180 mA ICC2Q Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 1,800 1,440 1,260 mA ICC2N Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,980 1,620 1,440 mA ICC3P Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 TBD 1,260 1,080 900 mA Slow PDN Exit MRS(12) = 1 TBD 360 360 360 mA ICC3N Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 2,340 1,980 1,620 mA ICC4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 2,880 2,430 2,070 mA ICC4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 3,240 2,700 2,160 mA ICC5B Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 7,560 7,200 6,840 mA ICC6 Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING TBD 180 180 180 mA ICC7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the following page for detailed timing conditions TBD 5,130 4,770 4,230 mA NOTE: ICC specs are based on MICRON components. Other DRAM manufacturers parameters may be different.

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 AC TIMING PARAMETERS 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 667 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Clock Clock cycle time CL = 6 t CK (6) TBD TBD ps 16, 24 CL = 5 t CK (5) TBD TBD 3,000 8,000 ps 16, 24 CL = 4 t CK (4) TBD TBD 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24 CL = 3 t CK (3) TBD TBD 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24 Half clock period t HP TBD TBD MIN (tCH, tCL) MIN (tCH, tCL) MIN (tCH, tCL) ps 19 Data DQ output access time from CK/CK# t AC TBD TBD -450 +450 -500 +500 -600 +600 ps Data-out high-impedance window from CK/CK# tHZ TBD TBD tAC (MAX) tAC MAX tAC MAX ps 8, 9 Data-out low-impedance window from CK/CK# t LZ TBD TBD tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) ps 8, 10 DQ and DM input setup time relative to DQS t DSa TBD TBD 300 350 400 ps 7, 15, DQ and DM input hold time relative to DQS t DHa TBD TBD 300 350 400 ps 7, 15, DQ and DM input setup time relative to DQS t DSb TBD TBD 100 100 150 t CK 7, 15, DQ and DM input hold time relative to DQS t QHb TBD TBD 175 225 275 ps 7, 15, DQ…DQS hold, DQS to ﬁ rst DQ to go nonvalid, per access relative to DQS tDIPW TBD TBD 0.35 0.35 0.35 ps Data hold skew factor t QHS TBD TBD 340 400 450 DQ–DQS hold, DQS to ﬁ rst DQ to go nonvalid, per access tQH TBD TBD tHP- tQHS tHP- tQHS tHP- tQHS 15, 17 Data valid output window (DVW) t DVW TBD TBD tQH- tDQSQ tQH- tDQSQ tQH- tDQSQ 15, 17 Data Strobe DQS input high pulse width t DQSH TBD TBD 0.35 0.35 0.35 t CK DQS input low pulse width t DQSL TBD TBD 0.35 0.35 0.35 t CK DQS output access time from CK/CK# t DQSCK TBD TBD -400 +400 -450 +450 -500 +500 ps DQS falling edge to CK rising– setup time t DSS TBD TBD 0.2 0.2 0.2 t CK DQS falling edge from CK rising – hold time t DSH TBD TBD 0.2 0.2 0.2 t CK DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ TBD TBD 240 300 350 ps 15, 17 NOTE:

AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 AC TIMING PARAMETERS (Continued) 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Data Strobe DQS write preamble setup time tWPRES TBD TBD 0 0 0 ps 12, 13, DQS write preamble t WPRE TBD TBD 0.35 0.25 0.25 t CK Write command to ﬁ rst DQS latching transition tDQSS TBD TBD WL- 0.25 WL- 0.25 WL- 0.25 tCK Command and Address Address and control input pulse width for each input tIPW TBD TBD 0.6 0.6 0.6 t CK Address and control input setup time tISa TBD TBD 400 500 600 ps 6, 21 Address and control input hold time tIHa TBD TBD 400 500 600 ps 6, 21 Address and control input setup time tISb TBD TBD 200 250 350 ps 6, 21 Address and control input hold time tIHb TBD TBD 275 375 475 ps 6, 21 CAS# to CAS# command delay tCCD TBD TBD 222 t CK Active to Active (same bank) command tRC TBD TBD 55 55 55 ns 33 Active bank a to Active b bank command tRRD TBD TBD 7.5 7.5 7.5 ns 27 Active to Read or Write delay t RCD TBD TBD 15 15 15 ns Four Bank Activate period t FAW TBD TBD 37.5 37.5 37.5 ns 30 Active to precharge command t RAS TBD TBD 40 70,000 40 70,000 40 70,000 ns 20, 33 Internal Read to precharge command delay tRTP TBD TBD 7.5 7.5 7.5 ns 23, 27 Write recovery time t WR TBD TBD 15 15 15 ns 27 Auto precharge write recovery and precharge time tDAL TBD TBD tWR+tRP tWR+tRP tWR+tRP ns 22 Interval Write to Read command delay tWTR TBD TBD 10 7.5 10 ns 27 Precharge command period t RP TBD TBD 15 15 15 ns 31 Precharge All command period t RPA TBD TBD tRP+tCK tRP+tCK tRP+tCK ns 31 Load Mode command cycle time tMRD TBD TBD 222 t CK CKE low to CK,CK# uncertainty tDELAY TBD TBD tIS+tCK+tIH tIS+tCK+tIH tIS+tCK+tIH ns 28 NOTE:

AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 AC TIMING PARAMETERS (Continued) 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Self Refresh Refresh to Active or Refresh to Refresh command interval tRFC (2GB) TBD TBD 105 70,000 105 70,000 105 70,000 ns 14 tRFC (4GB) TBD TBD 127.5 70,000 127.5 70,000 127.5 70,000 ns 14 Average periodic refresh interval tREFI TBD TBD 200 7.8 7.8 7.8 µs 14 Exit self refresh to non-read command tXSNR TBD TBD tRFC (MIN)+10 tRFC (MIN)+10 tRFC (MIN)+10 ns Exit self refresh to read command tXSRD TBD TBD 200 200 200 t CK Exit self refresh timing reference tISXR TBD TBD tIS tIS tIS ps 6, 29 ODT ODT turn-on delay t AOND TBD TBD 222222 t CK ODT turn-on t AON TBD TBD tAC(MIN) tAC(MAX) +700 tAC(MIN) tAC(MAX) +1,000 tAC(MIN) tAC(MAX) +1,000 ps 25 ODT turn-off t AOF TBD TBD tAC(MIN) tAC(MAX) +600 tAC(MIN) tAC(MAX) +600 tAC(MIN) tAC(MAX) +600 ps 26 ODT turn-on (power-down mode) tAONPD TBD TBD tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 ps ODT turn-off (power-down mode) tAOFPD TBD TBD tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 tCK ODT to power-down entry latency tANPD TBD TBD 333 t CK ODT power-down exit latency t AXPD TBD TBD 888 t CK Power-Down Exit active power-down to READ command, MR[bit12=0] tXARD TBD TBD 222 t CK Exit active power-down to READ command, MR[bit12=1] tXARDS TBD TBD 7-AL 6-AL 6-AL t CK Exit precharge power-down to any non-READ command. tXP TBD TBD 222 t CK CKE minimum high/low time t CKE TBD TBD 333 t CK 34 NOTE:

AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 Notes 1. All voltages referenced to V SS 2. Tests for AC timing, I CC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related speciﬁ cations and device operation are guaranteed for the full voltage range speciﬁ ed. 3. Outputs measured with equivalent load: 4. AC timing and I CC tests may use a VIL to VIH swing of up to 1.0V in the test environment parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between V IL (AC) and VIH (AC). Slew derates less than 1.0V/ns require the timing parameters to be rated as speciﬁ ed. 5. The AC and DC input level speciﬁ cations are as deﬁ ned in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated using t ISb and the Setup and Hold Time Derating Values table. tIS timing (tISb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (AC) for a rising signal and VIL (DC) for a falling signal. The timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the “base” values. 7. Data minimum input slew rate is at 1.0V/ns. Data input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated if the timing is referenced from the logic trip points. t DS timing (tDSb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (DC) for a rising signal and VIL (DC) for a falling signal. The timing table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not enabled, timing is no longer referenced to the cross point of DQS/DQS#. Data timing is now referenced to V REF, provided the DQS slew rate is not less than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to V IH (AC) for a rising DQS and VIL (DC) for a falling DQS. 8. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (t HZ) or begins driving (tLZ). 9. This maximum value is derived from the referenced test load. t HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 10. t LZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition. 11. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low or Output (VOUT) Reference Point 25Ω VTT = VCCQ/2 High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above V IH DC (MIN) then it must not transition low (below VIH (DC) prior to tDQSH (MIN). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turn around. 13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 14. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. However, a REFRESH command must be asserted at least once every 70.3µs or t RFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms. 15. Each half-byte lane has a corresponding DQS. 16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured differentially). 17. The data valid window is derived by achieving other speciﬁ cations - t HP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. MIN (t CL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. This value can be greater than the minimum speciﬁ cation limits for t CL and tCH. For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. 19. t HP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. 20. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisﬁ ed since tRAS lockout feature is supported in DDR2 SDRAM devices. 21. V IL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb or 1Gb DDR2 SDRAM data sheet for more detail. 22. t DAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. 23. The minimum READ to internal PRECHARGE time. This parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1, then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has to be satisﬁ ed as well. The DDR2 SDRAM device will automatically delay the internal PRECHARGE command until t RAS (MIN) has been satisﬁ ed. 24. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 25. ODT turn-on time t AON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time t AON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 26. ODT turn-off time t AOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. 27. This parameter has a two clock minimum requirement at any t CK. 28. t DELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. 29. t ISXR is equal to tIS and is used for CKE setup time during self refresh exit. 30. No more than 4 bank ACTIVE commands may be issued in a given tFAW (MIN) period. tRRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. 31. t RPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, t RP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices. 32. Value is minimum pulse width, not the number of clock registrations. 33. Applicable to Read cycles only. Write cycles generally require additional time due to Write recovery time (tWR) during auto precharge. 34. t CKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of t IS + 2* tCK + tIH. 35. This parameter is not referenced to a speciﬁ c voltage level, but speciﬁ ed when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). 36. When DQS is used single-ended, the minimum limit is reduced by 100ps.

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 1.27 (0.050± -0.004) 4.06 (0.160) 133.35 (5.25) Front View Back View 4.00 (0.157) 3.00 (0.118) 18.29 (0.720) TYP 2.50 ± 0.20 (0.059 ± 0.004) 4.00 (0.157) 5.00 (0.196) 1.00 (0.039) 0.80 ± 0.05 (0.031 ± 0.002) PACKAGE DIMENSIONS FOR AD6 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) ORDERING INFORMATION FOR AD6 Part Number Speed/Data Rate CAS Latency t RCD tRP Height* W3HG2128M72ACER806AD6xG 400MHz/800Mb/s 6 6 6 18.29mm (0.72") TYP W3HG2128M72ACER665AD6xG 333MHz/667Mb/s 5 5 5 18.29mm (0.72") TYP W3HG2128M72ACER534AD6xG 266MHz/533Mb/s 4 4 4 18.29mm (0.72") TYP W3HG2128M72ACER403AD6xG 200MHz/400Mb/s 3 3 3 18.29mm (0.72") TYP ** Contact factory for availability NOTES:

RoHS compliant product. (G = RoHS Compliant)
Vendor speciﬁ c part numbers are used to provide memory component source control. The place holder for this is shown as a l ower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualiﬁ ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40°C to 85°C) option

12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 PART NUMBERING GUIDE W 3 H G 2 128M 72 A C E R xxx AD6 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x4 STACKED DIE BGA 1.8V REGISTERED SPEED (Mb/s) PACKAGE 240 PIN (.72) COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT

13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 Document Title 2GB – 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL,VLP

Revision History

Rev # History Release Date Status Rev 0 Evaluation and review July 2005 Concept Rev 1 1.1 Created concept data sheet December 2005 Concept Rev 2 2.1 Added ICC specs

2.2 Added AC specs

Rev 3 3.1 Moved to Preliminary January 2006 Preliminary Rev 4 4.0 Updated package outline

4.1 Added "stacked die" designation "C" to part number and

4.2 Added new capacitance numbers. February 2006 Preliminary Rev 5 5.1 Corrected package width dimension May 2006 Preliminary

Summary

2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP

Description