W3EG6432S265D3

W3EG6418S-D3 WEDC | Alldatasheet

Document overview

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Technical content

1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PRELIMINARY* White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. W3EG6418S-D3 -JD3 May 2005 Rev. 3 128MB – 16Mx64 DDR SDRAM UNBUFFERED

DESCRIPTION

The W3DG6418S is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM components. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualifi ed or characterized and is subject to change without notice.

FEATURES

/square6 Double-data-rate architecture /square6 DDR200 and DDR266

• JEDEC design specifi cations /square6 Bi-directional data strobes (DQS) /square6 Differential clock inputs (CK & CK#) /square6 Programmable Read Latency 2,2,5 (clock) /square6 Programmable Burst Length (2,4,8) /square6 Programmable Burst type (sequential & interleave) /square6 Edge aligned data output, center aligned data input /square6 Auto and self refresh /square6 Serial presence detect /square6 Power Supply: 2.5V ± 0.20V /square6 JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48mm (1.20") MAX NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option OPERATING FREQUENCIES DDR266 @CL=2 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 133MHz 133MHz 133MHz 100MHz

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. PIN CONFIGURATION PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V REF 47 NC 93 V SS 139 V SS

2 DQ0 48 A0 94 DQ4 140 NC

3V SS 49 NC 95 DQ5 141 A10

4 DQ1 50 V SS 96 V CCQ 142 NC

5 DQS0 51 NC 97 DQM0 143 V CCQ

6 DQ2 52 BA1 98 DQ6 144 NC

CC 53 DQ32 99 DQ7 145 V SS

8 DQ3 54 V CCQ 100 V SS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 NC 56 DQS4 102 NC 148 V CC

11 V SS 57 DQ34 103 NC 149 DQM4

12 DQ8 58 V SS 104 V CCQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 V SS

15 V CCQ 61 DQ40 107 DQM1 153 DQ44

16 CK1 62 V CCQ 108 V CC 154 RAS#

17 CK1# 63 WE# 109 DQ14 155 DQ45

18 V SS 64 DQ41 110 DQ15 156 V CCQ

19 DQ10 65 CAS# 111 NC 157 CS0#

20 DQ11 66 V

21 CKE0 67 DQS5 113 NC 159 DQM5

22 V CCQ 68 DQ42 114 DQ20 160 V SS

23 DQ16 69 DQ43 115 NC 161 DQ46

24 DQ17 70 V CC 116 V SS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 V SS 72 DQ48 118 A11 164 V CCQ

27 A9 73 DQ49 119 DQM2 165 DQ52

28 DQ18 74 V SS 120 V CC 166 DQ53

29 A7 75 CK2# 121 DQ22 167 NC

CCQ 76 CK2 122 A8 168 V CC

31 DQ19 77 V CCQ 123 DQ23 169 DQM6

32 A5 78 DQS6 124 V SS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

SS 80 DQ51 126 DQ28 172 V CCQ

35 DQ25 81 V SS 127 DQ29 173 NC

36 DQS3 82 V CCID 128 V CCQ 174 DQ60

37 A4 83 DQ56 129 DQM3 175 DQ61

CC 84 DQ57 130 A3 176 V SS

39 DQ26 85 V CC 131 DQ30 177 DQM7

40 DQ27 86 DQS7 132 V SS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

SS 88 DQ59 134 NC 180 V CCQ

43 A1 89 V SS 135 NC 181 SA0

44 NC 90 WP 136 V CCQ 182 SA1

45 NC 91 SDA 137 CK0 183 SA2

CC 92 SCL 138 CK0# 184 V CCSPD PIN NAMES A0-A11 Address input (Multiplexed) BA0-BA1 Bank Select Address DQ0-DQ63 Data Input/Output DQS0-DQS7 Data Strobe Input/Output CK0, CK1, CK2 Clock Input CK0#, CK1#, CK2# Clock Input CKE0 Clock Enable input CS0# Chip Select Input RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable DQM0-DQM7 Data-in-mask V CC Power Supply VCCQ Power Supply for DQS VSS Ground VREF Power Supply for Reference VCCSPD Serial EEPROM Power Supply SDA Serial data I/O SCL Serial clock SA0-SA2 Address in EEPROM V CCID VCC Indentifi cation Flag NC No Connect

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. FUNCTIONAL BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS# CS# CS# CS# CS# CS# CS# CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS DQS DQS DQS DQS DQS DQS CS0# DQS0 DQM0 DQS1 DQM1 DQS2 DQM2 DQS3 DQM3 DQS4 DQM4 DQS5 DQM5 DQS3 DQM3 DQS1 DQM1 RAS# CAS# BA0-BA1 WE# A0-A11 CKE0 RAS#: DDR SDRAMs CAS#: DDR SDRAMs BA0-BA1: DDR SDRAMs WE#: DDR SDRAMs A0-A11: DDR SDRAMs CKE0: DDR SDRAMs VCCSPD VCCQ VCC VREF VSS SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs SERIAL PD SCL WP SDA SA0 SA1 SA2 A0 A1 A2 CK0, CK0# CK1, CK1# CK2, CK2#

2 SDRAMs

3 SDRAMs

NOTE: All resistor values are 22 ohms unless otherwise specifi ed

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V Storage Temperature T STG -55 to +150 °C Power Dissipation P D 8W Short Circuit Current I OS 50 mA Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliabilityDC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7 V Supply Voltage V CCQ 2.3 2.7 V Reference Voltage V REF 1.15 1.35 V Termination Voltage V TT 1.15 1.35 V Input High Voltage V IH VREF + 0.15 V CCQ + 0.3 V Input Low Voltage V IL -0.3 V REF -0.15 V Output High Voltage V OH VTT + 0.76 — V Output Low Voltage V OL —V TT-0.76 V CAPACITANCE TA = 25°C. f = 1MHz, VCC = 2.5V ± 0.2V Parameter Symbol Max Unit Input Capacitance (A0-A11) C IN1 26 pF Input Capacitance (RAS#,CAS#,WE#) C IN2 26 pF Input Capacitance (CKE0, CKE1) C IN3 26 pF Input Capacitance (CK0#,CK0) C IN4 26 pF Input Capacitance (CS0#, CS1#) C IN5 26 pF Input Capacitance (DQM0-DQM8) C IN6 8p F Input Capacitance (BA0-BA1) C IN7 26 pF Data input/output capacitance (DQ0-DQ63)(DQS) C OUT 8p F

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR266@CL=2 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1000 880 880 mA Operating Current I DD1 One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 1080 960 960 mA Precharge Power- Down Standby Current I DD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 24 24 24 mA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. V IN = VREF for DQ, DQS and DM. 360 360 360 mA Active Power- Down Standby Current I DD3P One device bank active; Power-Down mode; t CK (MIN); CKE=(low) 200 200 200 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active- Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 400 400 400 mA Operating Current I DD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; T CK= TCK (MIN); lOUT = 0mA. 1120 1040 1040 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 1120 1000 1000 mA Auto Refresh Current IDD5 tRC = tRC (MIN) 2120 1760 1760 mA Self Refresh Current IDD6 CKE ≤ 0.2V 24 24 24 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 2840 2640 2640 mA * Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. IDD1 : OPERATING CURRENT : ONE BANK 1. Typical Case : V CC=2.5V, T=25°C 2. Worst Case : V CC=2.7V, T=10°C 3. Only one bank is accessed with t RC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. I OUT = 0mA 4. Timing Patterns :

• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : t CK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : V CC=2.5V, T=25°C 2. Worst Case : V CC=2.7V, T=10°C 3. Four banks are being interleaved with t RC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : t CK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics 262 263/265 202 Parameter Symbol Min Max Min Max Min Max Units Notes CL=2 t CK (2) 7.5 13 7.5 13 10 13 ns 22 DQ and DM input hold time relative to DQS t DH 0.5 0.5 0.5 ns 14,17 DQ and DM input setup time relative to DQS t DS 0.5 0.5 0.5 ns 14,17 DQ and DM input pulse width (for each input) t DIPW 1.75 1.75 1.75 ns 17 DQS input high pulse width t DQSH 0.35 0.35 0.35 t CK DQS input low pulse width t DQSL 0.35 0.35 0.35 t CK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.5 0.5 ns 13,14 DQS falling edge to CK rising - setup time t DSS 0.2 0.2 0.2 t CK DQS falling edge from CK rising - hold time t DSH 0.2 0.2 0.2 t CK Half clock period t HP tCH, tCL tCH, tCL tCH, tCL ns 18 Data-out high-impedance window from CK, CK# t HZ +0.75 +0.75 +0.75 ns 8,19 Data-out low-impedance window from CK, CK# t LZ -0.75 -0.75 -0.75 ns 8,20 Address and control input hold time (fast slew rate) t IHf 0.90 0.90 0.90 ns 6 Address and control input set-up time (fast slew rate) t ISf 0.90 0.90 0.90 ns 6 Address and control input hold time (slow slew rate) t IHs 111 n s 6 Address and control input setup time (slow slew rate) t ISs 111 n s 6 Address and control input pulse width (for each input) t IPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time t MRD 15 15 15 ns DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access t QH tHP-tQHS tHP-tQHS tHP- tQHS ns 13,14 Data hold skew factor t QHS 0.75 0.75 0.75 ns ACTIVE to PRECHARGE command t RAS 40 120,000 40 120,000 40 120,000 ns 15 ACTIVE to READ with Auto precharge command t RAP 15 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 60 65 65 ns AUTO REFRESH command period t RFC 75 75 75 ns 21

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC Characteristics 262 263/265 202 Parameter Symbol Min Max Min Max Min Max Units Notes ACTIVE to READ or WRITE delay t RCD 15 20 20 ns PRECHARGE command period t RP 15 20 20 ns ACTIVE bank a to ACTIVE bank b command t RRD 15 15 15 ns DQS write preamble t WPRE 0.25 0.25 0.25 t CK DQS write preamble setup time t WPRES 0 0 0 ns 10,11 Write recovery time t WR 15 15 15 ns Internal WRITE to READ command delay t WTR 111 t CK Data valid output window NA t QH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns 13 REFRESH to REFRESH command interval t REFC 140.6 140.6 140.6 μs 12 Average periodic refresh interval t REFI 15.6 15.6 15.6 μs 12 Terminating voltage delay to VCC tVTD 000 n s Exit SELF REFRESH to non-READ command t XSNR 75 75 75 ns Exit SELF REFRESH to READ command t XSRD 200 200 200 t CK

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 12. The refresh period is 64ms. This equates to an average refresh rate of 15.625µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 13. The valid data window is derived by achieving other specifi cations - t HP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 14. Referenced to each output group: x8 = DQS with DQ0-DQ7. 15. R EADs and WRITEs with auto precharge are not allowed to be issued until t RAS (MIN) can be satisfi ed prior to the internal precharge command being issued. 16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). 17. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. 18. t HP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. 19. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may refl ect up to 310ps less for t HZ (MAX) and last DVW. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. 20. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. 21. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 22. W henever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). Notes 1. All voltages referenced to V SS 2. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifi cations and device operations are guaranteed for the full voltage range specifi ed. 3. Outputs are measured with equivalent load: 4. AC timing and I DD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifi cations are defi ned in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). 6. Command/Address input slew rate = 0.5V/ns. For 262 with slew rates 1V/ns and faster, t IS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. t IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 7. Inputs are not recognized as valid until V REF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. 8. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). 9. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 10. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 11. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on t DQSS. OutputOutput (V(VOUTOUT) Reference Reference PointPoint 5050Ω VTTTT 30pF30pF

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 133.48 (5.255" MAX.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) MAX 2.31 (0.091) (2x) 1.27 (0.050 TYP.)6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100 MAX) 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050 ± 0.004) PACKAGE DIMENSIONS FOR JD3 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) ORDERING INFORMATION FOR JD3 Part Number Speed CAS Latency t RCD tRP Height* Temperature W3EG6432S262JD3 133MHz/266Mb/s 2 2 2 30.48 (1.20") 0°C to 70°C W3EG6432S263JD3 133MHz/266Mb/s 2 3 3 30.48 (1.20") 0°C to 70°C W3EG6432S265JD3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") 0°C to 70°C W3EG6432S202JD3 100MHz/200Mb/s 2 2 2 30.48 (1.20") 0°C to 70°C NOTE:

• Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lo wer case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 133.48 (5.255" MAX.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) MAX 2.31 (0.091) (2x) 1.27 (0.050 TYP.)6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100 MAX) 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050 ± 0.004) PACKAGE DIMENSIONS FOR D3 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) ORDERING INFORMATION FOR D3 Part Number Speed CAS Latency t RCD tRP Height* Temperature W3EG6432S262D3 133MHz/266Mb/s 2 2 2 30.48 (1.20") 0°C to 70°C W3EG6432S263D3 133MHz/266Mb/s 2 3 3 30.48 (1.20") 0°C to 70°C W3EG6432S265D3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") 0°C to 70°C W3EG6432S202D3 100MHz/200Mb/s 2 2 2 30.48 (1.20") 0°C to 70°C NOTE:

• Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lo wer case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option

12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6418S-D3 -JD3 May 2005 Rev. 3 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. Document Title 128MB – 16Mx64, DDR SDRAM UNBUFFERED

Revision History

Rev # History Release Date Status Rev A Created 9-4-02 Advanced Rev 0 0.1 Removed "ED from part number

0.2 Added document title page

0.3 Moved from Advanced to Preliminary

Rev 1 1.1 Updated I DD and CAP specs

1.2 Added new AC specs

Rev 2 2.1 Added lead-free and RoHS notes 12-04 Preliminary Rev 3 3.1 Added JEDEC standard PCB

3.2 D3 option "NOT RECOMMENDED FOR NEW DESIGNS"