W3EG128M72ETSU262AJD3

W3EG128M72ETSU-D3 WEDC | Alldatasheet

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1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.comJanuary 2005 Rev. 0 W3EG128M72ETSU-D3 -JD3 -AJD3 ADVANCED* 1GB – 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

FEATURES

/square6 Double-data-rate architecture /square6 DDR200, DDR266, DDR333 and DDR400

• JEDEC design specifi cation /square6 Bi-directional data strobes (DQS) /square6 Differential clock inputs (CK & CK#) /square6 Programmable Read Latency 2,2.5 (clock) /square6 Programmable Burst Length (2,4,8) /square6 Programmable Burst type (sequential & interleave) /square6 Edge aligned data output, center aligned data input /square6 Auto and self refresh /square6 Serial presence detect /square6 Power supply:
• V CC = VCCQ = +2.5V ± 0.2V (100, 133 and 166MHz)
• V CC = VCCQ = +2.6V ± 0.1V (200MHz) /square6 JEDEC standard 184 pin DIMM package
• Package height options: NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option

DESCRIPTION

The W3EG128M72ETSU is a 128Mx72 Double Data Rate SDRAM memory module based on 1Gb DDR SDRAM components. The module consists of nine 128Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * This product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice. OPERATING FREQUENCIES DDR400@CL=3 DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2 Clock Speed 200MHz 166MHz 133MHz 133MHz 100MHz

-JD3 -AJD3 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED PIN CONFIGURATION PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 1V REF 47 DQS8 93 V SS 139 V SS

2 DQ0 48 A0 94 DQ4 140 DQS17

3V SS 49 CB2 95 DQ5 141 A10

4 DQ1 50 V SS 96 V CCQ 142 CB6

5 DQS0 51 CB3 97 DQS9 143 V CCQ

6 DQ2 52 BA1 98 DQ6 144 CB7

7V CC 53 DQ32 99 DQ7 145 V SS 8D Q 3 5 4 V CCQ 100 V SS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 RESET# 56 DQS4 102 NC 148 V CC

11 V SS 57 DQ34 103 NC 149 DQS13

12 DQ8 58 V SS 104 V CCQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 V

15 V CCQ 61 DQ40 107 DQS10 153 DQ44

16 NC 62 V CCQ 108 V CC 154 RAS#

17 NC 63 WE# 109 DQ14 155 DQ45

18 V SS 64 DQ41 110 DQ15 156 V CCQ

19 DQ10 65 CAS# 111 CKE1 157 CS0#

20 DQ11 66 V

SS 112 V CCQ 158 CS1#

21 CKE0 67 DQS5 113 NC 159 DQS14

22 V CCQ 68 DQ42 114 DQ20 160 V SS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 V CC 116 V SS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

SS 72 DQ48 118 A11 164 V CCQ

27 A9 73 DQ49 119 DQS11 165 DQ52

28 DQ18 74 V

29 A7 75 NC 121 DQ22 167 NC

31 DQ19 77 V CCQ 123 DQ23 169 DQS15

32 A5 78 DQS6 124 V SS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

SS 80 DQ51 126 DQ28 172 V CCQ

35 DQ25 81 V SS 127 DQ29 173 NC

36 DQS3 82 V CCID 128 V CCQ 174 DQ60

37 A4 83 DQ56 129 DQS12 175 DQ61

38 V CC 84 DQ57 130 A3 176 V SS

39 DQ26 85 V CC 131 DQ30 177 DQS16

40 DQ27 86 DQS7 132 V SS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

SS 88 DQ59 134 CB4 180 V CCQ

43 A1 89 V SS 135 CB5 181 SA0

44 CB0 90 NC 136 V CCQ 182 SA1

45 CB1 91 SDA 137 CK0 183 SA2

CC 92 SCL 138 CK0# 184 V CCSPD PIN NAMES A0-A12 Address input (Multiplexed) BA0-BA1 Bank Select Address DQ0-DQ63 Data Input/Output CB0-CB7 Check bits DQS0-DQS17 Data Strobe Input/Output CK0 Clock Input CK0# Clock input CKE0, CKE1 Clock Enable input CS0#, CS1# Chip Select Input RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable V CC Power Supply VCCQ Power Supply for DQS VSS Ground VREF Power Supply for Reference VCCSPD Serial EEPROM Power Supply SDA Serial data I/O SCL Serial clock SA0-SA2 Address in EEPROM V CCID VCC Indentifi cation Flag NC No Connect RESET# Reset Enable

-JD3 -AJD3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED FUNCTIONAL BLOCK DIAGRAM BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs WE#: DDR SDRAMs DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM0 S0# DM CS# DQS DM CS# DQS DM CS# DQS DQS0 DM4 DQS4 DM1 DQS1 DM5 DQS5 DM2 DQS2 DM6 DQS6 DM CS# DQS DM CS# DQS DM CS# DQ DM CS# DQ DM CS# DQS DM3 DQS3 DM7 DQS7 DM8 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VCCSPD VCC VREF VSS SPD/EEPROM DDR SDRAMS DDR SDRAMS DDR SDRAMS DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ SA0 SERIAL PD SDA SA1 SA2 WP SCL CK0A# CK0 CK0A PLL FREQ_SEL VCC CK0# DDR SDRAM 120 CK0 CK0# 120 DDR SDRAM CK1 CK1# DDR SDRAM 120 CK2 CK2# DDR SDRAM 120 NOTE: All resistor values are 22 ohms unless otherwise specifi ed

-JD3 -AJD3 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT – 0.5 ~ 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ –1.0 ~ 3.6 V Storage Temperature T STG – 55 ~ +150 °C Power Dissipation P D 9W Short Circuit Current I OS 50 mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz) Parameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7 V Supply Voltage V CCQ 2.3 2.7 V Reference Voltage V REF 1.15 1.35 V Termination Voltage V TT 1.15 1.35 V Input High Voltage V IH VREF + 0.15 V CCQ + 0.3 V Input Low Voltage V IL – 0.3 V REF – 0.15 V Output High Voltage V OH VTT + 0.76 — V Output Low Voltage V OL —V TT – 0.76 V CAPACITANCE TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V (100, 133 and 166MHz), VCCQ = 2.6V ± 0.1V (200MHz) Parameter Symbol Max Unit Input Capacitance (A0-A12) C IN1 29 pF Input Capacitance (RAS#,CAS#,WE#) C IN2 29 pF Input Capacitance (CKE0,CKE1) C IN3 29 pF Input Capacitance (CK0,CK0#) C IN4 5.5 pF Input Capacitance (CS0#,CS1#) C IN5 29 pF Input Capacitance (DQM0-DQM8) C IN6 8p F Input Capacitance (BA0-BA1) C IN7 29 pF Data input/output Capacitance (DQ0-DQ63)(DQS) C OUT 8p F Data input/output Capacitance (CB0-CB7) C OUT 8p F

-JD3 -AJD3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz) Parameter Symbol Conditions DDR400@ CL=3 DDR333@ CL=2.5 DDR266@ CL=2, 2.5 DDR200@ CL=2 UnitsMax Max Max Max Operating Current I DD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. T RC=TRC(MIN); TCK=TCK TBD TBD TBD TBD mA Operating Current I DD1 One device bank; Active- Read-Precharge; Burst = 2; T RC=TRC(MIN);TCK=TCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. TBD TBD TBD TBD mA Precharge Power- Down Standby Current I DD2P All device banks idle; Power-down mode; TCK=TCK(MIN); CKE=(low) TBD TBD TBD TBD mA Idle Standby Current I DD2F CS# = High; All device banks idle; TCK=TCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. V IN = VREF for DQ, DQS and DM. TBD TBD TBD TBD mA Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; TCK(MIN); CKE=(low) TBD TBD TBD TBD mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; T RC=TRAS(MAX); TCK=TCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. TBD TBD TBD TBD mA Operating Current I DD4R Burst = 2; Reads; Continous burst; One device bank active;Address andcontrol inputs changing once per clock cycle; T CK=TCK(MIN); IOUT = 0mA. TBD TBD TBD TBD mA Operating Current I DD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; T CK=TCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. TBD TBD TBD TBD mA Auto Refresh Current I DD5 TRC=TRC(MIN) TBD TBD TBD TBD mA Self Refresh Current I DD6 CKE ≤ 0.2V TBD TBD TBD TBD mA Operating Current I DD7A Four bank interleaving Reads (BL=4) with auto precharge with TRC=TRC (MIN); TCK=TCK(MIN); Address and control inputs change only during Active Read or Write commands TBD TBD TBD TBD mA

-JD3 -AJD3 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED IDD1 : OPERATING CURRENT : ONE BANK 1. Typical Case : V CC=2.5V, T=25°C 2. Worst Case : V CC=2.7V, T=10°C 3. Only one bank is accessed with t RC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. I OUT = 0mA 4. Timing Patterns :

• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : t CK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : t CK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
• DDR400 (200MHz, CL=3) : t CK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : V CC=2.5V, T=25°C 2. Worst Case : V CC=2.7V, T=10°C 3. Four banks are being interleaved with t RC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : t CK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : t CK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
• DDR400 (200MHz, CL=3) : t CK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3

-JD3 -AJD3 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V AC CHARACTERISTICS 403 335 262 265 202 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES Clock cycle time CL = 3 t CK (3) 5 7.5 6 13 7.5 13 7.5 13 8 13 ns 38, 43 CL = 2 t CK (2) 7.5 13 ns 37, 42 DQ and DM input hold time relative to DQS t DH 0.4 0.45 0.5 0.6 ns 22, 26 DQ and DM input setup time relative to DQS t DS 0.4 0.45 0.5 0.6 ns 22, 26 DQ and DM input pulse width (for each input) t DIPW 1.75 1.75 1.75 2 ns 26 DQS input high pulse width t DQSH 0.35 0.35 0.35 0.35 t CK DQS input low pulse width t DQSL 0.35 0.35 0.35 0.35 t CK DQS-DQ skew, DQS to last DQ valid, per group, per access Half clock period t HP tCH,tCL tCH,tCL tCH,tCL tCH,tCL tCH,tCL ns 29 Address and control input hold time (0.5 V/ns) t IHS 0.6 0.80 1 1 1.1 ns 12 Address and control input setup time (0.5 V/ns) t ISS 0.6 0.80 1 1 1.1 ns 12 LOAD MODE REGISTER command cycle time t MRD 2 1 21 51 51 6n s DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS tHP - tQHS tHP - tQHS ns 22 Data hold skew factor t QHS 0.50 0.60 0.75 0.75 1 ns ACTIVE to PRECHARGE command t RAS 40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns 30 ACTIVE to READ with Auto precharge command t RAP 15 15 15 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 55 60 60 65 70 ns AUTO REFRESH command period t RFC 70 72 75 72 75 ns 41 ACTIVE to READ or WRITE delay t RCD 15 15 15 20 20 ns PRECHARGE command period t RP 15 15 15 20 20 ns ACTIVE bank a to ACTIVE bank b command t RRD 10 12 15 15 15 ns DQS write preamble setup time t WPRES 00000 n s 1 7 , 1 9

-JD3 -AJD3 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) DDR400: VCC = VCCQ = +2.6V ± 0.1V AC CHARACTERISTICS 403 355 262 265 202 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES Write recovery time t WR 15 15 15 15 15 ns Internal WRITE to READ command delay t WTR 21111 t CK Data valid output window na t QH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 22 Terminating voltage delay to VCC tVTD 00000 n s Exit SELF REFRESH to non-READ command t XSNR 75 75 75 75 80 ns Exit SELF REFRESH to READ command t XSRD 200 200 200 200 200 t CK

-JD3 -AJD3 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED Notes 1. All voltages referenced to V SS. 2. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifi cations and device operation are guaranteed for the full voltage range specifi ed. 3. Outputs measured with equivalent load: OutputOutput (V(VOUTOUT) Reference Reference PointPoint 50Ω50Ω VTTTT 30pF30pF 4. AC timing and I DD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between V IL (AC) and VIH (AC). 5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF bypass capacitor. 7. V TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. I DD is dependent on output loading and cycle rates. Specifi ed values are obtained with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and CL = 3 for 403 with the outputs open. 9. Enables on-chip refresh and address counters. 10. I DD specifi cations are tested after the device is properly initialized, and is averaged at the defi ned cycle rate. f = 100 MHz, TA = 25°C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, refl ecting the fact that they are matched in loading. 12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For 403, slew rates must be 0.5 V/ns. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V REF. 14. Inputs are not recognized as valid until V REF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 16. t HZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion of the postamble is the DQS- driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high [above V IHDC (MIN)] then it must not transition low (below VIHDC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 20. MIN (t RC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be as-serted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The data valid window is derived by achieving other specifi cations: t HP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (t RFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, V IL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC). 26. JEDEC specifi es CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to t DS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns. 28. V CC must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfi ed prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V mini-mum, whichever is more positive.

-JD3 -AJD3 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED 33. The voltage levels used are derived from a mini-mum V CC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide signifi cantly different voltage values. 34. V IH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. V CC and VCCQ must track each other. 36. t HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 37. t RPST end point and tRPRE begin point are not referenced to a specifi c voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 38. During initialization, V CCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0V, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. 39. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not refl ect this option. 40. Random addressing changing and 50 percent of data changing at every transfer. 41. Random addressing changing and 100 percent of data changing at every transfer. 42. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 43. I DD2N specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifi es the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 44. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 45. Leakage number refl ects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or LOW. 47. The 403 speed grade will operate with t RAS (MIN) = 40 ns and tRAS (MAX) = 120,000ns at any slower frequency.

-JD3 -AJD3 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) PACKAGE DIMENSIONS FOR JD3 ORDERING INFORMATION FOR JD3 Part Number Speed Height* Commercial Operating Range W3EG128M72ETSU403JD3 200MHz/400Mbps, CL=3 30.48 (1.20") 0°C to 70°C W3EG128M72ETSU335JD3 166MHz/333Mbps, CL=2.5 30.48 (1.20") 0°C to 70°C W3EG128M72ETSU262JD3 133MHz/266Mbps, CL=2 30.48 (1.20") 0°C to 70°C W3EG128M72ETSU265JD3 133MHz/266Mbps, CL=2.5 30.48 (1.20") 0°C to 70°C W3EG128M72ETSU202JD3 100MHz/200Mbps, CL=2 30.48 (1.20") 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specifi c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a specifi c component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options 133.48 (5.255" MAX.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.0 (0.394) 6.36 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20 MAX) 2.31 (0.091) (2x) 1.27 (0.050 TYP.)6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050) (± 0.004) 2.54 (0.100 MAX)

-JD3 -AJD3 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED PACKAGE DIMENSIONS FOR AJD3 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) ORDERING INFORMATION FOR AJD3 Part Number Speed Height* Commercial Operating Range W3EG128M72ETSU403AJD3 200MHz/400Mbps, CL=3 28.70 (1.13") MAX 0°C to 70°C W3EG128M72ETSU335AJD3 166MHz/333Mbps, CL=2.5 28.70 (1.13") MAX 0°C to 70°C W3EG128M72ETSU262AJD3 133MHz/266Mbps, CL=2 28.70 (1.13") MAX 0°C to 70°C W3EG128M72ETSU265AJD3 133MHz/266Mbps, CL=2.5 28.70 (1.13") MAX 0°C to 70°C W3EG128M72ETSU202AJD3 100MHz/200Mbps, CL=2 28.70 (1.13") MAX 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specifi c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a specifi c component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options 133.48 (5.255" MAX.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.0 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 28.70 (1.13 MAX) 2.31 (0.091) (2x) 1.27 (0.050 TYP.)6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050) (± 0.004) 2.54 (0.100 MAX)

-JD3 -AJD3 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED PACKAGE DIMENSIONS FOR D3 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) ORDERING INFORMATION FOR D3 Part Number Speed Height* Commercial Operating Range W3EG128M72ETSU403D3 200MHz/400Mbps, CL=3 28.58 (1.125") MAX 0°C to 70°C W3EG128M72ETSU335D3 166MHz/333Mbps, CL=2.5 28.58 (1.125") MAX 0°C to 70°C W3EG128M72ETSU262D3 133MHz/266Mbps, CL=2 28.58 (1.125") MAX 0°C to 70°C W3EG128M72ETSU265D3 133MHz/266Mbps, CL=2.5 28.58 (1.125") MAX 0°C to 70°C W3EG128M72ETSU202D3 100MHz/200Mbps, CL=2 28.58 (1.125") MAX 0°C to 70°C NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specifi c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a specifi c component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options NOT RECOMMENDED Note: D3 Not Recommended For New Designs 133.48 (5.255" MAX.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.0 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 28.58 (1.125 MAX) 2.31 (0.091) (2x) 1.27 (0.050 TYP.)6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 3.99 (0.157) (MIN) 1.27 ± 0.10 (0.050) (± 0.004) 2.54 (0.100 MAX)

-JD3 -AJD3 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 ADVANCED Document Title 1GB – 128Mx72, DDR, SDRAM Unbuffered ECC, w/PLL

Revision History

Rev # History Release Date Status Rev 0 Created 1-04-05 Advanced