W3E64M72S-250ESM

W3E64M72S-XBX WEDC | Alldatasheet

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ADVANCED* 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 64Mx72 DDR SDRAM

FEATURES

/square6 Data rate = 200, 250, 266 and 333Mbs /square6 Package:

• 219 Plastic Ball Grid Array (PBGA), 25 x 32mm /square6 2.5V ±0.2V core power supply /square6 2.5V I/O (SSTL_2 compatible) /square6 Differential clock in puts (CK and CK#) /square6 Commands entered on each positive CK edge /square6 Internal pipelined double-data-rate (DDR) ar chi tec ture; two data accesses per clock cy cle /square6 Programmable Burst length: 2,4 or 8 /square6 Bidirectional data strobe (DQS) transmitted/ re ceived with data, i.e., source-syn chro nous data capture (one per byte) /square6 DQS edge-aligned with data for READs; center- aligned with data for WRITEs /square6 DLL to align DQ and DQS transitions with CK /square6 Four internal banks for concurrent operation /square6 Data mask (DM) pins for masking write data (one per byte) /square6 Programmable IOL/IOH option /square6 Auto precharge option /square6 Auto Refresh and Self Refresh Modes /square6 Commercial, Industrial and Military TemperatureRang es /square6 Organized as 64M x 72 /square6 Weight: W3E64M72S-XBX - 4.5 grams typical * This product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice. BENEFITS /square6 66% Space Savings vs. TSOP /square6 Re duced part count /square6 55% I/O reduction vs TSOP /square6 Reduced trace lengths for lower parasitic capacitance /square6 Suitable for hi-reliability applications /square6 Laminate interposer for optimum TCE match GENERAL DESCRIPTION The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS, dy nam ic ran dom-access, memory using 9 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 512MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate ar chi tec ture is essentially a 2n-prefetch architecture with an in ter face designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two cor re spond ing n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 512MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com mands (ad dress and control signals) are registered at every positive edge of CK. Input data is registered on both edg es of DQS, and out put data is ref er enced to both edges of DQS, as well as to both edges of CK.

2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DENSITY COMPARISONS Read and write accesses to the DDR SDRAM are burst ori ent ed; accesses start at a selected location and continue for a pro grammed number of locations in a programmed sequence. Accesses begin with the registration of an AC TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The ad dress bits registered coincident with the READ or WRITE com mand are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge func tion may be enabled to provide a self- timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAMs al lows for concurrent operation, thereby providing high ef fec tive band width by hiding row precharge and activation time. An auto refresh mode is provided, along with a power- saving power-down mode. All inputs are compatible with the Jedec Standard for SSTL_2. All full drive options outputs are SSTL_2, Class II compatible. FUNCTIONAL DE SCRIP TION Read and write accesses to the DDR SDRAM are burst ori ent ed; accesses start at a selected location and continue for a pro grammed number of locations in a pro grammed se quence. Ac cess es begin with the registration of an AC TIVE com mand which is then followed by a READ or WRITE com mand. The address bits registered coincident with the AC TIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE com mand are used to select the start ing column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information cov er ing device initialization, register defi nition, command de scrip tions and de vice operation. Discrete Approach SAVINGS – Area: 66% – I/O Count: 55% Area = 800mm2 Area: 9 x 265mm2 = 2,385mm2 I/O Count = 219 Balls I/O Count: 9 x 54 pins = 486 pins 22.3 54 TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP ACTUAL SIZE White Electronic Designs W3E64M72S-XBX

3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. FIGURE 1 – PIN CONFIGURATION NOTE: DNU = Do Not Use. Top View 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A B C D E F G H J K L M N P R T DQ1 DQ3 DQ6 DQ7 CAS0# CS0# V SS VSS CLK3# NC DQ56 DQ57 DQ60 DQ62 V SS VSS DQ30 DQ28 DQ25 DQ24 CLK1 CKE1 V CC VCC CS2# CAS2# DQ39 DQ38 DQ35 DQ33 V CC DQ0 DQ2 DQ4 DQ5 DQML0 WE0# RAS0# V SS VSS CKE3 CLK3 DQMH3 DQ58 DQ59 DQ61 DQ63 DQ31 DQ29 DQ27 DQ26 NC DQMH1 CLK1# V CCQ VCCQ RAS2# WE2# DQML2 DQ37 DQ36 DQ34 DQ32 DQ14 DQ12 DQ10 DQ8 V CC VCC VCC VCC VCC VCC VCC VCC DQ55 DQ53 DQ51 DQ49 DQ17 DQ19 DQ21 DQ23 V SS VSS VSS Vss VSS VSS VSS VSS DQ40 DQ42 DQ44 DQ46 DQ15 DQ13 DQ11 DQ9 DQMH0 CLK0 CKE0 V CCQ VCCQ CS3# CAS3# WE3# DQ54 DQ52 DQ50 DQ48 DQ16 DQ18 DQ20 DQ22 DQML1 WE1# CS1# V SS VSS CKE2 CLK2 DQMH2 DQ41 DQ43 DQ45 DQ47 V SS VSS VCC VCCQ DQSH3 DQSL3 CLK0# VSS VSS DQSL4 RAS3# DQML3 NC VSS VCC VCCQ VCCQ VCC VSS VSS VREF RAS1# CAS1# V CC VCC CLK2# DQSL2 CS4# DQSH2 VCC VSS VSS A12 DQSH0 NC NC NC NC NC DNU DQSL1 WE4# DQ70 DQ68 DQ66 DQ64 A10 DNU BA0 CLK4 NC NC NC NC A11 DNU BA1 CAS4# DQ71 DQ69 DQ67 DQ65 V SS VSS VCC VCCQ DQSL0 CKE4 CLK4# VSS VCC VCCQ VCCQ VCC VSS VSS DQSH1 RAS4# DQML4 VCC VSS VSS

4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM A0-12 A0-12 BA0-1 BA0-1 CK0# CK# DQ0 DQ7 CKE0 CKE DQML0 DQML DQ0 DQ7 IC1 A0-12 BA0-1 CK1# CK# CK DQ16 DQ23 DQ0 DQ7 IC0 CKE1 CKE DQML1 DQM DQ0 DQ7 IC2 A0-12 BA0-1 CK2# CK# DQ32 DQ39 CKE2 CKE DQML2 DQM DQ0 DQ7 IC3 A0-12 BA0-1 CK3# CK# DQ48 DQ55 CKE3 CKE DQML3 DQM DQ0 DQ7 IC4 A0-12 BA0-1 CK4# CK# DQ64 DQ71 CKE4 CKE DQML4 DQM DQSL4 DQS CS0# CK0# CKE0 DQMH0 CS0#CS# RAS0# WE0# CAS0# WE# RAS# CAS# CS1# CS# CK1# CK# CKE1 CKE DQMH1 DQM DQSL1 DQS DQSH1 DQS CS1#C S # RAS1# WE1# CAS1# WE# RAS# CAS# CS2# CS# CK2# CK# CKE2 CKE DQMH2 DQM CS2# CS# RAS2# WE2# CAS2# WE# RAS# CAS# CS3# CS# CK3# CK# CKE3 CKE DQMH3 DQM DQSL2 DQS DQSL3 DQS DQSH2 DQS DQSH3 DQS CS3# CS# RAS3# WE3# CAS3# WE# RAS# CAS# CS4# CS# RAS4# WE4# CAS4# WE# RAS# CAS# A0-12 BA0-1 CK# CK0 CK CK1 CK2 CK CK3 CK CK4 CK CK0 CK1 CK CK2 CK CK3 CK CK DQ8 DQ15 CKE DQM DQSL0 DQS DQSH0 DQS DQ0 DQ7 IC6 A0-12 BA0-1 DQ24 DQ31 DQ0 DQ7 IC5 DQ0 DQ7 IC7 A0-12 BA0-1 DQ40 DQ47 DQ0 DQ7 IC8 A0-12 BA0-1 DQ56 DQ63 CS# WE# RAS# CAS# WE# RAS# CAS# WE# RAS# CAS# WE# RAS# CAS#

5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. INITIALIZATION DDR SDRAMs must be powered up and initialized in a pre defi ned manner. Operational procedures other than those specifi ed may result in undefi ned operation. Power must fi rst be applied to V CC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after V CCQ to avoid device latch-up, which may cause per ma nent dam age to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after V CC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power- up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read ac cess). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable com mand. Once the 200µs delay has been satisfi ed, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REG IS TER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the D LL, fol lowed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the D LL and to program the operating parameters. Two-hundred clock cy cles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (t RFC must be satisfi ed.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating pa ram e ters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal op er a tion. REGISTER DEFINITION MODE REGISTER The Mode Register is used to defi ne the specifi c mode of op er a tion of the DDR SDRAM. This defi nition includes the selection of a burst length, a burst type, a CAS latency, and an op er at ing mode, as shown in Figure 3. The Mode Reg is ter is programmed via the MODE REG IS TER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored in for ma tion until it is pro grammed again or the device loses power. (Ex cept for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Reg is ter must be load ed (reloaded) when all banks are idle and no bursts are in progress, and the con trol ler must wait the spec i fi ed time be fore ini ti at ing the sub se quent op er a tion. Vi o lat ing either of these re quire ments will result in un spec i fi ed operation. Mode register bits A0-A2 specify the burst length, A3 spec i fi es the type of burst (sequential or in ter leaved), A4-A6 spec i fy the CAS latency, and A7-A12 specify the op er at ing mode. BURST LENGTH Read and write ac cess es to the DDR SDRAM are burst ori ent ed, with the burst length being programmable, as shown in Fig ure 3. The burst length determines the maximum num ber of column lo ca tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 lo ca tions are avail able for both the sequential and the in ter leaved burst types. Reserved states should not be used, as unknown op er a tion or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of col umns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most signifi cant column address for a given confi guration); and by A3-Ai when the burst length is set to eight. The remaining (least sig nifi cant) ad dress bit(s) is (are) used to select the starting lo ca tion within the block. The pro grammed burst length ap plies to both READ and WRITE bursts.

6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. BURST TYPE Accesses within a given burst may be pro grammed to be either se quen tial or interleaved; this is re ferred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is de ter mined by the burst length, the burst type and the start ing column address, as shown in Table 1. READ LATENCY The READ latency is the delay, in clock cycles, between the reg is tra tion of a READ command and the avail abil i ty of the fi rst bit of output data. The latency can be set to 2, 2.5, or 3 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the op er at ing fre quen cies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not re quired, JEDEC specifi cations recommend when a LOAD MODE REG IS TER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to se lect nor mal op er at ing mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifi ed time before initiating any sub se quent operation. Violating either of these requirements could result in unspecifi ed operation. TABLE 2 – CAS LATENCY ALLOWABLE OPERATING FREQUENCY (MHz) SPEED CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3 -200 ≤ 75 ≤ 100 — -250 ≤ 100 ≤ 125 — -266 ≤ 100 ≤ 133 — -333* ≤ 100 ≤ 133/≤ 166 ≤ 166 * For 333Mbs operation of Industrial and commercial temperatures CL = 2.5, at Military temperature CL = 3. OUTPUT DRIVE STRENGTH The normal full drive strength for all outputs are specifi ed to be SSTL2, Class II. DLL ENABLE/DISABLE When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power- up initialization and upon re turn ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur be fore a READ command can be issued.

7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. COMMANDS The Truth Table provides a quick reference of available com mands. This is followed by a written de scrip tion of each command. DESELECT The DESELECT function (CS# High) prevents new com mands from be ing ex e cut ed by the DDR SDRAM. The SDRAM is ef fec tive ly de se lect ed. Op er a tions already in progress are not af fect ed. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW while RAS#, CAS#, and WE# are high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable com mand cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs se lects the bank, and the address pro vid ed on inputs A0-12 selects the row. This row remains active (or open) for ac cess es until a PRECHARGE com mand is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9, 11 se lects the starting column location. The value on input A10 de ter mines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent ac cess es. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9, 11 se lects the starting column location. The value on input A10 de ter mines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for sub se quent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic level ap pear ing co in ci dent with the data. If a given DQM signal is reg is tered LOW, the cor re spond ing data will be written to mem o ry; if the DQM signal is reg is tered HIGH, the cor re spond ing data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specifi ed time (t RP) after the PRECHARGE command is is sued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing pa ram e ters. Input A10 de ter mines wheth er one or all banks are to be precharged, and in the case where only one bank is to be precharged, in puts BA0, BA1 select the bank. Oth er wise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be ac ti vat ed pri or to any READ or WRITE commands being is sued to that bank. A PRECHARGE com mand will be treat ed as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the pro cess of precharging. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same in di vid u al-bank PRECHARGE function de scribed above, but with out re quir ing an explicit command. This is ac com plished by using A10 to enable AUTO PRECHARGE in conjunction with a spe cifi c READ or WRITE command. A precharge of the bank/row that is ad dressed with the READ or WRITE com mand is au to mat i cal ly performed upon com ple tion of the READ or WRITE burst. AUTO

8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. TABLE 1 – BURST DEFINITION Burst Length Starting Column Address Order of Accesses With in a Burst Type = Sequential Type = In ter leaved 0 0-1 0-1 1 1-0 1-0 A1 A0 A2 A1 A0 NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. FIGURE 3 – MODE REGISTER DEFINITION M3 = 0 Reserved Reserved Reserved M3 = 1 Reserved Reserved Reserved Reserved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

00 V a l i d

2.5 Reserved Burst Length Burst LengthCAS Latency BT A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus M6-M0M8 M7 Operating Mode A10A11 * M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register). 0*0* BA0BA1 Reserved Reserved Reserved Reserved M9M10M11 000 10000 ----- - A12 M12 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRECHARGE is non per sis tent in that it is either en abled or dis abled for each in di vid u al READ or WRITE command. The device sup ports concurrent auto precharge if the com mand to the oth er bank does not in ter rupt the data transfer to the current bank. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit precharge command was is sued at the earliest possible time, without violating t RAS (MIN).The user must not is sue an oth er com mand to the same bank until the precharge time (tRP) is com plet ed. BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open. AUTO REFRESH AUTO REFRESH is used during normal op er a tion of the DDR SDRAM and is analogous to CAS-BEFORE-RAS (CBR) RE FRESH in con ven tion al DRAMs. This com mand is non per sis tent, so it must be issued each time a refresh is required. All banks must be idle before an AUTO REFRESH command is issued. The addressing is generated by the internal refresh con trol ler. This makes the address bits “Don’t Care”

9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. COMMAND READ NOP NOP NOP CL = 2.5 DON'T CARETRANSITIONING DATA DQ DQS T0 T1 T2 T2n T3 T3n COMMAND READ NOP NOP NOP CL = 2 DQ DQS CLK CLK# T0 T1 T2 T2n T3 T3n Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA CLK CLK# FIGURE 4 – CAS LATENCY FIGURE 5 – EXTENDED MODE REGISTER DEFINITION DLL Enable Disable A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended Mode Register (Ex) Address BusA10A11 1101 BA0BA1 Drive Strength Normal Reserved Operating Mode Reserved Reserved E1, E0 Valid E12 E10 A12 E11 1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFC# function is not supported. 1 4 1 3 1 2 1 1 1 0 9 876543210 DLLDSOperating Mode during an AUTO RE FRESH command. Each DDR SDRAM requires AUTO RE FRESH cycles at an average interval of 7.8125µs (maximum). To allow for improved efficiency in scheduling and switch ing between tasks, some fl exibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, mean ing that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in t AC between updates. Although not a JEDEC requirement, to provide for future func tion al ity features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends t RFC later. SELF REFRESH* The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM re tains data with out external clocking. The SELF RE FRESH com mand is ini ti at ed like an AUTO REFRESH com mand except CKE is dis abled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then oc cur before a READ command can be issued). Input sig nals except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands is sued for t XSNR, be cause time is required for the com ple tion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL re quire ments is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only.

10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 defi ne the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-9, 11 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” TRUTH TABLE – COMMANDS (NOTE 1) NAME (FUNCTION) CS# RAS# CAS# WE# ADDR DESELECT (NOP) (9) H X X X X NO OPERATION (NOP) (9) L H H H X ACTIVE (Select bank and activate row) ( 3) L L H H Bank/Row READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col BURST TERMINATE (8) L H H L X PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X LOAD MODE REGISTER (2) L L L L Op-Code TRUTH TABLE – DM OPERATION NAME (FUNCTION) DM DQs WRITE ENABLE (10) L Valid WRITE INHIBIT (10) H X 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefi ned (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data.

11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS Parameter Unit Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V Voltage on I/O pins relative to Vss -0.5V to V CCQ +0.5V V Operating Temperature TA (Mil) -55 to +125 °C Operating Temperature TA (Ind) -40 to +85 °C Operating Temperature TA (Com) -0 to +70 °C Storage Temperature, Plastic -55 to +125 °C Maximum Junction Temperature 125 °C NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this specifi cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability. CAPACITANCE (NOTE 13) Parameter Symbol Max Unit Input Capacitance: CK/CK# C I1 TBD pF Addresses, BA0-1 Input Capacitance CA TBD pF Input Capacitance: All other input-only pins C I2 TBD pF Input/Output Capacitance: I/Os C IO TBD pF BGA THERMAL RESISTANCE Description Symbol Max Units Notes Junction to Ambient (No Airfl ow) Theta JA TBD °C/W 1 Junction to Ball Theta JB TBD °C/W 1 Junction to Case (Top) Theta JC TBD °C/W 1 Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.wedc.com in the application notes section for modeling conditions.

12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16) VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Parameter/Condition Symbol Min Max Units Supply Voltage (36, 41) V CC 2.3 2.7 V I/O Supply Voltage (36, 41, 44) V CCQ 2.3 2.7 V Input Leakage Current: Any one input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -2 2 µA Input Leakage Address Current (All other pins not under test = 0V) II -18 18 µA Output Leakage Current: I/Os are disabled; 0V ≤ V OUT ≤ VCCQ IOZ -5 5 µA Output Levels: Full drive option (37, 39) High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOH - 1 2-m A IOL 12 - mA I/O Reference Voltage (6,44) V REF 0.49 x VCCQ 0.51 x VCCQ V I/O Termination Voltage (7, 44) V TT VREF - 0.04 V REF + 0.04 V AC INPUT OPERATING CONDITIONS VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Parameter/Condition Symbol Min Max Units Input High (Logic 1) Voltage V IH V REF +0.500 — V Input Low (Logic 0) Voltage V IL —V REF -0.500 V

13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. Parameter/Condition MAX Symbol 333Mbs 250Mbs/ 266Mbs 200Mbs Units OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 47) I CC0 1,170 1,170 1,035 mA OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 47) ICC1 1,440 1,440 1,305 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 49) ICC2P 45 45 45 mA IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50) ICC2F 405 405 360 mA ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 49) ICC3P 315 315 270 mA ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22) ICC3N 450 450 405 mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 47) ICC4R 1,485 1,485 1,305 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22) ICC4W 1,755 1,440 1,215 mA AUTO REFRESH CURRENT t REFC = tRC (MIN) (49) I CC5 2,610 2,610 2,520 mA tREFC = 7.8125µs (27, 49) I CC5A 90 90 90 mA SELF REFRESH CURRENT: CKE 0.2V Standard (11) I CC6 45 45 45 mA OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 48) ICC7 3,645 3,645 3,510 mA ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46) VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C

14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS Notes 1-5, 14-17, 33 333 Mbs CL3/CL2.5 (53) 266 Mbs CL2.5 266 Mbs CL2.5

200 CL2

250 Mbs CL2.5

200 Mbs CL2

200 Mbs CL2.5

150 Mbs CL2

Parameter Symbol Min Max Min Max Min Max Min Max Units Clock cycle time CL = 3 (45, 51) t CK (3) 6 13 ns CL = 2.5 (45, 51) t CK (2.5) 7.5 13 7.5 13 8 13 10 13 ns CL = 2 (45, 51) t CK ( 2 ) 1 01 31 01 31 01 31 31 5n s DQ and DM input hold time relative to DQS (26, 31) t DH 0.45 0.5 0.6 0.6 ns DQ and DM input setup time relative to DQS (26, 31) t DS 0.45 0.5 0.6 0.6 ns DQ and DM input pulse width (for each input) (31) t DIPW 1.75 1.75 2 2 ns DQS input high pulse width t DQSH 0.35 0.35 0.35 0.35 t CK DQS input low pulse width t DQSL 0.35 0.35 0.35 0.35 t CK DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) t DQSQ 0.45 0.5 0.6 0.6 ns DQS falling edge to CK rising - setup time t DSS 0.2 0.2 0.2 0.2 t CK DQS falling edge from CK rising - hold time t DSH 0.2 0.2 0.2 0.2 t CK Half clock period (34) t HP tCH,tCL tCH,tCL tCH,tCL tCH,tCL ns Data-out high-impedance window from CK/CK# (18, 42) t HZ +0.70 +0.75 +0.8 +0.8 ns Data-out low-impedance window from CK/CK# (18, 42) t LZ -0.70 -0.75 -0.8 -0.8 ns Address and control input hold time (fast slew rate) t IHF 0.75 0.90 1.1 1.1 ns Address and control input setup time (fast slew rate) t ISF 0.75 0.90 1.1 1.1 ns Address and control input hold time (slow slew rate) (14) t IHS 0.8 1 1.1 1.1 ns Address and control input setup time (slow slew rate) (14) t ISS 0.8 1 1.1 1.1 ns LOAD MODE REGISTER command cycle time t MRD 12 15 16 16 ns DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access (25, 26) t QH tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS ns Data hold skew factor t QHS 0.55 0.75 1 1 ns ACTIVE to PRECHARGE command (35) t RAS 42 70,000 40 120,000 40 120,000 40 120,000 ns ACTIVE to READ with Auto precharge command t RAP 15 20 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 60 65 70 70 ns AUTO REFRESH command period (49) t RFC 72 75 80 80 ns ACTIVE to READ or WRITE delay t RCD 15 20 20 20 ns PRECHARGE command period t RP 15 20 20 20 ns ACTIVE bank a to ACTIVE bank b command t RRD 12 15 15 15 ns DQS write preamble t WPRE 0.25 0.25 0.25 0.25 t CK DQS write preamble setup time (20, 21) t WPRES 0000 n s Write recovery time t WR 15 15 15 15 ns Internal WRITE to READ command delay t WTR 1111 t CK Data valid output window (25) na t QH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns REFRESH to REFRESH command interval (23) (Commercial & Industrial only) t REFC 70.3 70.3 70.3 70.3 µs REFRESH to REFRESH command interval (23) (Military temperature only)* t REFC 35 35 35 35.15 µs Average periodic refresh interval (23) (Commercial & Industrial only) t REFI 7.8 7.8 7.8 7.8 µs Average periodic refresh interval (23) (Military temperature only)* t REFI 3.9 3.9 3.9 3.9 µs Terminating voltage delay to VDD t VTD 0000 n s Exit SELF REFRESH to non-READ command t XSNR 75 75 80 80 ns Exit SELF REFRESH to READ command t XSRD 200 200 200 200 t CK * Self refresh available in commercial and industrial temperatures only.

15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, I CC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifi cations and device operation are guaranteed for the full voltage range specifi ed. 3. Outputs measured with equivalent load: 4. AC timing and I CC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF by-pass capacitor. 7. V TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. V ID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of V IX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. 10. I CC is dependent on output loading and cycle rates. Specifi ed values are obtained with minimum cycle time with the outputs open. 11. Enables on-chip refresh and address counters. 12. I CC specifi cations are tested after the device is properly initialized, and is averaged at the defi ned cycle rate. 13. This parameter is not tested but guaranteed by design. t A = 25°C, F= 1 MHz 14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK# and CK# cross; the input reference level for signals other than CK/CK# is V REF. 16. Inputs are not recognized as valid until V REF stabilizes. Once initialized, including SELF REFRESH mode, VREF must be powered within specifi ed range. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The intent of the Don't Care state after completion of the postamble is the DQS- driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above V IHDC(MIN) then it must not transition low (below VIHDC) prior to tDQSH(MIN). 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 22. MIN (t RC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. (32ms for Military grade) This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifi cations - t HP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8- DQ15 of each chip. 160 140 120 100 VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum 50Ω Output (VOUT) VTT FIGURE A FULL DRIVE PULL-DOWN CHARACTERISTICS FIGURE B FULL DRIVE PULL-UP CHARACTERISTICS -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 VCCQ - VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum

16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, V IL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be ≤ 1V/ns (≤2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. V CC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfi ed prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. The average cannot be below the 2.5V minimum. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. NA 39. The voltage levels used are derived from a minimum V CC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide signifi cantly different voltage values. 40. V IH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. 41. V CC and VCCQ must track each other. 42. t HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. t RPST end point and tRPRE begin point are not referenced to a specifi c voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, V CCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not refl ect this option. 46. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH or LOW. 47. Random addressing changing: 50% of data changing at every transfer. 48. Random addressing changing: 100% of data changing at every transfer. 49. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t RFC has been satisfi ed. 50. I CC2N specifi es the DQ, DQS, and DQM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifi es the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.” 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV. 53. For 333Mbs operation of Industrial and commercial temperatures CL = 2.5, at Military temperature CL = 3.

17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES BOTTOM VIEW PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA) 32.1 (1.264) MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A 25.1 (0.988) MAX 19.05 (0.750) NOM 1.27 (0.050) NOM 19.05 (0.750) NOM 2.96 (0.116) MAX 0.61 (0.024) NOM219 x Ø 0.762 (0.030) NOM

18 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

ORDERING INFORMATION

WHITE ELECTRONIC DESIGNS CORP. DDR SDRAM CONFIGURATION, 64M x 72 2.5V Power Supply DATA RATE (Mbs) 200 = 200Mbs 250 = 250Mbs 266 = 266Mbs 333 = 333Mbs PACKAGE: ES = Non Qualifi ed Product (1) B = 219 Plastic Ball Grid Array (PBGA) DEVICE GRADE: M = Military -55°C to +125°C I = In dus tri al -40°C to +85°C C = Com mer cial 0°C to +70°C W 3E 64M 72 S - XXX B X Note 1: W3E64M72S-ESB is the only available product until completion of qualifi cation.

19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifi cations without notice. Document Title 64M x 72 DDR SDRAM 219 PBGA Multi-Chip Package

Revision History

Rev # History Release Date Status Rev 0 Initial Release June 2005 Advanced