W3E32M64S-XBX WEDC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333Mb/s Package:
- 219 Plastic Ball Grid Array (PBGA), 25mm x 25mm, 625mm2 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock in puts (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) ar chi tec ture; two data accesses per clock cy cle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ re ceived with data, i.e., source-syn chro nous data capture (one per byte) DQS edge-aligned with data for READs; center- aligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable I OL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRang es Organized as 32M x 64 User con fi gurable as 2x32Mx32 or 4x32Mx16 Pinout compatible with previous W3E16M64S-XBX version. Weight: W3E32M64S-XBX - 2.5 grams typical * This product subject to change without notice. BENEFITS 41% SPACE SAVINGS vs. TSOP Re duced part count Re duced trace lengths for low er par a sit ic ca pac i tance Suit able for hi-re li abil i ty ap pli ca tions Lam i nate in ter pos er for op ti mum TCE match GENERAL DESCRIPTION The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dy nam ic ran dom-access, memory using 4 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate ar chi tec ture is essentially a 2n-prefetch architecture with an in ter face designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two cor re spond ing n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge- aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 256MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com mands (ad dress and control signals) are registered at every positive edge of CK. Input data is registered on both edg es of DQS, and out put data is ref er enced to both
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 Area 4 x 265mm 2 = 1060mm2 625mm2 41% S A V I N G S Actual Size W3E32M64S-XBX White Electronic Designs W3E32M64S-XBX TSOP Approach (mm) 22.3 11.9 TSOP TSOP TSOP TSOP 11.9 11.9 11.9 DENSITY COMPARISONS edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst ori ent ed; accesses start at a selected location and continue for a pro grammed number of locations in a programmed sequence. Accesses begin with the registration of an AC TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The ad dress bits registered coincident with the READ or WRITE com mand are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge func tion may be enabled to provide a self- timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAMs al lows for concurrent operation, thereby providing high ef fec tive band width by hiding row precharge and activation time. An auto refresh mode is provided, along with a power- saving power-down mode. FUNCTIONAL DE SCRIP TION Read and write accesses to the DDR SDRAM are burst ori ent ed; accesses start at a selected location and continue for a pro grammed number of locations in a pro grammed se quence. Ac cess es begin with the registration of an AC TIVE com mand which is then followed by a READ or WRITE com mand. The address bits registered coincident with the AC TIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE com mand are used to select the start ing column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information cov er ing device initialization, register defi nition, command de scrip tions and de vice operation. INITIALIZATION DDR SDRAMs must be powered up and initialized in a pre defi ned manner. Operational procedures other than those specifi ed may result in undefi ned operation. Power must fi rst be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after V CCQ to avoid device latch-up, which may cause per ma nent dam age to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 FIGURE 1 – PIN CONFIGURATION Top View 1 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A B C D E F G H J K L M N P R T DQ15 DQ0 DQ14 DQ1 CAS0# CS0# VSS VSS CLK3# NC DQ49 DQ62 DQ48 DQ63 V SS VSS DQ31 DQ16 DQ30 DQ17 CLK1 CKE1 V CC VCC CS2# CAS2# DQ33 DQ46 DQ32 DQ47 V CC DQ13 DQ2 DQ12 DQ3 DQML0 WE0# RAS0# VSS VSS CKE3 CLK3 DQMH3 DQ50 DQ60 DQ51 DQ61 DQ29 DQ18 DQ28 DQ19 NC DQMH1 CLK1# V CCQ VCCQ RAS2# WE2# DQML2 DQ35 DQ44 DQ34 DQ45 DQ11 DQ4 DQ10 DQ5 V CC VCC VCC VCC VCC VCC VCC VCC DQ52 DQ57 DQ53 DQ59 DQ27 DQ20 DQ26 DQ21 V SS VSS VSS Vss VSS VSS VSS VSS DQ38 DQ42 DQ36 DQ43 DQ9 DQ6 DQ8 DQ7 DQMH0 CLK0 CKE0 V CCQ VCCQ CS3# CAS3# WE3# DQ54 DQ56 DQ55 DQ58 DQ25 DQ22 DQ24 DQ23 DQML1 WE1# CS1# V SS VSS CKE2 CLK2 DQMH2 DQ39 DQ41 DQ37 DQ40 V SS VSS VCC VCCQ DQSH3 DQSL3 CLK0# VSS VSS NC RAS3# DQML3 NC VSS VCC VCCQ VCCQ VCC VSS VSS VREF RAS1# CAS1# V CC VCC CLK2# DQSL2 NC DQSH2 VCC VSS VSS A12 DQSH0 NC NC NC NC NC DNU DQSL1 NC NC NC NC NC A10 DNU BA0 NC NC NC NC NC A11 DNU BA1 NC NC NC NC NC V SS VSS VCC VCCQ DQSL0 NC NC VSS VCC VCCQ VCCQ VCC VSS VSS DQSH1 NC NC VCC VSS VSS NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. NC = Not Connected Internally.
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 RAS0# WE0# CAS0# WE# RAS# CAS# CLK0# CLK# CS0# CS# RAS1# WE1# CAS1# WE# RAS# CAS# CLK1# CLK# CS1# CS# A0-12 A0-12 BA0-1 BA0-1 DQ0 DQ15 CKE0 CKE DQML0 DQML DQMH0 DQMH DQ0 DQ15 A0-12 BA0-1 DQ16 DQ31 DQ0 DQ15 CKE1 CKE DQML1 DQML DQMH1 DQMH DQ0 DQ15 A0-12 BA0-1 DQ32 DQ47 CKE2 CKE RAS2# WE2# CAS2# WE# RAS# CAS# CLK2# CLK# CS2# CS# DQML2 DQML DQMH2 DQMH RAS3# WE3# CAS3# DQ0 DQ15 WE# RAS# A0-12 BA0-1 CLK3# CLK# CAS# DQ48 DQ63 CKE3 CKE CS3# CS# DQSL3 DQSL DQSH3 DQSH CLK3 CLK VREF DQSL2 DQSL DQSH2 DQSH VREF DQSL1 DQSL DQSH1 DQSH VREF DQSL0 DQSL DQSH0 DQSH CLK2 CLK CLK1 CLK CLK0 CLK VREF DQML3 DQML DQMH3 DQMH FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an L VCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read ac cess). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable com mand. Once the 200µs delay has been satis fi ed, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REG IS TER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, fol lowed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cy cles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (t RFC must be satisfi ed.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating pa ram e ters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal op er a tion.
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 REGISTER DEFINITION MODE REGISTER The Mode Register is used to defi ne the specifi c mode of op er a tion of the DDR SDRAM. This defi nition includes the selection of a burst length, a burst type, a CAS latency, and an op er at ing mode, as shown in Figure 3. The Mode Reg is ter is programmed via the MODE REG IS TER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored in for ma tion until it is pro grammed again or the device loses power. (Ex cept for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Reg is ter must be load ed (reloaded) when all banks are idle and no bursts are in progress, and the con trol ler must wait the spec i fi ed time be fore ini ti at ing the sub se quent op er a tion. Vi o lat ing either of these re quire ments will result in un spec i fi ed operation. Mode register bits A0-A2 specify the burst length, A3 spec i fi es the type of burst (sequential or in ter leaved), A4-A6 spec i fy the CAS latency, and A7-A12 specify the op er at ing mode. BURST LENGTH Read and write ac cess es to the DDR SDRAM are burst ori ent ed, with the burst length being programmable, as shown in Fig ure 3. The burst length determines the maximum num ber of column lo ca tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 lo ca tions are avail able for both the sequential and the in ter leaved burst types. Reserved states should not be used, as unknown op er a tion or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of col umns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most signifi cant column address for a given con fi guration); and by A3-Ai when the burst length is set to eight. The remaining (least sig nifi cant) ad dress bit(s) is (are) used to select the starting lo ca tion within the block. The pro grammed burst length ap plies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst may be pro grammed to be either se quen tial or interleaved; this is re ferred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is de ter mined by the burst length, the burst type and the start ing column address, as shown in Table 1. READ LATENCY The READ latency is the delay, in clock cycles, between the reg is tra tion of a READ command and the avail abil i ty of the fi rst bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the op er at ing fre quen cies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not re quired, JEDEC specifi cations recommend when a LOAD MODE REG IS TER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to se lect nor mal op er at ing mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength,
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 and QFC. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. TABLE 2 – CAS LATENCY ALLOWABLE OPERATING FREQUENCY (MHz) Data Rate CAS LATENCY = 2 CAS LATENCY = 2.5 -200 ≤ 75 ≤ 100 -250 ≤ 100 ≤ 125 -266 ≤ 100 ≤ 133 -333 - ≤ 166 The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the speci fi ed time before initiating any sub se quent operation. Violating either of these requirements could result in unspecifi ed operation. OUTPUT DRIVE STRENGTH The normal full drive strength for all outputs are specifi ed to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. DLL ENABLE/DISABLE When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power- up initialization and upon re turn ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur be fore a READ command can be issued. COMMANDS The Truth Table provides a quick reference of available com mands. This is followed by a written de scrip tion of each command. DESELECT The DESELECT function (CS# High) prevents new com mands from be ing ex e cut ed by the DDR SDRAM. The SDRAM is ef fec tive ly de se lect ed. Op er a tions already in progress are not af fect ed. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW while RAS#, CAS#, and WE# are high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable com mand cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs se lects the bank, and the address pro vid ed on inputs A0-12 selects the row. This row remains active (or open) for ac cess es until a PRECHARGE com mand is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 se lects the starting column location. The value on input A10 de ter mines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent ac cess es.
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 TABLE 1 – BURST DEFINITION NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. FIGURE 3 – MODE REGISTER DEFINITION M3 = 0 Reserved Reserved Reserved M3 = 1 Reserved Reserved Reserved Reserved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
00 V a l i d
2.5 Reserved Burst Length Burst LengthCAS Latency BT A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus M6-M0M8 M7 Operating Mode A10A11 * M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register). 0*0* BA0BA1 Reserved Reserved Reserved Reserved M9M10M11 000 10000 ----- - A12 M12 WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 se lects the starting column location. The value on input A10 de ter mines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for sub se quent accesses. Input data appearing on the D/Qs is written to the memory array subject to the DQM input logic level ap pear ing co in ci dent with the data. If a given DQM signal is reg is tered LOW, the cor re spond ing data will be written to mem o ry; if the DQM signal is reg is tered HIGH, the cor re spond ing data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specifi ed time (tRP) after the PRECHARGE command is is sued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = In ter leaved 0 0-1 0-1 1 1-0 1-0 A1 A0 A2 A1 A0
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 COMMAND READ NOP NOP NOP CL = 2.5 DON'T CARETRANSITIONING DATA DQ DQS T0 T1 T2 T2n T3 T3n COMMAND READ NOP NOP NOP CL = 2 DQ DQS CLK CLK T0 T1 T2 T2n T3 T3n Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA CLK CLK FIGURE 4 – CAS LATENCY FIGURE 5 – EXTENDED MODE REGISTER DEFINITION DLL Enable Disable DLLDS A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus Operating Mode A10A11 1101 BA0BA1 Drive Strength Normal Reduced Operating Mode Reserved Reserved E1, E0 Valid E12 E10 A12 E11 1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFC function is not supported. allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing pa ram e ters. Input A10 de ter mines wheth er one or all banks are to be precharged, and in the case where only one bank is to be precharged, in puts BA0, BA1 select the bank. Oth er wise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be ac ti vat ed pri or to any READ or WRITE commands being is sued to that bank. A PRECHARGE com mand will be treat ed as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the pro cess of precharging. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same in di vid u al-bank PRECHARGE function de scribed above, but with out re quir ing an explicit command. This is ac com plished by using A10 to enable AUTO PRECHARGE in conjunction with a spe cifi c READ or WRITE command. A precharge of the bank/row that is ad dressed with the READ or WRITE com mand is au to mat i cal ly performed upon com ple tion of the READ or WRITE burst. AUTO PRECHARGE is non persistent in that it is either en abled or dis abled for each in di vid u al READ or WRITE command. The device sup ports concurrent auto precharge if the com mand to the oth er bank does not in ter rupt the data transfer to the current bank. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit precharge command was is sued at the earliest possible time, without violating t RAS (MIN).The user must not is sue an oth er com mand to the same bank until the precharge time (tRP) is com plet ed. BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open.
9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 AUTO REFRESH AUTO REFRESH is used during normal op er a tion of the DDR SDRAM and is analogous to CAS-BEFORE-RAS (CBR) RE FRESH in con ven tion al DRAMs. This com mand is non persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh con trol ler. This makes the address bits “Don’t Care” during an AUTO RE FRESH command. Each DDR SDRAM requires AUTO RE FRESH cycles at an average interval of 7.8125µs (maximum). To allow for improved efficiency in scheduling and switch ing between tasks, some fl exibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, mean ing that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in t AC between updates. Although not a JEDEC requirement, to provide for future func tion al ity features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends t RFC later. SELF REFRESH* The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM re tains data with out external clocking. The SELF TRUTH TABLE – COMMANDS (NOTE 1) NAME (FUNCTION) CS# RAS# CAS# WE# ADDR DESELECT (NOP) (9) H X X X X NO OPERATION (NOP) (9) L H H H X ACTIVE (Select bank and activate row) (3) L L H H Bank/Row READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col BURST TERMINATE (8) L H H L X PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X LOAD MODE REGISTER (2) L L L L Op-Code NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 de fi ne the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is unde fi ned (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. TRUTH TABLE – DM OPERATION NAME (FUNCTION) DM DQs WRITE ENABLE (10) L Valid WRITE INHIBIT (10) H X
10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 RE FRESH com mand is ini ti at ed like an AUTO REFRESH com mand except CKE is dis abled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then oc cur before a READ command can be issued). Input sig nals except CKE are “Don’t Care” during SELF REFRESH. V REF voltage is also required for the full duration of SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior ABSOLUTE MAXIMUM RATINGS Parameter Unit Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V Voltage on I/O pins relative to VSS -1 to 3.6 V Operating Temperature TA (Mil) -55 to +125 °C Operating Temperature TA (Ind) -40 to +85 °C Storage Temperature, Plastic -55 to +125 °C NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this specifi cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability. CAPACITANCE (NOTE 13) Parameter Symbol Max Unit Input Capacitance: CLK CI1 8 pF Addresses, BA0-1 Input Capacitance CA 22 pF Input Capacitance: All other input-only pins CI2 10 pF Input/Output Capacitance: I/Os CIO 10 pF BGA THERMAL RESISTANCE Description Symbol Max Units Notes Junction to Ambient (No Airfl ow) Theta JA 14.1 °C/W 1 Junction to Ball Theta JB 10.0 °C/W 1 Junction to Case (Top) Theta JC 5.2 °C/W 1 NOTE 1: Refer to "PBGA Thermal Resistance Correlation" Application Note at www.wedc.com in the application notes section for modeling conditions. to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands is sued for t XSNR, be cause time is required for the com ple tion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL re quire ments is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only.
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 Parameter/Condition Symbol Min Max Units Supply Voltage V CC 2.3 2.7 V I/O Supply Voltage V CCQ 2.3 2.7 V Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) I I -2 2 µA Input Leakage Address Current (All other pins not under test = 0V) I I -8 8 µA Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC I OZ -5 5 µA Output Levels: Full drive option High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOH -16.8 – mA IOL 16.8 – mA Output Levels: Reduced drive option High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) IOHR -9 – mA IOLR 9– m A I/O Reference Voltage V REF 0.49 x VCCQ 0.51 x VCCQ V I/O Termination Voltage V TT VREF - 0.04 V REF + 0.04 V ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14) Parameter/Condition Symbol MAX 333Mbs 250Mbs 266Mbs 200Mbs Units OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; (22, 48) ICC0 520 520 460 mA OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 48) ICC1 640 640 580 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50) ICC2P 20 20 20 mA IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51) ICC2F 180 180 160 mA ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50) ICC3P 140 140 120 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22) I CC3N 200 200 180 mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48) ICC4R 660 660 580 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22) ICC4W 975 800 540 mA AUTO REFRESH CURRENT t REF = tRC (MIN) (27, 50) I CC5 1,160 1,160 1,120 mA tREF = 7.8125µs (27, 50) I CC5A 40 40 40 mA SELF REFRESH CURRENT: CKE ≤ 0.2V Standard (11) I CC6 20 20 20 mA OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49) ICC7 2,025 1,620 1,400 mA AC INPUT OPERATING CONDITIONS VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C Parameter/Condition Symbol Min Max Units Input High (Logic 1) Voltage VIH VREF + 0.5 - V Input Low (Logic 0) Voltage VIL -V REF - 0.5 V
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 Parameter Symbol 333 Mbs CL 2.5 266 Mbs CL 2.5
200 CL 2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
UnitsMin Max Min Max Min Max Clock cycle time CL = 2.5 (45, 52) t CK (2.5) 7.5 13 7.5 13 8 13 10 13 ns CL = 2 (45, 52) t CK (2) 10 13 10 13 10 13 13 15 ns DQ and DM input hold time relative to DQS (26, 31) t DH 0.45 0.5 0.6 0.6 ns DQ and DM input setup time relative to DQS (26, 31) t DS 0.45 0.5 0.6 0.6 ns DQ and DM input pulse width (for each input) (31) t DIPW 1.75 1.75 2 2 ns DQS input high pulse width t DQSH 0.35 0.35 0.35 0.35 t CK DQS input low pulse width t DQSL 0.35 0.35 0.35 0.35 t CK DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) t DQSQ 0.45 0.5 0.6 0.6 ns DQS falling edge to CLK rising - setup time t DSS 0.2 0.2 0.2 0.2 t CK DQS falling edge from CLK rising - hold time t DSH 0.2 0.2 0.2 0.2 t CK Half clock period (34) t HP tCH, tCL tCH, tCL tCH, tCL tCH, tCL ns Data-out high-impedance window from CLK/CLK# (18, 42) t HZ +0.70 +0.75 +0.8 +0.8 ns Data-out low-impedance window from CLK/CLK# (18, 43) t LZ -0.7 -0.75 -0.8 -0.8 ns Address and control input hold time (fast slew rate) (14) t IHF 0.75 0.90 1.1 1.1 ns Address and control input setup time (fast slew rate) (14) t ISF 0.75 0.90 1.1 1.1 ns Address and control input hold time (slow slew rate) (14) t IHS 0.8 1 1.1 1.1 ns Address and control input setup time (slow slew rate) (14) t ISS 0.8 1 1.1 1.1 ns LOAD MODE REGISTER command cycle time t MRD 12 15 16 16 ns DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access (25, 26) t QH tHP - tQHS tHP - tQHS tHP - tQHS tHP - tQHS ns Data hold skew factor t QHS 0.55 0.75 1 1 ns ACTIVE to PRECHARGE command (35) t RAS 42 70,000 40 120,000 40 120,000 40 120,000 ns ACTIVE to READ with Auto precharge command (46) t RAP 15 20 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 60 65 70 70 ns AUTO REFRESH command period (50) t RFC 72 75 80 80 ns ACTIVE to READ or WRITE delay t RCD 15 20 20 20 ns PRECHARGE command period t RP 15 20 20 20 ns ACTIVE bank a to ACTIVE bank b command t RRD 12 15 15 15 ns DQS write preamble t WPRE 0.25 0.25 0.25 0.25 t CK DQS write preamble setup time (20, 21) t WPRES 0000n s Write recovery time t WR 15 15 15 15 ns Internal WRITE to READ command delay t WTR 1111 t CK Data valid output window (25) na t QH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns REFRESH to REFRESH command interval (23) t REFC 70.3 70.3 70.3 70.3 µs Average periodic refresh interval (23) t REFI 7.8 7.8 7.8 7.8 µs Terminating voltage delay to VCC (53) t VTD 0000n s Exit SELF REFRESH to non-READ command t XSNR 75 75 80 80 ns Exit SELF REFRESH to READ command t XSRD 200 200 200 200 t CK ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, I CC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifi cations and device operation are guaranteed for the full voltage range specifi ed. 3. Outputs measured with equivalent load: 50Ω Reference Point 30pF Output (VOUT) VTT 4. AC timing and I CC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CLK/CLK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level speci fi cations are as defi ned in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF by-pass capacitor. 7. V TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. V ID is the magnitude of the difference between the input level on CLK and the input level on CK#. 9. The value of V IX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. 10. I CC is dependent on output loading and cycle rates. Specifi ed values are obtained with minimum cycle time with the outputs open. 11. Enables on-chip refresh and address counters. 12. I CC specifi cations are tested after the device is properly initialized, and is averaged at the defi ned cycle rate. 13. This parameter is not tested but guaranteed by design. t A = 25°C, F= 1 MHz 14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V REF. 16. Inputs are not recognized as valid until V REF stabilizes once initialized, including SELF REFRESH mode, VREF must be powered within specifi ed range. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The intent of the Don't Care state after completion of the postamble is the DQS- driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above V IHDC(MIN) then it must not transition low (below VIHDC) prior to tDQSH(MIN). 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 22. MIN (t RC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other speci fi cations - t HP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8- DQ15 of each chip. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (t RFC [MIN]) else CKE is LOW (i.e., during standby). 160 140 120 100 VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum FIGURE A – PULL-DOWN CHARACTERISTICS FIGURE B – PULL-UP CHARACTERISTICS -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 VCCQ - VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum
14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be > 1V/ns (>2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. V CC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfi ed prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. The average cannot be below the 2.5V minimum. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V. 39. The voltage levels used are derived from a minimum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide signifi cantly different voltage values. 40. V IH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width < 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. 41. V CC and VCCQ must track each other. 42. t HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. t RPST end point and tRPRE begin point are not referenced to a specifi c voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, V CCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not refl ect this option. 46. When an input signal is HIGH or LOW, it is de fi ned as a steady state logic HIGH or LOW. 47. Random addressing changing 50% of data changing at every transfer. 48. Random addressing changing 100% of data changing at every transfer. 49.. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t RFC has been satisfi ed. FIGURE C – PULL-DOWN CHARACTERISTICS VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum FIGURE D – PULL-UP CHARACTERISTICS VCCQ - VOUT (V) IOUT (mA) Maximum Nominal high Nominal low Minimum -10 -20 -30 -40 -50 -60 -70 -80
15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 50. I CC2N specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifi es the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.” 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ± 100mV.
16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3
ORDERING INFORMATION
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA) WHITE ELECTRONIC DESIGNS CORP. DDR SDRAM CONFIGURATION, 32M x 64 2.5V Power Supply DATA RATE (Mbs): 200 = 100MHz/200Mbs 250 = 125MHz/250Mbs 266 = 133MHz/266Mbs 333 = 166MHz/333Mbs PACKAGE: B = 219 Plastic Ball Grid Array (PBGA), 25mm x 25mm DEVICE GRADE: M = Military -55°C to +125°C I = In dus tri al -40°C to +85°C C = Com mer cial 0°C to +70°C W 3E 32M 64 S - XXX B X ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Bottom View 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 T R P N M L K J H G F E D C B A 219 x ∅ 0.762 (0.030) NOM 1.27 (0.050) NOM 25.1 (0.988) MAX 19.05 (0.750) NOM 25.1 (0.988) MAX 19.05 (0.750) NOM 2.03 (0.080) MAX 0.61 (0.024) NOM Note: This package utlizes solderballs which contain lead: Sn63Pb37 If you require lead free solder ball packages, please contack WEDC for information
17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 Document Title 32M x 64 DDR SDRAM Multi-Chip Package, 219 PBGA
Revision History
Rev # History Release Date Status Rev 0 Initial Release August 2004 Advanced Rev 1 Changes (Pg. 1, 10, 16, 17)
1.1 Update capacitance table values
1.2 Add thermal resistance values
1.3 Changes status to Final
Rev 2 Changes (Pg. 1, 6, 11, 12, 16, 17)
2.1 Add 333Mbs data rate
Rev 3 Changes (Pg. 1, 3, 11, 16, 17)