W20NM50

STW20NM50 STMICROELECTRONICS | Alldatasheet

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N-CHANNEL 500V - 0.20Ω - 20A TO-247 MDmesh™Power MOSFET /c110 TYPICAL R DS (on) = 0.20Ω /c110 HIGH dv/dt AND AVALANCHE CAPABILITIES /c110 100% AVALANCHE TESTED /c110 LOW INPUT CAPACITANCE AND GATE CHARGE /c110 LOW GATE INPUT RESISTANCE /c110 TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS

DESCRIPTION

The MDmesh ™ is a new revolutionary MOSFET technology that associates the Multiple Drain pro- cess with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products.

APPLICATIONS

The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STW20NM50 500V < 0.25 Ω 20 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 500 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 500 V VGS Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 20 A ID Drain Current (continuous) at TC = 100°C 12.6 A IDM (/c108 ) Drain Current (pulsed) 80 A PTOT Total Dissipation at TC = 25°C 214 W Derating Factor 1.44 W/°C dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1) ISD ≤20A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. TO-247 INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS . Rthj-case Thermal Resistance Junction-case Max 0.585 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 10 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = 5 A, VDD = 35 V) 650 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 500 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 100 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 345V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 10A 0.20 0.25 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS > ID(on) x RDS(on)max, ID = 10A 10 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 1480 pF C oss Output Capacitance 285 pF C rss Reverse Transfer Capacitance 34 pF C oss eq. (2) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V 130 pF R G Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.6 Ω

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 250V, ID = 10 A R G = 4.7Ω VGS = 10 V (see test circuit, Figure 3) 24 ns tr Rise Time 16 ns Q g Total Gate Charge VDD = 400 V, ID = 20 A, VGS = 10 V 40 56 nC Q gs Gate-Source Charge 13 nC Q gd Gate-Drain Charge 19 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 400 V, ID = 20 A, R G = 4.7Ω, VGS = 10 V (see test circuit, Figure 5) 9n s tf Fall Time 8.5 ns tc Cross-over Time 23 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 20 A ISDM (2) Source-drain Current (pulsed) 80 A VSD (1) Forward On Voltage ISD = 20 A, VGS = 0 1.5 V trr Q rr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 20 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 350 4.6 ns µC A trr Q rr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 435 5.9 ns µC A Safe Operating Area

Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations Transconductance Transfer CharacteristicsOutput Characteristics

Source-drain Diode Forward Characteristics Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm. inch A 4.85 5.15 0.19 0.20 D 2.20 2.60 0.08 0.10 E 0.40 0.80 0.015 0.03 F 1 1.40 0.04 0.05 F1 3 0.11 F2 2 0.07 F3 2 2.40 0.07 0.09 F4 3 3.40 0.11 0.13 G 10.90 0.43 H 15.45 15.75 0.60 0.62 L 19.85 20.15 0.78 0.79 L1 3.70 4.30 0.14 0.17 L2 18.50 0.72 L3 14.20 14.80 0.56 0.58 L4 34.60 1.36 L5 5.50 0.21 M 2 3 0.07 0.11 V 5º5 º V2 60º 60º Dia 3.55 3.65 0.14 0.143 TO-247 MECHANICAL DATA

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