STW20NC50 STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 500V - 0.22Ω - 18.4A TO-247 PowerMesh™II MOSFET ■ TYPICAL R DS (on) = 0.22Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ NEW HIGH VOLTAGE BENCHMARK ■ GATE CHARGE MINIMIZED

DESCRIPTION

The PowerMESH ™ II is the evolution of the first generation of MESH OVERLAY™. The layout re- finements introduced greatly improve the Ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness.

APPLICATIONS

■ SWITH MODE LOW POWER SUPPLIES (SMPS) ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVES ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STW20NC50 500V < 0.27 Ω 18.4A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 500 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 500 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 18.4 A ID Drain Current (continuos) at TC = 100°C 11.6 A IDM (● ) Drain Current (pulsed) 73.6 A PTOT Total Dissipation at TC = 25°C 220 W Derating Factor 1.75 W/°C dv/dt(1) Peak Diode Recovery voltage slope 2 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤18.4A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. TO-247 INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC Rthj-case Thermal Resistance Junction-case Max 0.57 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.1 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 20 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 960 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 500 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 234V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 9 A 0.22 0.27 Ω ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS =1 0 V 18.4 A Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max, ID =9 A 18 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2980 pF C oss Output Capacitance 410 pF C rss Reverse Transfer Capacitance 58 pF

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 250V, ID = 10A R G = 4.7Ω VGS = 10V (see test circuit, Figure 3) 29 ns tr Rise Time 21 ns Q g Total Gate Charge VDD = 400V, ID = 20A, VGS = 10V 95 128 nC Q gs Gate-Source Charge 14.7 nC Q gd Gate-Drain Charge 41.7 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 400V, ID = 20A, R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 5) 20 ns tf Fall Time 21 ns tc Cross-over Time 58 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 18.4 A ISDM (2) Source-drain Current (pulsed) 73.6 A VSD (1) Forward On Voltage ISD = 18.4A, VGS = 0 1.6 V trr Reverse Recovery Time ISD = 20A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 480 ns Q rr Reverse Recovery Charge 5 µC IRRM Reverse Recovery Current 21 A Thermal ImpedenceSafe Operating Area

Static Drain-source On Resistance Output Characteristics Transfer Characteristics Transconductance Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Thereshold Voltage vs Temp. Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm. inch A 4.85 5.15 0.19 0.20 D 2.20 2.60 0.08 0.10 E 0.40 0.80 0.015 0.03 F 1 1.40 0.04 0.05 F1 3 0.11 F2 2 0.07 F3 2 2.40 0.07 0.09 F4 3 3.40 0.11 0.13 G 10.90 0.43 H 15.45 15.75 0.60 0.62 L 19.85 20.15 0.78 0.79 L1 3.70 4.30 0.14 0.17 L2 18.50 0.72 L3 14.20 14.80 0.56 0.58 L4 34.60 1.36 L5 5.50 0.21 M 2 3 0.07 0.11 V 5º5 º V2 60º 60º Dia 3.55 3.65 0.14 0.143 TO-247 MECHANICAL DATA

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