BF1009SW INFINEON | Alldatasheet

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Technical content

1 Jun-28-2001

Silicon N-Channel MOSFET Tetrode /G01 For low noise, high gain controlled input stages up to 1GHz /G01 Operating voltage 9V /G01 Integrated bias network VPS05605 EHA07215 GND Drain AGC HF Input HF Output +D C ESD: Electrostatic discharge sensitive device, observe handling precaution! Type Marking Pin Configuration Package BF1009SW JLs 1 = D 2 = S 3 = G1 4 = G2 SOT343 Maximum Ratings Parameter Symbol Value Unit VDS 12Drain-source voltage V mA25IDContinuos drain current Gate 1/gate 2 peak source current 10±IG1/2SM +VG1SE 3Gate 1 (external biasing) V mWPtotTotal power dissipation, TS /G01 76 °C 200 Storage temperature °C-55 ... 150Tstg Tch 150Channel temperature Thermal Resistance Channel - soldering point1) Rthchs /G01 280 K/W 1For calculation of RthJA please refer to Application Note Thermal Resistance Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode.

2 Jun-28-2001

Electrical Characteristics at TA = 25°C, unless otherwise specified. Parameter Symbol Values Unit min. typ. max. DC characteristics Drain-source breakdown voltage ID = 300 µA, VG1S = 0 V, VG2S = 0 V V-V(BR)DS -16 Gate 1 - source breakdown voltage +IG1S = 10 mA, VG2S = 0 V, VDS = 0 V - 12+V(BR)G1SS 8 Gate 2 source breakdown voltage ±IG2S = 10 mA, VG1S = 0 V, VDS = 0 V - 1610±V(BR)G2SS Gate 1 source current VG1S = 6 V, VG2S = 0 V - - µA60+IG1SS Gate 2 source leakage current ±VG2S = 8 V, VG1S = 0 V, VDS = 0 V ±IG2SS -- nA50 IDSS - 500 µA-Drain current VDS = 9 V, VG1S = 0 , VG2S = 6 V IDSO 10 14Operating current (selfbiased) VDS = 9 V, VG2S = 6 V mA19 VG2S(p) - 0.9 - VGate 2-source pinch-off voltage VDS = 9 V, ID = 100 µA AC characteristics Forward transconductance (self biased) VDS = 9 V, VG2S = 6 V gfs 26 30 - mS Gate 1-input capacitance (self biased) VDS = 9 V, VG2S = 6 V, f = 1 MHz Cg1ss - 2.1 2.7 pF Output capacitance (self biased) VDS = 9 V, VG2S = 6 V, f = 1 MHz Cdss - 0.9 - Power gain (self biased) VDS = 9 V, VG2S = 6 V, f = 800 MHz Gps 18 22 - dB Noise figure (self biased) VDS = 9 V, VG2S = 6 V, f = 800 MHz F800 - 1.4 - Gain control range (self biased) VDS = 9 V, VG2S = 6 ... 0V, f = 800 MHz /G01 Gps 40 50 -

3 Jun-28-2001

Total power dissipation Ptot = f (TS) 0 20 40 60 80 100 120 °C 150 TS 100 150 200 mW 300 Ptot Drain current ID = f (VG2S) VG2S mA ID Forward transfer admittance | Y21 | = f (VG2S) VG2S mS |Y21| Insertion power gain | S21 | 2 = f (VG2S) VG2S -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 dB | S21|2

4 Jun-28-2001

Gate 1 input capacitance Cg1ss = f (Vg2s) f = 200MHz VG2S 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pF 3.0 Cg1ss Output capacitance Cdss = f (VG2S) f = 200MHz VG2S 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pF 3.0 Cdss